From nobody Tue Sep 16 10:53:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 961FEC46467 for ; Thu, 5 Jan 2023 03:47:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231211AbjAEDqz (ORCPT ); Wed, 4 Jan 2023 22:46:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231179AbjAEDpi (ORCPT ); Wed, 4 Jan 2023 22:45:38 -0500 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2086.outbound.protection.outlook.com [40.107.244.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E77214FD5D for ; Wed, 4 Jan 2023 19:44:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ByHZIRi4vnTnbG0yUBD3kwAti18qZQn9EumNPAdz5ReXnhFfYFJElDgFuTQV/pBCdpuyXtZqm4fA82Oodf70G6Q5YUN0X2HADOabYmK1flgGWqx/8PvnyJtEAFWcOHkYaySPaMf7b1y1jhokQk0FVZuuktnwY2l97goFfiFxyXgbyromoj44u6VVzBZaMxSf9ogukxjTgYRxxA2j37xc8F+GkuIxXPt6KB4r3y+IgwgV5n43t9oHoqyoULSU5N15vetSBtBCRH1mbtlxjMCVGV855PgQuULWJMejSEWbov4NiOyIOBe00qhPG1UMsJfVP4iO7YhW0duLAIzdmYYTuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/wm2H3gExGsTdrmy8S08Cb0DAScutGkO1T5brQlLz84=; b=hBFfl2BXSKEa+DTC9cD4JEZJIEDoAv9tP0gUow2vNLYmk7KtEpzNwKZm1iknBEBsVLbh3UFebPf493datG41GgB2zcOdt39IR1IZ143X+jdq+2zA2B/ZcABBX70PrnarI6eQN/LkARkfgcGxo3UtA/+hp2YpSwiNG38G7CnIUzPpZ9sWfSpoduKxJRTI0raZ3oLFdGbl5kYpui22CuMb+M7Syih0dmMWvYCODHReBx2bRtcmIuh5r8pzQxaASFSY0BSMBV6GOzC3bTyMbt2t+MhjpJWnWzN7RNj6eLXYMEvjp+zd4zAqboPvpQA4EM9yajrmzWUyOJRFMz8HP6elfg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/wm2H3gExGsTdrmy8S08Cb0DAScutGkO1T5brQlLz84=; b=ZMTgZfX34wOHLbeVCB7Ei4JBNoLFXDnVS6DtPcWPQbLZqgUH6f70DsXt43KrpnDwTdSO2HCSuwj9ePMZ2M4b69XJBA6pzbPhQvzMZMwEyhDPER45xYWNczP0aR1jVjbXEwFq5jzXGffdRQe0XKLLxckCSvsTwQOJpbEaWKygG54= Received: from BN9PR03CA0078.namprd03.prod.outlook.com (2603:10b6:408:fc::23) by PH7PR12MB6612.namprd12.prod.outlook.com (2603:10b6:510:210::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5944.19; Thu, 5 Jan 2023 03:44:52 +0000 Received: from BN8NAM11FT023.eop-nam11.prod.protection.outlook.com (2603:10b6:408:fc:cafe::76) by BN9PR03CA0078.outlook.office365.com (2603:10b6:408:fc::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5986.14 via Frontend Transport; Thu, 5 Jan 2023 03:44:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT023.mail.protection.outlook.com (10.13.177.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5986.14 via Frontend Transport; Thu, 5 Jan 2023 03:44:51 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 4 Jan 2023 21:44:49 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Lazar Lijo , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v6 31/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX8 Date: Wed, 4 Jan 2023 21:43:05 -0600 Message-ID: <20230105034327.1439-32-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT023:EE_|PH7PR12MB6612:EE_ X-MS-Office365-Filtering-Correlation-Id: 03543d44-cd72-4147-c16d-08daeecf33a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W2S6LXRRJ2L3bmVLap8Rnwd3H7vBbP6F/iJrPUBj/d3KKUxw9ZxxV475y8kuRCOP59k0aPLg99dl6V76by77tmImmaQgUlN5xFZ5tCbuGFVC2tNoJAsG7+D1zK0SUP7SPeTVjzrjJ5jZjojcEFmsMf2DzkF8ZYE8ZvDU20PTsgLEHMkKbQCHKl+Ntnzt4lZgtbFmnR3GRpjwwkXl+CGL9vgvZlyTaZ/tQBaKUm0qi+84RkLB98QiynHcGbDXJaby3zkjPJPSsLwliKDM2fWp/5xvsGMcgJ0oK5tAut3Aw206d6sUAfBWbel+R9GRxfwenQ+uC3/B2ZeFg26O9bocV8p7ETac9rhtBi9j/OpewXu2yZ/F8EPMGRKeOl/D4N5PTXURmWDSerX1B5IxH6YALBcYxgiLkg4z5AMQihyAm7eI+Dp2gXBKz6dhq5y3iSeQPd0k3UcNtFLO+K+EEcpqYOgYktiDxSfMtG8/IjPaKNgfAj790MEBqptG5xHTAy/LdXAyx7u8z/frLb1P6wL6pBe5CTKdGGp7jEi3HombHTcXLikvIjHo49f9v3j0C+JCa0IcHkLyy64luGpiPbF8gdiu8Is20dTpSOFINP8jY1z+RTZCb0HJ0YM2/DXc1Y825qp4B1iaDtMO6cihsPinpqV1TEAl8niJOy+/imjufLBOY38om1phEzabpEVVxeTj2rHObmgGFCv2r7xpWCDtNB2Wt9hjYhGzrQ7/x87tU5hAwVOFGDXT9ep9bxLHW0eXw4Z+MtzczaKDQ+d+iO8k5g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(136003)(396003)(376002)(451199015)(36840700001)(40470700004)(46966006)(83380400001)(2616005)(1076003)(47076005)(336012)(36860700001)(426003)(40480700001)(86362001)(40460700003)(82310400005)(81166007)(356005)(82740400003)(36756003)(110136005)(54906003)(316002)(2906002)(41300700001)(44832011)(8936002)(70586007)(4326008)(8676002)(70206006)(26005)(186003)(478600001)(5660300002)(6666004)(16526019)(7696005)(81973001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:51.8241 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03543d44-cd72-4147-c16d-08daeecf33a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6612 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unloading. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 94 ++++++++++----------------- 1 file changed, 33 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/am= dgpu/gfx_v8_0.c index d47135606e3e..04577e5234ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -924,20 +924,14 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *= ring, long timeout) =20 static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) { - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw =3D NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw =3D NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw =3D NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw =3D NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw =3D NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); if ((adev->asic_type !=3D CHIP_STONEY) && (adev->asic_type !=3D CHIP_TOPAZ)) - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw =3D NULL; + amdgpu_ucode_release(&adev->gfx.mec2_fw); =20 kfree(adev->gfx.rlc.register_list_format); } @@ -989,18 +983,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_devi= ce *adev) =20 if (adev->asic_type >=3D CHIP_POLARIS10 && adev->asic_type <=3D CHIP_POLA= RIS12) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name); - err =3D request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err =3D=3D -ENOENT) { + err =3D amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); + if (err =3D=3D -ENODEV) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err =3D request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); } } else { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err =3D request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); } - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.pfp_fw); if (err) goto out; cp_hdr =3D (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->dat= a; @@ -1009,18 +1000,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_de= vice *adev) =20 if (adev->asic_type >=3D CHIP_POLARIS10 && adev->asic_type <=3D CHIP_POLA= RIS12) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name); - err =3D request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err =3D=3D -ENOENT) { + err =3D amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); + if (err =3D=3D -ENODEV) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err =3D request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); } } else { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err =3D request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); } - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.me_fw); if (err) goto out; cp_hdr =3D (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; @@ -1030,18 +1018,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_de= vice *adev) =20 if (adev->asic_type >=3D CHIP_POLARIS10 && adev->asic_type <=3D CHIP_POLA= RIS12) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name); - err =3D request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err =3D=3D -ENOENT) { + err =3D amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); + if (err =3D=3D -ENODEV) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err =3D request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); } } else { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err =3D request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); } - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.ce_fw); if (err) goto out; cp_hdr =3D (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; @@ -1060,10 +1045,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_dev= ice *adev) adev->virt.chained_ib_support =3D false; =20 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err =3D request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); if (err) goto out; - err =3D amdgpu_ucode_validate(adev->gfx.rlc_fw); rlc_hdr =3D (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->da= ta; adev->gfx.rlc_fw_version =3D le32_to_cpu(rlc_hdr->header.ucode_version); adev->gfx.rlc_feature_version =3D le32_to_cpu(rlc_hdr->ucode_feature_vers= ion); @@ -1110,18 +1094,15 @@ static int gfx_v8_0_init_microcode(struct amdgpu_de= vice *adev) =20 if (adev->asic_type >=3D CHIP_POLARIS10 && adev->asic_type <=3D CHIP_POLA= RIS12) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name); - err =3D request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err =3D=3D -ENOENT) { + err =3D amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); + if (err =3D=3D -ENODEV) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); - err =3D request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); } } else { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); - err =3D request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); } - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.mec_fw); if (err) goto out; cp_hdr =3D (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->dat= a; @@ -1132,19 +1113,16 @@ static int gfx_v8_0_init_microcode(struct amdgpu_de= vice *adev) (adev->asic_type !=3D CHIP_TOPAZ)) { if (adev->asic_type >=3D CHIP_POLARIS10 && adev->asic_type <=3D CHIP_POL= ARIS12) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name); - err =3D request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); - if (err =3D=3D -ENOENT) { + err =3D amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); + if (err =3D=3D -ENODEV) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - err =3D request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); } } else { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - err =3D request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + err =3D amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); } if (!err) { - err =3D amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; cp_hdr =3D (const struct gfx_firmware_header_v1_0 *) adev->gfx.mec2_fw->data; adev->gfx.mec2_fw_version =3D @@ -1219,18 +1197,12 @@ static int gfx_v8_0_init_microcode(struct amdgpu_de= vice *adev) dev_err(adev->dev, "gfx8: Failed to load firmware \"%s\"\n", fw_name); - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw =3D NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw =3D NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw =3D NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw =3D NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw =3D NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw =3D NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); } return err; } --=20 2.34.1