From nobody Sat Sep 21 08:37:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C3C1C54EBD for ; Thu, 5 Jan 2023 01:08:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230365AbjAEBH7 (ORCPT ); Wed, 4 Jan 2023 20:07:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230162AbjAEBHr (ORCPT ); Wed, 4 Jan 2023 20:07:47 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7D61479C2; Wed, 4 Jan 2023 17:07:22 -0800 (PST) X-UUID: 4c0ee232f52844a7bfd6df4ec49bfa14-20230105 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=/tajBNzIihAGN7nzWbirFSCOw1aUlX0N1cIhsjxveVg=; b=ingUcWZAeqfPszYqiKbaJn7kYrNOvuVQdn3k7VDlhkCvNF2N0ue8+k8Dd+VyWw0eC2dRjuh3GrYpfJ2nrPUDNOAYhxNGi21xtj51v7Hl1Bsrmnlhqy/UWt1puFoPPstqtcXNeHyXUbr5+LazRclv0iir/5OtxZaKoz2bWidaAWc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.16,REQID:13c6b6c4-bffe-45c5-a05a-11544e452c1e,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:09771b1,CLOUDID:9bc6d3f4-ff42-4fb0-b929-626456a83c14,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: 4c0ee232f52844a7bfd6df4ec49bfa14-20230105 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 924514787; Thu, 05 Jan 2023 09:07:17 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 5 Jan 2023 09:07:16 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 5 Jan 2023 09:07:15 +0800 From: Biao Huang To: Andrew Lunn , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Richard Cochran , , , , , Biao Huang , , Subject: [PATCH v8 1/2] stmmac: dwmac-mediatek: remove the dwmac_fix_mac_speed Date: Thu, 5 Jan 2023 09:07:11 +0800 Message-ID: <20230105010712.10116-2-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105010712.10116-1-biao.huang@mediatek.com> References: <20230105010712.10116-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In current driver, MAC will always enable 2ns delay in RGMII mode, but that's not the correct usage. Remove the dwmac_fix_mac_speed() in driver, and recommend "rgmii-id" for phy-mode in device tree. Fixes: f2d356a6ab71 ("stmmac: dwmac-mediatek: add support for mt8195") Reviewed-by: Andrew Lunn Signed-off-by: Biao Huang --- .../ethernet/stmicro/stmmac/dwmac-mediatek.c | 26 ------------------- 1 file changed, 26 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers= /net/ethernet/stmicro/stmmac/dwmac-mediatek.c index d42e1afb6521..2f7d8e4561d9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -90,7 +90,6 @@ struct mediatek_dwmac_plat_data { struct mediatek_dwmac_variant { int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat); int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat); - void (*dwmac_fix_mac_speed)(void *priv, unsigned int speed); =20 /* clock ids to be requested */ const char * const *clk_list; @@ -443,32 +442,9 @@ static int mt8195_set_delay(struct mediatek_dwmac_plat= _data *plat) return 0; } =20 -static void mt8195_fix_mac_speed(void *priv, unsigned int speed) -{ - struct mediatek_dwmac_plat_data *priv_plat =3D priv; - - if ((phy_interface_mode_is_rgmii(priv_plat->phy_mode))) { - /* prefer 2ns fixed delay which is controlled by TXC_PHASE_CTRL, - * when link speed is 1Gbps with RGMII interface, - * Fall back to delay macro circuit for 10/100Mbps link speed. - */ - if (speed =3D=3D SPEED_1000) - regmap_update_bits(priv_plat->peri_regmap, - MT8195_PERI_ETH_CTRL0, - MT8195_RGMII_TXC_PHASE_CTRL | - MT8195_DLY_GTXC_ENABLE | - MT8195_DLY_GTXC_INV | - MT8195_DLY_GTXC_STAGES, - MT8195_RGMII_TXC_PHASE_CTRL); - else - mt8195_set_delay(priv_plat); - } -} - static const struct mediatek_dwmac_variant mt8195_gmac_variant =3D { .dwmac_set_phy_interface =3D mt8195_set_interface, .dwmac_set_delay =3D mt8195_set_delay, - .dwmac_fix_mac_speed =3D mt8195_fix_mac_speed, .clk_list =3D mt8195_dwmac_clk_l, .num_clks =3D ARRAY_SIZE(mt8195_dwmac_clk_l), .dma_bit_mask =3D 35, @@ -619,8 +595,6 @@ static int mediatek_dwmac_common_data(struct platform_d= evice *pdev, plat->bsp_priv =3D priv_plat; plat->init =3D mediatek_dwmac_init; plat->clks_config =3D mediatek_dwmac_clks_config; - if (priv_plat->variant->dwmac_fix_mac_speed) - plat->fix_mac_speed =3D priv_plat->variant->dwmac_fix_mac_speed; =20 plat->safety_feat_cfg =3D devm_kzalloc(&pdev->dev, sizeof(*plat->safety_feat_cfg), --=20 2.25.1 From nobody Sat Sep 21 08:37:11 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6F23C53210 for ; Thu, 5 Jan 2023 01:08:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230209AbjAEBIL (ORCPT ); Wed, 4 Jan 2023 20:08:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230172AbjAEBHr (ORCPT ); Wed, 4 Jan 2023 20:07:47 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4ED42F7B1; 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Thu, 05 Jan 2023 09:07:18 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 5 Jan 2023 09:07:17 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 5 Jan 2023 09:07:16 +0800 From: Biao Huang To: Andrew Lunn , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Maxime Coquelin , Richard Cochran , , , , , "Biao Huang" , , Subject: [PATCH v8 2/2] arm64: dts: mt8195: Add Ethernet controller Date: Thu, 5 Jan 2023 09:07:12 +0800 Message-ID: <20230105010712.10116-3-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105010712.10116-1-biao.huang@mediatek.com> References: <20230105010712.10116-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Ethernet controller node for mt8195. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Andrew Lunn Signed-off-by: Biao Huang --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 77 ++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 92 ++++++++++++++++++++ 2 files changed, 169 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot= /dts/mediatek/mt8195-demo.dts index 4fbd99eb496a..6a48c135f0da 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -78,6 +78,23 @@ optee_reserved: optee@43200000 { }; }; =20 +ð { + phy-mode =3D"rgmii-id"; + phy-handle =3D <ðernet_phy0>; + snps,reset-gpio =3D <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us =3D <0 10000 80000>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <ð_default_pins>; + pinctrl-1 =3D <ð_sleep_pins>; + status =3D "okay"; + + mdio { + ethernet_phy0: ethernet-phy@1 { + reg =3D <0x1>; + }; + }; +}; + &i2c6 { clock-frequency =3D <400000>; pinctrl-0 =3D <&i2c6_pins>; @@ -258,6 +275,66 @@ &mt6359_vsram_others_ldo_reg { }; =20 &pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux =3D , + , + , + ; + drive-strength =3D ; + }; + pins-cc { + pinmux =3D , + , + , + ; + drive-strength =3D ; + }; + pins-rxd { + pinmux =3D , + , + , + ; + }; + pins-mdio { + pinmux =3D , + ; + input-enable; + }; + pins-power { + pinmux =3D , + ; + output-high; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux =3D , + , + , + ; + }; + pins-cc { + pinmux =3D , + , + , + ; + }; + pins-rxd { + pinmux =3D , + , + , + ; + }; + pins-mdio { + pinmux =3D , + ; + input-disable; + bias-disable; + }; + }; + gpio_keys_pins: gpio-keys-pins { pins { pinmux =3D ; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 5d31536f4c48..28b3ebd145bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1046,6 +1046,98 @@ spis1: spi@1101e000 { status =3D "disabled"; }; =20 + eth: ethernet@11021000 { + compatible =3D "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg =3D <0 0x11021000 0 0x4000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clock-names =3D "axi", + "apb", + "mac_main", + "ptp_ref", + "rmii_internal", + "mac_cg"; + clocks =3D <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + assigned-clocks =3D <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents =3D <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg =3D <&infracfg_ao>; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + snps,clk-csr =3D <0>; + status =3D "disabled"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0x7>; + snps,rd_osr_lmt =3D <0x7>; + snps,blen =3D <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,priority =3D <0x0>; + }; + queue1 { + snps,weight =3D <0x11>; + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + queue2 { + snps,weight =3D <0x12>; + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + queue3 { + snps,weight =3D <0x13>; + snps,dcb-algorithm; + snps,priority =3D <0x3>; + }; + }; + }; + xhci0: usb@11200000 { compatible =3D "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; --=20 2.25.1