From nobody Tue Sep 16 08:40:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A930C4332F for ; Wed, 4 Jan 2023 18:06:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240046AbjADSF6 (ORCPT ); Wed, 4 Jan 2023 13:05:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239903AbjADSFu (ORCPT ); Wed, 4 Jan 2023 13:05:50 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7EC5108A; Wed, 4 Jan 2023 10:05:49 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 43A906179B; Wed, 4 Jan 2023 18:05:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CF8A6C43396; Wed, 4 Jan 2023 18:05:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1672855548; bh=SpxUfboVfaSWtvMSqW0B+NZAeloH/U4lZdg9RHU4N3c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MZyaK10kBqxH/xTpI6ZGaW6VYehCAWKr4pIlLC7OEE5Psip32Y1FhtVa0esLwfIWY Ucp6yTs8EtQAPPX4mLo3Z0ezzgA37F2YHznb+fLhEx2N2Vsiozsi1dpb98R05e6Ji3 4lWe9XtR83YxVnriLYZOjZoD2Sp03q5B3sQZFdiYvC0KSoh0qTalDm+0MMI1dNhr8z Mu2JoS+NnX8D5IS6VbhLD60LXXuhyR3tndeHWHxA+zpNdiLGT55SteqzINdxY19xN0 huKDkhxNkaJr+cINkBg+nXZEYk/SkmnOnyfa/Aav1Ilklsd5dRp5MyPBymK33013/p t9ImPPAILndaA== From: Conor Dooley To: palmer@dabbelt.com Cc: conor@kernel.org, Conor Dooley , Ley Foon Tan , Sudeep Holla , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Alex Shi , Yanteng Si , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v1 1/2] dt-bindings: arm: move cpu-capacity to a shared loation Date: Wed, 4 Jan 2023 18:05:13 +0000 Message-Id: <20230104180513.1379453-2-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230104180513.1379453-1-conor@kernel.org> References: <20230104180513.1379453-1-conor@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4078; i=conor.dooley@microchip.com; h=from:subject; bh=EHhLKTpL8b24ylcqPJCu6roLTdkZjz8WegHWiaxDAkY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlb91+c0cf+KyCreJNWx16FJ+++CThmLNT2+X5p868tcjfN H29431HKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJ/O5n+O/29NHEsKfOfOqBdjd+b/ /64NeTzX2i7xX/C1jdWFCg47COkWGp9LYpxfppoocYSyYqhum2eh2Y86/V/sqUG2sjGEKfsDMCAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Conor Dooley RISC-V uses the same generic topology code as arm64 & while there currently exists no binding for cpu-capacity on RISC-V, the code paths can be hit if the property is present. Move the documentation of cpu-capacity to a shared location, ahead of defining a binding for capacity-dmips-mhz on RISC-V. Update some references to this document in the process. Signed-off-by: Conor Dooley Acked-by: Rob Herring Reviewed-by: Ley Foon Tan Reviewed-by: Yanteng Si --- I wasn't sure what to do with reference [1], but since the property will be the same on RISC-V, I left it as is. --- Documentation/devicetree/bindings/arm/cpus.yaml | 2 +- .../devicetree/bindings/{arm =3D> cpu}/cpu-capacity.txt | 4 ++-- Documentation/scheduler/sched-capacity.rst | 2 +- Documentation/translations/zh_CN/scheduler/sched-capacity.rst | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/{arm =3D> cpu}/cpu-capacity.txt (= 98%) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentatio= n/devicetree/bindings/arm/cpus.yaml index 01b5a9c689a2..a7586295a6f5 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -257,7 +257,7 @@ properties: =20 capacity-dmips-mhz: description: - u32 value representing CPU capacity (see ./cpu-capacity.txt) in + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. =20 diff --git a/Documentation/devicetree/bindings/arm/cpu-capacity.txt b/Docum= entation/devicetree/bindings/cpu/cpu-capacity.txt similarity index 98% rename from Documentation/devicetree/bindings/arm/cpu-capacity.txt rename to Documentation/devicetree/bindings/cpu/cpu-capacity.txt index cc5e190390b7..f28e1adad428 100644 --- a/Documentation/devicetree/bindings/arm/cpu-capacity.txt +++ b/Documentation/devicetree/bindings/cpu/cpu-capacity.txt @@ -1,12 +1,12 @@ =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -ARM CPUs capacity bindings +CPU capacity bindings =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 1 - Introduction =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -ARM systems may be configured to have cpus with different power/performance +Some systems may be configured to have cpus with different power/performan= ce characteristics within the same chip. In this case, additional information= has to be made available to the kernel for it to be aware of such differences = and take decisions accordingly. diff --git a/Documentation/scheduler/sched-capacity.rst b/Documentation/sch= eduler/sched-capacity.rst index 805f85f330b5..8e2b8538bc2b 100644 --- a/Documentation/scheduler/sched-capacity.rst +++ b/Documentation/scheduler/sched-capacity.rst @@ -260,7 +260,7 @@ for that purpose. =20 The arm and arm64 architectures directly map this to the arch_topology dri= ver CPU scaling data, which is derived from the capacity-dmips-mhz CPU binding= ; see -Documentation/devicetree/bindings/arm/cpu-capacity.txt. +Documentation/devicetree/bindings/cpu/cpu-capacity.txt. =20 3.2 Frequency invariance ------------------------ diff --git a/Documentation/translations/zh_CN/scheduler/sched-capacity.rst = b/Documentation/translations/zh_CN/scheduler/sched-capacity.rst index 3a52053c29dc..e07ffdd391d3 100644 --- a/Documentation/translations/zh_CN/scheduler/sched-capacity.rst +++ b/Documentation/translations/zh_CN/scheduler/sched-capacity.rst @@ -233,7 +233,7 @@ CFS=E8=B0=83=E5=BA=A6=E7=B1=BB=E5=9F=BA=E4=BA=8E=E5=AE= =9E=E4=BD=93=E8=B4=9F=E8=BD=BD=E8=B7=9F=E8=B8=AA=E6=9C=BA=E5=88=B6=EF=BC=88= Per-Entity Load Tracking, PELT=EF=BC=89 =20 arm=E5=92=8Carm64=E6=9E=B6=E6=9E=84=E7=9B=B4=E6=8E=A5=E6=8A=8A=E8=BF=99=E4= =B8=AA=E4=BF=A1=E6=81=AF=E6=98=A0=E5=B0=84=E5=88=B0arch_topology=E9=A9=B1= =E5=8A=A8=E7=9A=84CPU scaling=E6=95=B0=E6=8D=AE=E4=B8=AD=EF=BC=88=E8=AF=91= =E6=B3=A8=EF=BC=9A=E5=8F=82=E8=80=83 arch_topology.h=E7=9A=84percpu=E5=8F=98=E9=87=8Fcpu_scale=EF=BC=89=EF=BC= =8C=E5=AE=83=E6=98=AF=E4=BB=8Ecapacity-dmips-mhz CPU binding=E4=B8=AD=E8=A1= =8D=E7=94=9F=E8=AE=A1=E7=AE=97 -=E5=87=BA=E6=9D=A5=E7=9A=84=E3=80=82=E5=8F=82=E8=A7=81Documentation/device= tree/bindings/arm/cpu-capacity.txt=E3=80=82 +=E5=87=BA=E6=9D=A5=E7=9A=84=E3=80=82=E5=8F=82=E8=A7=81Documentation/device= tree/bindings/cpu/cpu-capacity.txt=E3=80=82 =20 3.2 =E9=A2=91=E7=8E=87=E4=B8=8D=E5=8F=98=E6=80=A7 -------------- --=20 2.39.0 From nobody Tue Sep 16 08:40:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E98F0C4332F for ; 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d=kernel.org; s=k20201202; t=1672855551; bh=7hi84JBUzFJsCseSml62aqokn8J6yG6QNrOsogIOB7E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VN0/UaFFVZqOMHF3674yqncE3YyRqpXDi5c4Zhr48kmPb5BzW1m0UyuTiRIPHTwJg 6ohuZFHYCy0Uz7JEkrOAPmJp6q3t2prjNBbnCCfNlUrPifBiZX/pgi8euV7gQdOoHP u2v2FU+cSLVuTKpaCiiBL0znJ/bqgcFgJPj811JgYfwkqFLv0/noGd2P054fbFSkum 27soQ27+YV2HwVuhOTPDmw4Uyao4A8MUh0qiDqJFteLKnA99okpwEfjT/aMBXpvWka G0/T0SrhpxzhLwOVaXNTAqDb8xn/dI3ZL3EJewf+ZPwTJfM1E7q1aRvADplGsGgBvl /27kkR1aysMtw== From: Conor Dooley To: palmer@dabbelt.com Cc: conor@kernel.org, Conor Dooley , Ley Foon Tan , Sudeep Holla , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet , Alex Shi , Yanteng Si , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org Subject: [PATCH v1 2/2] dt-bindings: riscv: add a capacity-dmips-mhz cpu property Date: Wed, 4 Jan 2023 18:05:14 +0000 Message-Id: <20230104180513.1379453-3-conor@kernel.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230104180513.1379453-1-conor@kernel.org> References: <20230104180513.1379453-1-conor@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1179; i=conor.dooley@microchip.com; h=from:subject; bh=o07jjdwBTatvOwh4zgdAJ4rsKJozF7vor3izbX7Vg94=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDMlb91/MCL97v/HRZP+ZQQoTbpy8ObPJZKryPqsFBjsulS4U ZU1Y21HKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJ3H/D8FdGeDLTxqseKd6GMz+vn2 dw6/qlJwmcR85k5/KW588P13jA8Fc6rkupS13k7O3cN8f+q/6375qlbHJd6PmVowdZAyzu/uECAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Since commit 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") RISC-V has used the generic arch topology code, which provides for disparate CPU capacities. We never defined a binding to acquire this information from the DT though, so document the one already used by the generic arch topology code: "capacity-dmips-mhz". Signed-off-by: Conor Dooley Acked-by: Rob Herring Reviewed-by: Ley Foon Tan --- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index c6720764e765..2480c2460759 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -114,6 +114,12 @@ properties: List of phandles to idle state nodes supported by this hart (see ./idle-states.yaml). =20 + capacity-dmips-mhz: + description: + u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in + DMIPS/MHz, relative to highest capacity-dmips-mhz + in the system. + required: - riscv,isa - interrupt-controller --=20 2.39.0