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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF00010207.mail.protection.outlook.com (10.167.241.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5944.8 via Frontend Transport; Wed, 4 Jan 2023 16:43:07 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 4 Jan 2023 10:42:59 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Lazar Lijo , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v5 18/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX11 Date: Wed, 4 Jan 2023 10:40:07 -0600 Message-ID: <20230104164042.30271-19-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230104164042.30271-1-mario.limonciello@amd.com> References: <20230104164042.30271-1-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00010207:EE_|MW4PR12MB6780:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c200f4d-f517-4b95-a0ea-08daee72c1e5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jan 2023 16:43:07.2455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c200f4d-f517-4b95-a0ea-08daee72c1e5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00010207.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6780 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper will provide symmetery on unload. Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 102 +++++++++---------------- drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 7 +- 2 files changed, 37 insertions(+), 72 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/a= mdgpu/gfx_v11_0.c index a56c6e106d00..ce018331b093 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -431,18 +431,37 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring = *ring, long timeout) =20 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev) { - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw =3D NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw =3D NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw =3D NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw =3D NULL; + amdgpu_ucode_release(adev->gfx.pfp_fw); + amdgpu_ucode_release(adev->gfx.me_fw); + amdgpu_ucode_release(adev->gfx.rlc_fw); + amdgpu_ucode_release(adev->gfx.mec_fw); =20 kfree(adev->gfx.rlc.register_list_format); } =20 +static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, char *= ucode_prefix) +{ + const struct psp_firmware_header_v1_0 *toc_hdr; + int err =3D 0; + char fw_name[40]; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); + err =3D amdgpu_ucode_load(adev, &adev->psp.toc_fw, fw_name); + if (err) + goto out; + + toc_hdr =3D (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->da= ta; + adev->psp.toc.fw_version =3D le32_to_cpu(toc_hdr->header.ucode_version); + adev->psp.toc.feature_version =3D le32_to_cpu(toc_hdr->sos.fw_version); + adev->psp.toc.size_bytes =3D le32_to_cpu(toc_hdr->header.ucode_size_bytes= ); + adev->psp.toc.start_addr =3D (uint8_t *)toc_hdr + + le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); + return 0; +out: + amdgpu_ucode_release(adev->psp.toc_fw); + return err; +} + static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) { char fw_name[40]; @@ -457,10 +476,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_devi= ce *adev) amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_= prefix)); =20 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); - err =3D request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.pfp_fw); + err =3D amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); if (err) goto out; /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/ @@ -477,10 +493,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_devi= ce *adev) } =20 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); - err =3D request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.me_fw); + err =3D amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); if (err) goto out; if (adev->gfx.rs64_enable) { @@ -493,10 +506,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_devi= ce *adev) =20 if (!amdgpu_sriov_vf(adev)) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); - err =3D request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.rlc_fw); + err =3D amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); if (err) goto out; rlc_hdr =3D (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->d= ata; @@ -508,10 +518,7 @@ static int gfx_v11_0_init_microcode(struct amdgpu_devi= ce *adev) } =20 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); - err =3D request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.mec_fw); + err =3D amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); if (err) goto out; if (adev->gfx.rs64_enable) { @@ -530,54 +537,15 @@ static int gfx_v11_0_init_microcode(struct amdgpu_dev= ice *adev) =20 out: if (err) { - dev_err(adev->dev, - "gfx11: Failed to init firmware \"%s\"\n", - fw_name); - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw =3D NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw =3D NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw =3D NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw =3D NULL; + amdgpu_ucode_release(adev->gfx.pfp_fw); + amdgpu_ucode_release(adev->gfx.me_fw); + amdgpu_ucode_release(adev->gfx.rlc_fw); + amdgpu_ucode_release(adev->gfx.mec_fw); } =20 return err; } =20 -static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) -{ - const struct psp_firmware_header_v1_0 *toc_hdr; - int err =3D 0; - char fw_name[40]; - char ucode_prefix[30]; - - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_= prefix)); - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); - err =3D request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); - if (err) - goto out; - - err =3D amdgpu_ucode_validate(adev->psp.toc_fw); - if (err) - goto out; - - toc_hdr =3D (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->da= ta; - adev->psp.toc.fw_version =3D le32_to_cpu(toc_hdr->header.ucode_version); - adev->psp.toc.feature_version =3D le32_to_cpu(toc_hdr->sos.fw_version); - adev->psp.toc.size_bytes =3D le32_to_cpu(toc_hdr->header.ucode_size_bytes= ); - adev->psp.toc.start_addr =3D (uint8_t *)toc_hdr + - le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); - return 0; -out: - dev_err(adev->dev, "Failed to load TOC microcode\n"); - release_firmware(adev->psp.toc_fw); - adev->psp.toc_fw =3D NULL; - return err; -} - static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) { u32 count =3D 0; diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/a= mdgpu/imu_v11_0.c index 95548c512f4f..79ebf692cec6 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -49,10 +49,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device= *adev) amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_= prefix)); =20 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_imu.bin", ucode_prefix); - err =3D request_firmware(&adev->gfx.imu_fw, fw_name, adev->dev); - if (err) - goto out; - err =3D amdgpu_ucode_validate(adev->gfx.imu_fw); + err =3D amdgpu_ucode_request(adev, &adev->gfx.imu_fw, fw_name); if (err) goto out; imu_hdr =3D (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->da= ta; @@ -77,7 +74,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device = *adev) dev_err(adev->dev, "gfx11: Failed to load firmware \"%s\"\n", fw_name); - release_firmware(adev->gfx.imu_fw); + amdgpu_ucode_release(adev->gfx.imu_fw); } =20 return err; --=20 2.34.1