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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF00010207.mail.protection.outlook.com (10.167.241.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5944.8 via Frontend Transport; Wed, 4 Jan 2023 16:43:06 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 4 Jan 2023 10:42:57 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Lazar Lijo , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v5 17/45] drm/amd: Load GFX10 microcode during early_init Date: Wed, 4 Jan 2023 10:40:06 -0600 Message-ID: <20230104164042.30271-18-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230104164042.30271-1-mario.limonciello@amd.com> References: <20230104164042.30271-1-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00010207:EE_|PH0PR12MB5630:EE_ X-MS-Office365-Filtering-Correlation-Id: 9946da09-c3b6-48e7-2d0e-08daee72c1b1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jan 2023 16:43:06.9174 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9946da09-c3b6-48e7-2d0e-08daee72c1b1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00010207.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5630 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Simplifies the code so that GFX10 will get the firmware name from `amdgpu_ucode_ip_version_decode` and then use this filename to load microcode as part of the early_init process. Any failures will cause the driver to fail to probe before the firmware framebuffer has been removed. Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 84 ++++++-------------------- 1 file changed, 18 insertions(+), 66 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/a= mdgpu/gfx_v10_0.c index d36dd823a319..585b301856d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3968,9 +3968,9 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu= _device *adev) =20 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) { - const char *chip_name; char fw_name[40]; - char *wks =3D ""; + char ucode_prefix[30]; + const char *wks =3D ""; int err; const struct rlc_firmware_header_v2_0 *rlc_hdr; uint16_t version_major; @@ -3978,71 +3978,31 @@ static int gfx_v10_0_init_microcode(struct amdgpu_d= evice *adev) =20 DRM_DEBUG("\n"); =20 - switch (adev->ip_versions[GC_HWIP][0]) { - case IP_VERSION(10, 1, 10): - chip_name =3D "navi10"; - break; - case IP_VERSION(10, 1, 1): - chip_name =3D "navi14"; - if (!(adev->pdev->device =3D=3D 0x7340 && - adev->pdev->revision !=3D 0x00)) - wks =3D "_wks"; - break; - case IP_VERSION(10, 1, 2): - chip_name =3D "navi12"; - break; - case IP_VERSION(10, 3, 0): - chip_name =3D "sienna_cichlid"; - break; - case IP_VERSION(10, 3, 2): - chip_name =3D "navy_flounder"; - break; - case IP_VERSION(10, 3, 1): - chip_name =3D "vangogh"; - break; - case IP_VERSION(10, 3, 4): - chip_name =3D "dimgrey_cavefish"; - break; - case IP_VERSION(10, 3, 5): - chip_name =3D "beige_goby"; - break; - case IP_VERSION(10, 3, 3): - chip_name =3D "yellow_carp"; - break; - case IP_VERSION(10, 3, 6): - chip_name =3D "gc_10_3_6"; - break; - case IP_VERSION(10, 1, 3): - case IP_VERSION(10, 1, 4): - chip_name =3D "cyan_skillfish2"; - break; - case IP_VERSION(10, 3, 7): - chip_name =3D "gc_10_3_7"; - break; - default: - BUG(); - } + if (adev->ip_versions[GC_HWIP][0] =3D=3D IP_VERSION(10, 1, 1) && + (!(adev->pdev->device =3D=3D 0x7340 && adev->pdev->revision !=3D 0x00)= )) + wks =3D "_wks"; + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_= prefix)); =20 - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", ucode_prefix, w= ks); err =3D amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); =20 - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", ucode_prefix, wk= s); err =3D amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); =20 - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", ucode_prefix, wk= s); err =3D amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); =20 if (!amdgpu_sriov_vf(adev)) { - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); err =3D amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); /* don't check this. There are apparently firmwares in the wild with * incorrect size in the header @@ -4051,7 +4011,7 @@ static int gfx_v10_0_init_microcode(struct amdgpu_dev= ice *adev) goto out; if (err) dev_dbg(adev->dev, - "gfx10: amdgpu_ucode_validate() failed \"%s\"\n", + "gfx10: amdgpu_ucode_request() failed \"%s\"\n", fw_name); rlc_hdr =3D (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->d= ata; version_major =3D le16_to_cpu(rlc_hdr->header.header_version_major); @@ -4061,14 +4021,14 @@ static int gfx_v10_0_init_microcode(struct amdgpu_d= evice *adev) goto out; } =20 - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", ucode_prefix, w= ks); err =3D amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); =20 - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks= ); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", ucode_prefix, = wks); err =3D amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); if (!err) { amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); @@ -4077,6 +4037,8 @@ static int gfx_v10_0_init_microcode(struct amdgpu_dev= ice *adev) err =3D 0; adev->gfx.mec2_fw =3D NULL; } + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); =20 gfx_v10_0_check_fw_write_wait(adev); out: @@ -4239,19 +4201,11 @@ static void gfx_v10_0_mec_fini(struct amdgpu_device= *adev) amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); } =20 -static int gfx_v10_0_me_init(struct amdgpu_device *adev) +static void gfx_v10_0_me_init(struct amdgpu_device *adev) { - int r; - bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); =20 amdgpu_gfx_graphics_queue_acquire(adev); - - r =3D gfx_v10_0_init_microcode(adev); - if (r) - DRM_ERROR("Failed to load gfx firmware!\n"); - - return r; } =20 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) @@ -4619,9 +4573,7 @@ static int gfx_v10_0_sw_init(void *handle) =20 adev->gfx.gfx_current_status =3D AMDGPU_GFX_NORMAL_MODE; =20 - r =3D gfx_v10_0_me_init(adev); - if (r) - return r; + gfx_v10_0_me_init(adev); =20 if (adev->gfx.rlc.funcs) { if (adev->gfx.rlc.funcs->init) { @@ -7599,7 +7551,7 @@ static int gfx_v10_0_early_init(void *handle) /* init rlcg reg access ctrl */ gfx_v10_0_init_rlcg_reg_access_ctrl(adev); =20 - return 0; + return gfx_v10_0_init_microcode(adev); } =20 static int gfx_v10_0_late_init(void *handle) --=20 2.34.1