From nobody Sun Sep 14 20:09:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15A57C32793 for ; Wed, 18 Jan 2023 14:36:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230500AbjAROgd (ORCPT ); Wed, 18 Jan 2023 09:36:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231358AbjAROgK (ORCPT ); Wed, 18 Jan 2023 09:36:10 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1ECD55A824 for ; Wed, 18 Jan 2023 06:25:02 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id b5so12944905wrn.0 for ; Wed, 18 Jan 2023 06:25:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WuzP/jaB8SzyapPtRBeUXHdkGGoxVUS/1cp5Czf/Za8=; b=m9P576NVzReU6cAZ97xjCDVLaqkh+FUJSmIbgt1DzyyIQE/MfubIle3QDgHX3cBjRH WJ5VFZL9UtGtiTaolY2GqSkG4WQuEWOWchx5DYgzmSz18PijLpl41/gbc/z9kBotMsLF XS4m6hFXVRoTvFPt71Eb3nY2wO2/pH0D7Y37bp/3N99MHCq2MCMkYcTjoO205MawiLi5 qgk8s5PCO+U10Lrj0EOubi3oERBqHfEDx2f2NH3dcRAq1/lzfrnBeR31G2MFKoEs7DBO 1Zs6FMMWMfUkJ5vSnVYd6x0HGA27FOPSBM5ZMnHMOpXgdGcUIv+diWnFf8mdI3mq6v0P u7lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WuzP/jaB8SzyapPtRBeUXHdkGGoxVUS/1cp5Czf/Za8=; b=QVqjZ4AbPqX8ClMbY6aSbd/pgLdFqOMDIIoGG3LYD12BYJCMhgCwMU/oVdjQ/kL4fD aHSo+mN3eTibtWDneSrb8B3eITUnebo/N9LOD18hL82vNuqAVkTAQtkQFGpyGw8FLaV5 j7MXqJfqSasbQgsLASxpQ2K1f/sdkXfHQAQ9XiXPd2E9EWHttzkpjQYOlV91+N6Dz/Ow WUbl6Q6TMH6FD5rlm4rSY/aCshttjOqNCK3WKRByh9TPBIVVDpor1j+nJmOGREAdrREl noJj05xA0qISwJFxjcCKCwtXW0653gt5RE6hEFY1KqPONkml0FFNYNsg1c1JohlMPcx1 zL1A== X-Gm-Message-State: AFqh2kosScvJ+4luela+z9NtgkSbIKRKnnuBfqqSBpbxdetWrxKxxbd+ lecMk9FiY1Yy23AvMr2CImpohw== X-Google-Smtp-Source: AMrXdXufYd/H16RLmonSQX4Vu6dFWQJ1mQ8BzQbJ7fb41yBjHBg0VaFhiNZybRkQEAQ9YXJKqC7hOw== X-Received: by 2002:adf:f989:0:b0:2bd:db93:8f3b with SMTP id f9-20020adff989000000b002bddb938f3bmr6209778wrr.39.1674051901488; Wed, 18 Jan 2023 06:25:01 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id h3-20020adfe983000000b002bdf5832843sm10612919wrm.66.2023.01.18.06.25.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 06:25:01 -0800 (PST) From: Neil Armstrong Date: Wed, 18 Jan 2023 15:24:56 +0100 Subject: [PATCH v4 1/3] arm64: dts: qcom: sm8550: add display hardware devices MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230104-topic-sm8550-upstream-dts-display-v4-1-1729cfc0e5db@linaro.org> References: <20230104-topic-sm8550-upstream-dts-display-v4-0-1729cfc0e5db@linaro.org> In-Reply-To: <20230104-topic-sm8550-upstream-dts-display-v4-0-1729cfc0e5db@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devices tree nodes describing display hardware on SM8550: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on the SM8550. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 300 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 300 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 3d47281a276b..a2683709cd66 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -1727,6 +1728,305 @@ opp-202000000 { }; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,sm8550-mdss"; + reg =3D <0 0x0ae00000 0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc MDSS_GDSC>; + + interconnects =3D <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "mdp0-mem", "mdp1-mem"; + + iommus =3D <&apps_smmu 0x1c00 0x2>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sm8550-dpu"; + reg =3D <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names =3D "mdp", "vbif"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + power-domains =3D <&rpmhpd SM8550_MMCX>; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz =3D /bits/ 64 <325000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae94000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + power-domains =3D <&rpmhpd SM8550_MMCX>; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible =3D "qcom,sm8550-dsi-phy-4nm"; + reg =3D <0 0x0ae95000 0 0x200>, + <0 0x0ae95200 0 0x280>, + <0 0x0ae95500 0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae96000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <5>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + power-domains =3D <&rpmhpd SM8550_MMCX>; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DIS= P_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + phys =3D <&mdss_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible =3D "qcom,sm8550-dsi-phy-4nm"; + reg =3D <0 0x0ae97000 0 0x200>, + <0 0x0ae97200 0 0x280>, + <0 0x0ae97500 0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,sm8550-dispcc"; + reg =3D <0 0x0af00000 0 0x20000>; + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + power-domains =3D <&rpmhpd SM8550_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + status =3D "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8550-pdc", "qcom,pdc"; reg =3D <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; --=20 2.34.1 From nobody Sun Sep 14 20:09:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B03FC38147 for ; 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Wed, 18 Jan 2023 06:25:01 -0800 (PST) From: Neil Armstrong Date: Wed, 18 Jan 2023 15:24:57 +0100 Subject: [PATCH v4 2/3] arm64: dts: qcom: sm8550-mtp: enable display hardware MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230104-topic-sm8550-upstream-dts-display-v4-2-1729cfc0e5db@linaro.org> References: <20230104-topic-sm8550-upstream-dts-display-v4-0-1729cfc0e5db@linaro.org> In-Reply-To: <20230104-topic-sm8550-upstream-dts-display-v4-0-1729cfc0e5db@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable MDSS/DPU/DSI0 on SM8550-MTP device. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8550-mtp.dts index 81fcbdc6bdc4..0dfd1d3db86c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -359,6 +359,28 @@ vreg_l3g_1p2: ldo3 { }; }; =20 +&dispcc { + status =3D "okay"; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l3e_1p2>; + status =3D "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l1e_0p88>; + status =3D "okay"; +}; + +&mdss_mdp { + status =3D "okay"; +}; + &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins =3D "gpio12"; --=20 2.34.1 From nobody Sun Sep 14 20:09:14 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3307AC32793 for ; Wed, 18 Jan 2023 14:36:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231187AbjAROgk (ORCPT ); Wed, 18 Jan 2023 09:36:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjAROgM (ORCPT ); Wed, 18 Jan 2023 09:36:12 -0500 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A922C59576 for ; Wed, 18 Jan 2023 06:25:04 -0800 (PST) Received: by mail-wr1-x429.google.com with SMTP id bk16so34086141wrb.11 for ; Wed, 18 Jan 2023 06:25:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=CNO+xStLObefcxKOOqh9tWK7W5JtgOUQOQVnSTs3zSM=; b=kmSe9CfVAh5xT8BFcYWHgK7z1oOqlZ0SYoA7E/C6a9zN9oJT1Zyo90IgVhw1Juq5kE 37KRYnJCRUa9djuKhJh/Tl9x2V1yfseARAPHtkKHkVcs2WMMf+jcKtdeUbpUikGP+yr2 f8C2J1O+pjAtbiMJYNpyuU/hiyrGhK3Nb5dNYXhlYw/25c4eUEGZHwXAX7ncZSQ7G6yS SDyKAOq4gdoTHGfSZ00ZYL5Yh4rSuHnt/sS0I36KLxttt3+kQfsi8nFMyoKM9xVVLvtR PA4F2yO6M8w/BjUdtPW/biffVI/v6G14GeICliz/aziU6IbpjQ0OqlMFcKH+R3ChS4PF 0ysA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CNO+xStLObefcxKOOqh9tWK7W5JtgOUQOQVnSTs3zSM=; b=cH2ej01DxwbXvzFEAkHLoAvc8shy6B8eSgAdIx81PMRvOoGUmSsW+5PVS0liP/G/iu H5b33c7o3cWGFMzv26faiIgnoiZ+YSqpDMwIU9Ou/pFw6R+5VuiNDUQhWXHVMlrKacf7 Mm6Y+tyd9GdC5iAcYav5Jq0hrjb//z+tJVQiFvFcbXpKFeH4hiBpsccxXbyBEzYdHLLF 9vOjJo3VBWBjcPW692JJntOmpsSmPbc+sWDYKWpEohK++DnvF+jveire4fO7OYAY+CPw VfbyZcX2a2Y9D83KlVzaxGrVJ9ttVpAdNk8waM8SF92VW7wE/GOSezyCeJCrRQ2VV7NA mSzg== X-Gm-Message-State: AFqh2koR0cioWYbFsRXCtKfMEgkRdcjHWeXYjivaIoKiXs9C8xuZKgTs 8lllwgxJrXa7QOEh6eZo3arlOA== X-Google-Smtp-Source: AMrXdXsJ3dHBhvNGTqcmor3Cq+H6QNGzHNMvtLjytY4IRZjEyLY95aKDPlFoL+KJJ/UFw4l7/Zk6tw== X-Received: by 2002:adf:f342:0:b0:2bb:9106:d09 with SMTP id e2-20020adff342000000b002bb91060d09mr6110376wrp.15.1674051903216; Wed, 18 Jan 2023 06:25:03 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id h3-20020adfe983000000b002bdf5832843sm10612919wrm.66.2023.01.18.06.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 06:25:02 -0800 (PST) From: Neil Armstrong Date: Wed, 18 Jan 2023 15:24:58 +0100 Subject: [PATCH v4 3/3] arm64: dts: qcom: sm8550-mtp: add DSI panel MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230104-topic-sm8550-upstream-dts-display-v4-3-1729cfc0e5db@linaro.org> References: <20230104-topic-sm8550-upstream-dts-display-v4-0-1729cfc0e5db@linaro.org> In-Reply-To: <20230104-topic-sm8550-upstream-dts-display-v4-0-1729cfc0e5db@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add nodes for the Visionox VTDR6130 found on the SM8550-MTP device. TLMM states are also added for the Panel reset GPIO and Tearing Effect signal for when the panel is running in DSI Command mode. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 54 +++++++++++++++++++++++++++++= ++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8550-mtp.dts index 0dfd1d3db86c..405212940d09 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -370,6 +370,32 @@ &mdss { &mdss_dsi0 { vdda-supply =3D <&vreg_l3e_1p2>; status =3D "okay"; + + panel@0 { + compatible =3D "visionox,vtdr6130"; + reg =3D <0>; + + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sde_dsi_active>, <&sde_te_active>; + pinctrl-1 =3D <&sde_dsi_suspend>, <&sde_te_suspend>; + + vddio-supply =3D <&vreg_l12b_1p8>; + vci-supply =3D <&vreg_l13b_3p0>; + vdd-supply =3D <&vreg_l11b_1p2>; + + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; }; =20 &mdss_dsi0_phy { @@ -415,6 +441,34 @@ &sleep_clk { =20 &tlmm { gpio-reserved-ranges =3D <32 8>; + + sde_dsi_active: sde-dsi-active-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sde_te_active: sde-te-active-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; }; =20 &uart7 { --=20 2.34.1