From nobody Mon Sep 15 21:18:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78CE4C46467 for ; Tue, 10 Jan 2023 19:23:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239307AbjAJTXQ (ORCPT ); Tue, 10 Jan 2023 14:23:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235187AbjAJTWp (ORCPT ); Tue, 10 Jan 2023 14:22:45 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EF72551EC for ; Tue, 10 Jan 2023 11:22:43 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id j16-20020a05600c1c1000b003d9ef8c274bso6546087wms.0 for ; Tue, 10 Jan 2023 11:22:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EIQZzMj+NHdju0t2ECocoqq5GGkKwpX9WdATXuG5dps=; b=yEc+gsDdkzGwE/FSyvNyEh1vt0FGFYMl37lXZIUPXRbd54Bz/By5Bk7TQ5m8PjY6sV R/o2ewqkyU8ePtCmw1uB7uN9rjeMIgp8hoWWxERpC0+NWepPXfAvGZXqeWvyv4BLTaF8 c+uZy/yeUX20RjF7fGO+BmIpgfMTPiWY0647WOR5ACyhN1gVsm8s4fPRCzIAiomk3VWS +Oy46WN80//y9dvbWjnnEK/pOOwlIQq+SeNrii3m5VBu9dvXd/kmSlIFhRz5qmITgczA FHhXchJNP9oJLi+6bKJEwn7x42YDUUCbWBOob3kJSm1qRDZWt3H5mQzHWh4urebns+5b 5xVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EIQZzMj+NHdju0t2ECocoqq5GGkKwpX9WdATXuG5dps=; b=PFMf/xVxSTEgxl/ievU3sngdBQQr1qHsbQxg5Dzzr0snbgmpW0uKPAoejQJCvwjdWZ omR01mMxJsvWSnhqtX6tQpYCKc/laT52tEQz7dAQB0PJyS1g6cvNi6mGW+C5auzzb3tP 9q5tPVTsVF0aSseO2kX4OCpsiZAEpzF9JnfrXq0NKusynn6NzwvUdMVMuzwhOj1OfeLP R/mXn2Vm06+t0D2tw8FCo7H7ndZV4u+1UHZ2D99y64eeLJbTsGtDAHd9RBiJgy6C8BGU Vli0dChRr3e4tmMLBEB6i2gO+VMfYJLblas/QtkCGq41lfIVqpwGNp9LpQs18F0dIrWZ 6EaA== X-Gm-Message-State: AFqh2kpNg0Ae6DAtHmESr3mqdXx9g9G+3tXyYz9xLhf+7VxXsIrUATGt lUHJGIVjzY1dC2I/FoMqEBauaw== X-Google-Smtp-Source: AMrXdXsQ3jXXQ+9/7MqQL1QO2A97thYMfY62C5s3DqLGlNpE1/eOFpvuP28NAtdEmN5G5Jivb2s+yA== X-Received: by 2002:a05:600c:4d20:b0:3d3:5737:3afb with SMTP id u32-20020a05600c4d2000b003d357373afbmr51067099wmp.41.1673378561804; Tue, 10 Jan 2023 11:22:41 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c4f0e00b003d96c811d6dsm22284343wmq.30.2023.01.10.11.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 11:22:41 -0800 (PST) From: Neil Armstrong Date: Tue, 10 Jan 2023 20:22:36 +0100 Subject: [PATCH v2 1/3] arm64: dts: qcom: sm8550: add display hardware devices MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230104-topic-sm8550-upstream-dts-display-v2-1-9fbb15263e0d@linaro.org> References: <20230104-topic-sm8550-upstream-dts-display-v2-0-9fbb15263e0d@linaro.org> In-Reply-To: <20230104-topic-sm8550-upstream-dts-display-v2-0-9fbb15263e0d@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devices tree nodes describing display hardware on SM8550: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on the SM8550. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 299 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 299 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 2d9377e01c3f..243fffa19c35 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -1455,6 +1456,304 @@ opp-202000000 { }; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,sm8550-mdss"; + reg =3D <0 0x0ae00000 0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc MDSS_GDSC>; + + interconnects =3D <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "mdp0-mem", "mdp1-mem"; + + iommus =3D <&apps_smmu 0x1c00 0x2>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sm8550-dpu"; + reg =3D <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names =3D "mdp", "vbif"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + power-domains =3D <&rpmhpd SM8550_MMCX>; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz =3D /bits/ 64 <325000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae94000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + power-domains =3D <&rpmhpd SM8550_MMCX>; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DIS= P_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible =3D "qcom,sm8550-dsi-phy-4nm"; + reg =3D <0 0x0ae95000 0 0x200>, + <0 0x0ae95200 0 0x280>, + <0 0x0ae95500 0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae96000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <5>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + power-domains =3D <&rpmhpd SM8550_MMCX>; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DIS= P_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + phys =3D <&mdss_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible =3D "qcom,sm8550-dsi-phy-4nm"; + reg =3D <0 0x0ae97000 0 0x200>, + <0 0x0ae97200 0 0x280>, + <0 0x0ae97500 0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,sm8550-dispcc"; + reg =3D <0 0x0af00000 0 0x20000>; + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + power-domains =3D <&rpmhpd SM8550_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + status =3D "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible =3D "qcom,sm8550-pdc", "qcom,pdc"; reg =3D <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; --=20 2.34.1 From nobody Mon Sep 15 21:18:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD76CC54EBC for ; Tue, 10 Jan 2023 19:23:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239746AbjAJTXU (ORCPT ); Tue, 10 Jan 2023 14:23:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239842AbjAJTWp (ORCPT ); Tue, 10 Jan 2023 14:22:45 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01985551FB for ; Tue, 10 Jan 2023 11:22:44 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id ja17so9549998wmb.3 for ; Tue, 10 Jan 2023 11:22:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5zlEq+szaC9jzYJEsHWHt1ai4b91KOiLfW+IEavVvd0=; b=HvoTMm1s6sdwPzv8C23cwaqXrMEshROIJmcbTzHuCChp7AhXKL22TQjkA1SJ3L8fLE JMoPdfN9B+lz315IGm6RjGH31V5C0jeQfUdkJ/Bv7Pfw2asg1edzfDR4rGB2FbceMJtO OBRzt/EkjVTMMoLKzrAkzYev5dlcRcmQq0SL4EoHZxU1vKcu497xOvplcO3m+c4u3ZtM fjyHDtjFVvc7rp7AYb9F4H/sHvQgc2zN3sxOKXq5AZ9L5CgAlT2tw/Cx/doiD6nheivN bSgw5MSv7TwqqlK9BhcLwOIddmcgmH/EUcnZL7D6JoxYgts8TYd+N88nAYiJ68CLQ4Xl PwvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5zlEq+szaC9jzYJEsHWHt1ai4b91KOiLfW+IEavVvd0=; b=HZTMEVayGSV6L1YjS/R/HGiQJf8eN1e192tmpcI4gfLXbfBYQMmTk52O91pL+C9nd7 lK+sNUW+8x9cUbMKmHzq5C0fMFHHz2lSQyaYctDjuy3WZpL98mA744cjhgJmGVaGaWaP 65WayIUc5lkIvm7So7oxvWwYjeXoTVgTTfjBz3Jx7KFp5A3ZdbNGb6P7iM4Eno5JpOBb wNlDqKwhkQv2f1oeg1raQW86THwVoUkaAWCinHvwoKD/5h7iRDDvRYDpqJCOMa64bjE3 RfkPGMMH74WP++az83vKxdCl7d3Kfkpdx03v1ESvdi0+98ufSEvgpeRQ8+ovKCKkj7S+ SYDQ== X-Gm-Message-State: AFqh2kqRYAsiIrCehwjz+kUWy4JzpkKCgZUQ7idZaowgNJ3uV2RmM8Nk tO+vDBHlsqyQ0uCj5U3QtacP4A== X-Google-Smtp-Source: AMrXdXtwl+tzR7j30Byk5USB7+6s9fh52dD7EGx7AkK55FEmF+V9UI5OtGX1Xv2Gjx5FtRTuqXuV0Q== X-Received: by 2002:a7b:c3c6:0:b0:3d2:3376:6f37 with SMTP id t6-20020a7bc3c6000000b003d233766f37mr49599033wmj.10.1673378562582; Tue, 10 Jan 2023 11:22:42 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c4f0e00b003d96c811d6dsm22284343wmq.30.2023.01.10.11.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 11:22:42 -0800 (PST) From: Neil Armstrong Date: Tue, 10 Jan 2023 20:22:37 +0100 Subject: [PATCH v2 2/3] arm64: dts: qcom: sm8550-mtp: enable display hardware MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230104-topic-sm8550-upstream-dts-display-v2-2-9fbb15263e0d@linaro.org> References: <20230104-topic-sm8550-upstream-dts-display-v2-0-9fbb15263e0d@linaro.org> In-Reply-To: <20230104-topic-sm8550-upstream-dts-display-v2-0-9fbb15263e0d@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable MDSS/DPU/DSI0 on SM8550-MTP device. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8550-mtp.dts index 8586e16d6079..5b7e301cc2a2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -359,6 +359,28 @@ vreg_l3g_1p2: ldo3 { }; }; =20 +&dispcc { + status =3D "okay"; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l3e_1p2>; + status =3D "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l1e_0p88>; + status =3D "okay"; +}; + +&mdss_mdp { + status =3D "okay"; +}; + &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins =3D "gpio12"; --=20 2.34.1 From nobody Mon Sep 15 21:18:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81526C46467 for ; Tue, 10 Jan 2023 19:23:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239845AbjAJTX0 (ORCPT ); Tue, 10 Jan 2023 14:23:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239112AbjAJTWq (ORCPT ); Tue, 10 Jan 2023 14:22:46 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F205BE6C for ; Tue, 10 Jan 2023 11:22:44 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id k26-20020a05600c1c9a00b003d972646a7dso12702827wms.5 for ; Tue, 10 Jan 2023 11:22:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=uPKIsPLN5aJ8m2V2u6J9M4j3Y5N3lS/nTl2zakrSabY=; b=A8w67MK45VArk3cK6G+xKVKvdEJFQaory9yT0jghmdWL7Rajy0swdGmCUz9eFciAXJ H72w5SzUSyf5KozK5jMVKQ1lyxP6UEbnovNdaj5aUDuvq6HfApnlmKObNGt9F3+K3tBH DID6Ghcb1XW48suhd0SfRQZoMCR7upsw96EOiik2P6UWnh/FGyoJYIUdtE+3d60xELbU 2qiJmhvJYsgn7tvUhC2f/gqa4fb/qJOSrZAbZ8MmLl/S8GbLZPErzuHQUDZ/Xw6pAZqi XvnTmJCViinyrILiCWcEtNwSTBbK77uQSYJazZB70zj0aFytLatyMU4S4yIS2sZWg9jY jklA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uPKIsPLN5aJ8m2V2u6J9M4j3Y5N3lS/nTl2zakrSabY=; b=chd79Zt4+vQAHnR/tZF03KnyFOHHYgR1anh1/+5c64VUBmUcGIJR0I5m88K3Goj7Qm Ue6EizL7B6XmO4yOIQnlHt5nfg73R1XRQZaaIHdq6Ee79D5MxuuFosTycfMH8fAiRn2q YObl596xOp5mUaCAVOqF3NtKhvQyMssqYUfQaWUMizi0VrCnwcxHD/Qjl50FKKf7ijD/ qIeU1Qi9Up3o08Z3u1RONSdep8dWzs14q1Db64Tzrr4TDMjAvBmsbzd+8LTh+VigwULD /LcHr3VlPgm0RUvFMpvDOkev3vugW/3F0LOTf/ySZX+SKeotHo2d0FvrZoVtzY00I+Mw Q5VA== X-Gm-Message-State: AFqh2kr/aMXVfk5vBjamx7qaM/0C0hvTBR/plGNlQX2d5JJcbvS6fJpH kRXcBgMU2d2jQ1SiSpUmDeFBxA== X-Google-Smtp-Source: AMrXdXvfdK2K/FiWYbRqJXhuAHn4w03xHu3kQnkjC8fGsEfTxompCyurPdcN8GD5vV1O26okK81+5A== X-Received: by 2002:a05:600c:354b:b0:3d0:4993:d45b with SMTP id i11-20020a05600c354b00b003d04993d45bmr51661918wmq.4.1673378563568; Tue, 10 Jan 2023 11:22:43 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c4f0e00b003d96c811d6dsm22284343wmq.30.2023.01.10.11.22.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 11:22:43 -0800 (PST) From: Neil Armstrong Date: Tue, 10 Jan 2023 20:22:38 +0100 Subject: [PATCH v2 3/3] arm64: dts: qcom: sm8550-mtp: add DSI panel MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230104-topic-sm8550-upstream-dts-display-v2-3-9fbb15263e0d@linaro.org> References: <20230104-topic-sm8550-upstream-dts-display-v2-0-9fbb15263e0d@linaro.org> In-Reply-To: <20230104-topic-sm8550-upstream-dts-display-v2-0-9fbb15263e0d@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add nodes for the Visionox VTDR6130 found on the SM8550-MTP device. TLMM states are also added for the Panel reset GPIO and Tearing Effect signal for when the panel is running in DSI Command mode. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 56 +++++++++++++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8550-mtp.dts index 5b7e301cc2a2..cbb63a31f0ff 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -370,6 +370,34 @@ &mdss { &mdss_dsi0 { vdda-supply =3D <&vreg_l3e_1p2>; status =3D "okay"; + + panel@0 { + compatible =3D "visionox,vtdr6130"; + reg =3D <0>; + + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sde_dsi_active>, <&sde_te_active>; + pinctrl-1 =3D <&sde_dsi_suspend>, <&sde_te_suspend>; + + vddio-supply =3D <&vreg_l12b_1p8>; + vci-supply =3D <&vreg_l13b_3p0>; + vdd-supply =3D <&vreg_l11b_1p2>; + + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + + status =3D "okay"; + + port { + panel0_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; }; =20 &mdss_dsi0_phy { @@ -415,6 +443,34 @@ &sleep_clk { =20 &tlmm { gpio-reserved-ranges =3D <32 8>; + + sde_dsi_active: sde-dsi-active-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sde_te_active: sde-te-active-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; }; =20 &uart7 { --=20 2.34.1