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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000E650.mail.protection.outlook.com (10.167.18.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5944.8 via Frontend Transport; Tue, 3 Jan 2023 22:19:49 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 3 Jan 2023 16:19:48 -0600 From: Mario Limonciello To: Alex Deucher , CC: Javier Martinez Canillas , Carlos Soriano Sanchez , , , David Airlie , "Daniel Vetter" , , Lazar Lijo , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v4 19/27] drm/amd: Load GFX11 microcode during early_init Date: Tue, 3 Jan 2023 16:18:38 -0600 Message-ID: <20230103221852.22813-20-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230103221852.22813-1-mario.limonciello@amd.com> References: <20230103221852.22813-1-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E650:EE_|CH0PR12MB5385:EE_ X-MS-Office365-Filtering-Correlation-Id: c337a217-6027-4a3b-14e8-08daedd8a11b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jan 2023 22:19:49.7346 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c337a217-6027-4a3b-14e8-08daedd8a11b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E650.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5385 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If GFX11 microcode is required but not available during early init, the firmware framebuffer will have already been released and the screen will freeze. Move the request for GFX11 microcode into the early_init phase so that if it's not available, driver init will fail. Signed-off-by: Mario Limonciello --- v3->v4: * Move to early_init phase --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 78 ++++++++++---------------- 1 file changed, 30 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/a= mdgpu/gfx_v11_0.c index 0c77d165caf7..5c7bc286618a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -443,6 +443,30 @@ static void gfx_v11_0_free_microcode(struct amdgpu_dev= ice *adev) kfree(adev->gfx.rlc.register_list_format); } =20 +static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, char *= ucode_prefix) +{ + const struct psp_firmware_header_v1_0 *toc_hdr; + int err =3D 0; + char fw_name[40]; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); + err =3D amdgpu_ucode_load(adev, &adev->psp.toc_fw, fw_name); + if (err) + goto out; + + toc_hdr =3D (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->da= ta; + adev->psp.toc.fw_version =3D le32_to_cpu(toc_hdr->header.ucode_version); + adev->psp.toc.feature_version =3D le32_to_cpu(toc_hdr->sos.fw_version); + adev->psp.toc.size_bytes =3D le32_to_cpu(toc_hdr->header.ucode_size_bytes= ); + adev->psp.toc.start_addr =3D (uint8_t *)toc_hdr + + le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); + return 0; +out: + release_firmware(adev->psp.toc_fw); + adev->psp.toc_fw =3D NULL; + return err; +} + static int gfx_v11_0_init_microcode(struct amdgpu_device *adev) { char fw_name[40]; @@ -513,6 +537,9 @@ static int gfx_v11_0_init_microcode(struct amdgpu_devic= e *adev) amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); } =20 + if (adev->firmware.load_type =3D=3D AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) + err =3D gfx_v11_0_init_toc_microcode(adev, ucode_prefix); + /* only one MEC for gfx 11.0.0. */ adev->gfx.mec2_fw =3D NULL; =20 @@ -531,38 +558,6 @@ static int gfx_v11_0_init_microcode(struct amdgpu_devi= ce *adev) return err; } =20 -static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev) -{ - const struct psp_firmware_header_v1_0 *toc_hdr; - int err =3D 0; - char fw_name[40]; - char ucode_prefix[30]; - - amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_= prefix)); - - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix); - err =3D request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); - if (err) - goto out; - - err =3D amdgpu_ucode_validate(adev->psp.toc_fw); - if (err) - goto out; - - toc_hdr =3D (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->da= ta; - adev->psp.toc.fw_version =3D le32_to_cpu(toc_hdr->header.ucode_version); - adev->psp.toc.feature_version =3D le32_to_cpu(toc_hdr->sos.fw_version); - adev->psp.toc.size_bytes =3D le32_to_cpu(toc_hdr->header.ucode_size_bytes= ); - adev->psp.toc.start_addr =3D (uint8_t *)toc_hdr + - le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); - return 0; -out: - dev_err(adev->dev, "Failed to load TOC microcode\n"); - release_firmware(adev->psp.toc_fw); - adev->psp.toc_fw =3D NULL; - return err; -} - static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev) { u32 count =3D 0; @@ -699,19 +694,11 @@ static void gfx_v11_0_mec_fini(struct amdgpu_device *= adev) amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); } =20 -static int gfx_v11_0_me_init(struct amdgpu_device *adev) +static void gfx_v11_0_me_init(struct amdgpu_device *adev) { - int r; - bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); =20 amdgpu_gfx_graphics_queue_acquire(adev); - - r =3D gfx_v11_0_init_microcode(adev); - if (r) - DRM_ERROR("Failed to load gfx firmware!\n"); - - return r; } =20 static int gfx_v11_0_mec_init(struct amdgpu_device *adev) @@ -1324,9 +1311,7 @@ static int gfx_v11_0_sw_init(void *handle) } } =20 - r =3D gfx_v11_0_me_init(adev); - if (r) - return r; + gfx_v11_0_me_init(adev); =20 r =3D gfx_v11_0_rlc_init(adev); if (r) { @@ -1394,9 +1379,6 @@ static int gfx_v11_0_sw_init(void *handle) =20 /* allocate visible FB for rlc auto-loading fw */ if (adev->firmware.load_type =3D=3D AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { - r =3D gfx_v11_0_init_toc_microcode(adev); - if (r) - dev_err(adev->dev, "Failed to load toc firmware!\n"); r =3D gfx_v11_0_rlc_autoload_buffer_init(adev); if (r) return r; @@ -4665,7 +4647,7 @@ static int gfx_v11_0_early_init(void *handle) =20 gfx_v11_0_init_rlcg_reg_access_ctrl(adev); =20 - return 0; + return gfx_v11_0_init_microcode(adev); } =20 static int gfx_v11_0_ras_late_init(void *handle) --=20 2.34.1