From nobody Fri Dec 19 19:00:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C25BC4708D for ; Tue, 3 Jan 2023 18:26:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238876AbjACSZq (ORCPT ); Tue, 3 Jan 2023 13:25:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238900AbjACSZD (ORCPT ); Tue, 3 Jan 2023 13:25:03 -0500 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CF7513EB7 for ; Tue, 3 Jan 2023 10:22:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1672770178; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eV/IUCSp9/wTt/soiWDmeCkmMLn0e6ds3BvgOidxvE0=; b=eCXywAd3Qb46RjNskojc8QCUOeXVHL7oH8sfJfNdroBvBJFgBniHqPT3UUEAHJHHq2it7q CAwMGp7Z7JqHOpixKEjt5MbW1W8tQytQsYfdiQV3G4lMil3A0IoAqFV4QYxQ+S4n4w+RxV bogFNeZE2I9V8laiI01Bdy1aHOLDcZI= Received: from mail-ua1-f70.google.com (mail-ua1-f70.google.com [209.85.222.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-205-yGirQY6mNqCldeqFrD7TjQ-1; Tue, 03 Jan 2023 13:22:56 -0500 X-MC-Unique: yGirQY6mNqCldeqFrD7TjQ-1 Received: by mail-ua1-f70.google.com with SMTP id 88-20020a9f2161000000b00576fb176177so1758853uab.3 for ; Tue, 03 Jan 2023 10:22:56 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eV/IUCSp9/wTt/soiWDmeCkmMLn0e6ds3BvgOidxvE0=; b=XzFZY/obtSVoyMPQYUeAvCilM7VXyRJLh6Y8FiqqmrkPqwgtuRLjne594KcpZSBjQS feqp3vHHlzBmqQF2iMfSgXtCFj2RSQz5CK9wXhnYm51kyBr/OHxw6Y8XPDzK9k355bOu vkCBYzjV7SjR0gISWotUTHEhtD4ERHmPcC7PD83J7QuAkWh9qq1FtYCdnTilznxLfOaq XHug8oICeMRfCPernQaCcaza9xSFwqIA739kNMFEZQYwd38ZbIYdyMHuVUd85Kv3ycHP V3cNN0tHpxmc+ggNvKNZaaYlsq21BZ9nJ1B4sJ6d7bH9WsGIkL5y5NnVpyeKWAy49peq USwg== X-Gm-Message-State: AFqh2kp6Bjezns1YxXxbH+CoRW4BvQ38R8oDL6nDKowQZXsOAJU4vkr2 9dBLaE4HExINcHEoN5Ab6AU1D9gju90sFGCvNt3+RxpGeg/jx+ChqbFJ5gha2cPbCy7Jli6WXjk V6wFYzj/kDyM9hI7w9ptFmFrJ X-Received: by 2002:a1f:c887:0:b0:3d5:42e8:ba29 with SMTP id y129-20020a1fc887000000b003d542e8ba29mr14223535vkf.4.1672770175567; Tue, 03 Jan 2023 10:22:55 -0800 (PST) X-Google-Smtp-Source: AMrXdXuo1rGk7wJA63eJbepf2010MYMUXxvwa0cSlEi0egISZwy74EE+RNE+FtFZieFOamgEueKa1A== X-Received: by 2002:a1f:c887:0:b0:3d5:42e8:ba29 with SMTP id y129-20020a1fc887000000b003d542e8ba29mr14223517vkf.4.1672770175145; Tue, 03 Jan 2023 10:22:55 -0800 (PST) Received: from x1.. (c-73-214-169-22.hsd1.pa.comcast.net. [73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:22:53 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 07/10] arm64: dts: qcom: sc8280xp: add missing spi nodes Date: Tue, 3 Jan 2023 13:22:26 -0500 Message-Id: <20230103182229.37169-8-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the missing nodes for the spi buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney --- Changes in v4: - Move #address-cells and #size-cells properties below reg (Johan) - Add missing power-domains property (Johan) arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 384 +++++++++++++++++++++++++ 1 file changed, 384 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index a0974b7ad9b1..7f316c3918bd 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -829,6 +829,22 @@ i2c16: i2c@880000 { status =3D "disabled"; }; =20 + spi16: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00880000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c17: i2c@884000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00884000 0 0x4000>; @@ -845,6 +861,22 @@ i2c17: i2c@884000 { status =3D "disabled"; }; =20 + spi17: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00884000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + uart17: serial@884000 { compatible =3D "qcom,geni-uart"; reg =3D <0 0x00884000 0 0x4000>; @@ -875,6 +907,22 @@ i2c18: i2c@888000 { status =3D "disabled"; }; =20 + spi18: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00888000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c19: i2c@88c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0088c000 0 0x4000>; @@ -891,6 +939,22 @@ i2c19: i2c@88c000 { status =3D "disabled"; }; =20 + spi19: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0088c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c20: i2c@890000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00890000 0 0x4000>; @@ -907,6 +971,22 @@ i2c20: i2c@890000 { status =3D "disabled"; }; =20 + spi20: spi@890000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00890000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c21: i2c@894000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00894000 0 0x4000>; @@ -923,6 +1003,22 @@ i2c21: i2c@894000 { status =3D "disabled"; }; =20 + spi21: spi@894000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00894000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c22: i2c@898000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00898000 0 0x4000>; @@ -939,6 +1035,22 @@ i2c22: i2c@898000 { status =3D "disabled"; }; =20 + spi22: spi@898000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00898000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c23: i2c@89c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0089c000 0 0x4000>; @@ -954,6 +1066,22 @@ i2c23: i2c@89c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + spi23: spi@89c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0089c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 qup0: geniqup@9c0000 { @@ -986,6 +1114,22 @@ i2c0: i2c@980000 { status =3D "disabled"; }; =20 + spi0: spi@980000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00980000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c1: i2c@984000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00984000 0 0x4000>; @@ -1002,6 +1146,22 @@ i2c1: i2c@984000 { status =3D "disabled"; }; =20 + spi1: spi@984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00984000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c2: i2c@988000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00988000 0 0x4000>; @@ -1018,6 +1178,22 @@ i2c2: i2c@988000 { status =3D "disabled"; }; =20 + spi2: spi@988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00988000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c3: i2c@98c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0098c000 0 0x4000>; @@ -1034,6 +1210,22 @@ i2c3: i2c@98c000 { status =3D "disabled"; }; =20 + spi3: spi@98c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0098c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00990000 0 0x4000>; @@ -1050,6 +1242,22 @@ i2c4: i2c@990000 { status =3D "disabled"; }; =20 + spi4: spi@990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00990000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c5: i2c@994000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00994000 0 0x4000>; @@ -1066,6 +1274,22 @@ i2c5: i2c@994000 { status =3D "disabled"; }; =20 + spi5: spi@994000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00994000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c6: i2c@998000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00998000 0 0x4000>; @@ -1082,6 +1306,22 @@ i2c6: i2c@998000 { status =3D "disabled"; }; =20 + spi6: spi@998000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00998000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c7: i2c@99c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0099c000 0 0x4000>; @@ -1097,6 +1337,22 @@ i2c7: i2c@99c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + spi7: spi@99c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0099c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 qup1: geniqup@ac0000 { @@ -1129,6 +1385,22 @@ i2c8: i2c@a80000 { status =3D "disabled"; }; =20 + spi8: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a80000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c9: i2c@a84000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a84000 0 0x4000>; @@ -1145,6 +1417,22 @@ i2c9: i2c@a84000 { status =3D "disabled"; }; =20 + spi9: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a84000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c10: i2c@a88000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a88000 0 0x4000>; @@ -1161,6 +1449,22 @@ i2c10: i2c@a88000 { status =3D "disabled"; }; =20 + spi10: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a88000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c11: i2c@a8c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a8c000 0 0x4000>; @@ -1177,6 +1481,22 @@ i2c11: i2c@a8c000 { status =3D "disabled"; }; =20 + spi11: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a8c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c12: i2c@a90000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a90000 0 0x4000>; @@ -1193,6 +1513,22 @@ i2c12: i2c@a90000 { status =3D "disabled"; }; =20 + spi12: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a90000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c13: i2c@a94000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a94000 0 0x4000>; @@ -1209,6 +1545,22 @@ i2c13: i2c@a94000 { status =3D "disabled"; }; =20 + spi13: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a94000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c14: i2c@a98000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a98000 0 0x4000>; @@ -1225,6 +1577,22 @@ i2c14: i2c@a98000 { status =3D "disabled"; }; =20 + spi14: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a98000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c15: i2c@a9c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a9c000 0 0x4000>; @@ -1240,6 +1608,22 @@ i2c15: i2c@a9c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + spi15: spi@a9c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a9c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 pcie4: pcie@1c00000 { --=20 2.39.0