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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:22:41 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 01/10] dt-bindings: qcom,*-geni: move #{address,size}-cells on i2c/spi nodes Date: Tue, 3 Jan 2023 13:22:20 -0500 Message-Id: <20230103182229.37169-2-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the #address-cells and #size-cells properties on the existing i2c/spi example nodes below the reg property so that all of the address-related properties are grouped together. Signed-off-by: Brian Masney Link: https://lore.kernel.org/lkml/Y6Wnh+tXPhF6aC1b@hovoldconsulting.com/ Acked-by: Rob Herring --- New patch introduced in v4 .../devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml | 4 ++-- .../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 4 ++-- .../devicetree/bindings/spi/qcom,spi-geni-qcom.yaml | 8 ++++---- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml = b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index f5f7dc8f325c..594bf810a4aa 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -127,13 +127,13 @@ examples: i2c@88000 { compatible =3D "qcom,geni-i2c"; reg =3D <0x00880000 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c0_default>; interrupts =3D ; - #address-cells =3D <1>; - #size-cells =3D <0>; interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_Q= UP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QU= P_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b= /Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index ab4df0205285..d6128fb7d361 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -137,14 +137,14 @@ examples: i2c0: i2c@a94000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0xa94000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; interrupts =3D ; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&qup_1_i2c_5_active>; pinctrl-1 =3D <&qup_1_i2c_5_sleep>; - #address-cells =3D <1>; - #size-cells =3D <0>; }; =20 uart0: serial@a88000 { diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml = b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml index 2e20ca313ec1..efa7f52941f8 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -85,13 +85,13 @@ examples: spi@880000 { compatible =3D "qcom,geni-spi"; reg =3D <0x00880000 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi0_default>; interrupts =3D ; - #address-cells =3D <1>; - #size-cells =3D <0>; power-domains =3D <&rpmhpd SC7180_CX>; operating-points-v2 =3D <&qup_opp_table>; interconnects =3D <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_Q= UP_CORE_0 0>, @@ -105,6 +105,8 @@ examples: spi@884000 { compatible =3D "qcom,geni-spi"; reg =3D <0x00884000 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; dmas =3D <&gpi_dma0 0 1 QCOM_GPI_SPI>, @@ -113,6 +115,4 @@ examples: pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi1_default>; interrupts =3D ; - #address-cells =3D <1>; - #size-cells =3D <0>; }; --=20 2.39.0 From nobody Fri Dec 19 02:49:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05663C53210 for ; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:22:42 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 02/10] arm64: dts: qcom: sc8280xp: move #{address,size}-cells on i2c nodes Date: Tue, 3 Jan 2023 13:22:21 -0500 Message-Id: <20230103182229.37169-3-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the #address-cells and #size-cells properties on the existing i2c nodes below the reg property so that all of the address-related properties are grouped together. Signed-off-by: Brian Masney Link: https://lore.kernel.org/lkml/Y6Wnh+tXPhF6aC1b@hovoldconsulting.com/ --- New patch introduced in v4 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 109c9d2b684d..c0ffca9c9ddb 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -830,11 +830,11 @@ qup2_uart17: serial@884000 { qup2_i2c5: i2c@894000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00894000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; interrupts =3D ; - #address-cells =3D <1>; - #size-cells =3D <0>; power-domains =3D <&rpmhpd SC8280XP_CX>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, @@ -861,11 +861,11 @@ qup0: geniqup@9c0000 { qup0_i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00990000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; interrupts =3D ; - #address-cells =3D <1>; - #size-cells =3D <0>; power-domains =3D <&rpmhpd SC8280XP_CX>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, --=20 2.39.0 From nobody Fri Dec 19 02:49:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A02EFC4708D for ; Tue, 3 Jan 2023 18:25:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238818AbjACSYu (ORCPT ); Tue, 3 Jan 2023 13:24:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238324AbjACSYQ (ORCPT ); Tue, 3 Jan 2023 13:24:16 -0500 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCB4913E24 for ; Tue, 3 Jan 2023 10:22:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1672770168; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xBfnG2FEiyAwTAbQnSPSn0PzrNwcC6RoTMJ49+9V96M=; b=hwVLAvLhui7Vprd1SL8RFLL6Fb5qZ+8cYtPKSAPpxEHoY/Fcnmw9OMqAooKXeRiN74jBij sgH9mRlryiLDVpdzjMGrVWfVSddF2RyCC44q9rywKyPNdNqQJ4KnU6ebVwPb1kEqXgEZKI N+ZxpnmV1bdh542rDA/SmmlKDjkv5vw= Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-256-aLVqCfx5NByPiMQKhr645Q-1; Tue, 03 Jan 2023 13:22:46 -0500 X-MC-Unique: aLVqCfx5NByPiMQKhr645Q-1 Received: by mail-qt1-f200.google.com with SMTP id w13-20020ac87e8d000000b003ab89c2625eso7374332qtj.12 for ; Tue, 03 Jan 2023 10:22:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xBfnG2FEiyAwTAbQnSPSn0PzrNwcC6RoTMJ49+9V96M=; b=wWCg7D5JMdS2PF3KSv/edSw582eyWq1JvFtJziRLf9fj7vyHbNVNpOt17Xuu+TSedR /5yHdi1Yg4w+9QtuvB2jiZhiXKATDdSTBHfhJ/tstP29gyvhqr8G3G1O+gf4MnAyx7CJ jIbxwtCPAWOL5hgFptQfs42RnXrhyfa9GrKdnrnQEkRkYaD1X4lymJP+tmOmCfHr3iUa tLtAceBSevXuNMDOhlf4b+LGfq/qwh/4B5RFoVGcpB2S2+KicUxHchS6k2/eo+zuaYEC isSDIcH2zpRnadMsR2gNI3g86fnoZ1CWVJLM67JwWg0hVg9Gaw8b3GMyz3ybM2tG2rW2 uPAw== X-Gm-Message-State: AFqh2kpHKWyRwWtL3OA24V1dG/DpY9YgnVtfk6OzUSI1uU1JlFmYaech rZtiZ7W2KQp8tFJJO+qOm5rJcb35uO6bMwK80kqt1+Zr0zCkh71iLkiMxcTCKBumxKgqeKdrO2F dwgOWDY5AQf2KBEupHJRhK/Bq X-Received: by 2002:ac8:13cb:0:b0:3a8:2e73:24c9 with SMTP id i11-20020ac813cb000000b003a82e7324c9mr62936867qtj.46.1672770166392; Tue, 03 Jan 2023 10:22:46 -0800 (PST) X-Google-Smtp-Source: AMrXdXtbrwoSRn2qCdN72mM+X3Ta6eDMCdqzHyjkofDhl4dpgUir8YZQ6o8j2l9lMfayo2FL9CRvJQ== X-Received: by 2002:ac8:13cb:0:b0:3a8:2e73:24c9 with SMTP id i11-20020ac813cb000000b003a82e7324c9mr62936839qtj.46.1672770166122; Tue, 03 Jan 2023 10:22:46 -0800 (PST) Received: from x1.. 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:22:45 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 03/10] arm64: dts: qcom: sc8280xp: rename qup2_uart17 to uart17 Date: Tue, 3 Jan 2023 13:22:22 -0500 Message-Id: <20230103182229.37169-4-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup2_uart17 to uart17. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Signed-off-by: Brian Masney Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.= com/ Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold --- No changes in v4 arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 12 ++++++------ arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 12 ++++++------ arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 14 +++++++------- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts= /qcom/sa8295p-adp.dts index 84cb6f3eeb56..61f2e44e70c1 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -17,7 +17,7 @@ / { compatible =3D "qcom,sa8295p-adp", "qcom,sa8540p"; =20 aliases { - serial0 =3D &qup2_uart17; + serial0 =3D &uart17; }; =20 chosen { @@ -240,11 +240,6 @@ &qup2 { status =3D "okay"; }; =20 -&qup2_uart17 { - compatible =3D "qcom,geni-debug-uart"; - status =3D "okay"; -}; - &remoteproc_adsp { firmware-name =3D "qcom/sa8540p/adsp.mbn"; status =3D "okay"; @@ -338,6 +333,11 @@ pm8450g_gpios: gpio@c000 { }; }; =20 +&uart17 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + &ufs_mem_hc { reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; =20 diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8540p-ride.dts index d70859803fbd..d19af74f5057 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -17,7 +17,7 @@ / { compatible =3D "qcom,sa8540p-ride", "qcom,sa8540p"; =20 aliases { - serial0 =3D &qup2_uart17; + serial0 =3D &uart17; }; =20 chosen { @@ -192,11 +192,6 @@ &qup2 { status =3D "okay"; }; =20 -&qup2_uart17 { - compatible =3D "qcom,geni-debug-uart"; - status =3D "okay"; -}; - &remoteproc_nsp0 { firmware-name =3D "qcom/sa8540p/cdsp.mbn"; status =3D "okay"; @@ -207,6 +202,11 @@ &remoteproc_nsp1 { status =3D "okay"; }; =20 +&uart17 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + &ufs_mem_hc { reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; =20 diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index 551768f97729..db273face248 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -17,7 +17,7 @@ / { compatible =3D "qcom,sc8280xp-crd", "qcom,sc8280xp"; =20 aliases { - serial0 =3D &qup2_uart17; + serial0 =3D &uart17; }; =20 backlight { @@ -363,12 +363,6 @@ keyboard@68 { }; }; =20 -&qup2_uart17 { - compatible =3D "qcom,geni-debug-uart"; - - status =3D "okay"; -}; - &remoteproc_adsp { firmware-name =3D "qcom/sc8280xp/qcadsp8280.mbn"; =20 @@ -381,6 +375,12 @@ &remoteproc_nsp0 { status =3D "okay"; }; =20 +&uart17 { + compatible =3D "qcom,geni-debug-uart"; + + status =3D "okay"; +}; + &ufs_mem_hc { reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; =20 diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index c0ffca9c9ddb..b8f567642551 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -813,7 +813,7 @@ qup2: geniqup@8c0000 { =20 status =3D "disabled"; =20 - qup2_uart17: serial@884000 { + uart17: serial@884000 { compatible =3D "qcom,geni-uart"; reg =3D <0 0x00884000 0 0x4000>; clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; --=20 2.39.0 From nobody Fri Dec 19 02:49:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFBB2C54EBC for ; Tue, 3 Jan 2023 18:25:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238834AbjACSYw (ORCPT ); Tue, 3 Jan 2023 13:24:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238743AbjACSYQ (ORCPT ); Tue, 3 Jan 2023 13:24:16 -0500 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8526A13EA1 for ; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:22:48 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 04/10] arm64: dts: qcom: sc8280xp: rename qup2_i2c5 to i2c21 Date: Tue, 3 Jan 2023 13:22:23 -0500 Message-Id: <20230103182229.37169-5-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup2_i2c5 to i2c21. Under the old name, this was the 5th index under qup2, which starts at index 16. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Additionally, the properties within the pinctrl state node are sorted to match the expected order that's typically done in other DTs. Signed-off-by: Brian Masney Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.= com/ Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold Tested-by: Steev Klimaszewski --- No changes in v4 arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 89 +++++++------ .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 120 +++++++++--------- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 3 files changed, 105 insertions(+), 106 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index db273face248..03e3814f2722 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -228,6 +228,43 @@ vreg_l9d: ldo9 { }; }; =20 +&i2c21 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c21_default>; + + status =3D "okay"; + + touchpad@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tpad_default>; + + wakeup-source; + }; + + keyboard@68 { + compatible =3D "hid-over-i2c"; + reg =3D <0x68>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&kybd_default>; + + wakeup-source; + }; +}; + &pcie2a { perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; @@ -326,43 +363,6 @@ &qup2 { status =3D "okay"; }; =20 -&qup2_i2c5 { - clock-frequency =3D <400000>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qup2_i2c5_default>; - - status =3D "okay"; - - touchpad@15 { - compatible =3D "hid-over-i2c"; - reg =3D <0x15>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&tpad_default>; - - wakeup-source; - }; - - keyboard@68 { - compatible =3D "hid-over-i2c"; - reg =3D <0x68>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&kybd_default>; - - wakeup-source; - }; -}; - &remoteproc_adsp { firmware-name =3D "qcom/sc8280xp/qcadsp8280.mbn"; =20 @@ -494,6 +494,13 @@ hastings_reg_en: hastings-reg-en-state { &tlmm { gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; =20 + i2c21_default: i2c21-default-state { + pins =3D "gpio81", "gpio82"; + function =3D "qup21"; + drive-strength =3D <16>; + bias-disable; + }; + kybd_default: kybd-default-state { disable-pins { pins =3D "gpio102"; @@ -598,14 +605,6 @@ qup0_i2c4_default: qup0-i2c4-default-state { drive-strength =3D <16>; }; =20 - qup2_i2c5_default: qup2-i2c5-default-state { - pins =3D "gpio81", "gpio82"; - function =3D "qup21"; - - bias-disable; - drive-strength =3D <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins =3D "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 568c6be1ceaa..ad66a87141be 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -282,6 +282,59 @@ vreg_l9d: ldo9 { }; }; =20 +&i2c21 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c21_default>; + + status =3D "okay"; + + touchpad@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tpad_default>; + + wakeup-source; + + status =3D "disabled"; + }; + + touchpad@2c { + compatible =3D "hid-over-i2c"; + reg =3D <0x2c>; + + hid-descr-addr =3D <0x20>; + interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tpad_default>; + + wakeup-source; + }; + + keyboard@68 { + compatible =3D "hid-over-i2c"; + reg =3D <0x68>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&kybd_default>; + + wakeup-source; + }; +}; + &pcie2a { perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; @@ -531,59 +584,6 @@ &qup2 { status =3D "okay"; }; =20 -&qup2_i2c5 { - clock-frequency =3D <400000>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qup2_i2c5_default>; - - status =3D "okay"; - - touchpad@15 { - compatible =3D "hid-over-i2c"; - reg =3D <0x15>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&tpad_default>; - - wakeup-source; - - status =3D "disabled"; - }; - - touchpad@2c { - compatible =3D "hid-over-i2c"; - reg =3D <0x2c>; - - hid-descr-addr =3D <0x20>; - interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&tpad_default>; - - wakeup-source; - }; - - keyboard@68 { - compatible =3D "hid-over-i2c"; - reg =3D <0x68>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&kybd_default>; - - wakeup-source; - }; -}; - &remoteproc_adsp { firmware-name =3D "qcom/sc8280xp/LENOVO/21BX/qcadsp8280.mbn"; =20 @@ -698,6 +698,13 @@ hall_int_n_default: hall-int-n-state { bias-disable; }; =20 + i2c21_default: i2c21-default-state { + pins =3D "gpio81", "gpio82"; + function =3D "qup21"; + drive-strength =3D <16>; + bias-disable; + }; + kybd_default: kybd-default-state { disable-pins { pins =3D "gpio102"; @@ -801,13 +808,6 @@ qup0_i2c4_default: qup0-i2c4-default-state { drive-strength =3D <16>; }; =20 - qup2_i2c5_default: qup2-i2c5-default-state { - pins =3D "gpio81", "gpio82"; - function =3D "qup21"; - bias-disable; - drive-strength =3D <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins =3D "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index b8f567642551..d4a7a4c3fdee 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -827,7 +827,7 @@ uart17: serial@884000 { status =3D "disabled"; }; =20 - qup2_i2c5: i2c@894000 { + i2c21: i2c@894000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00894000 0 0x4000>; #address-cells =3D <1>; --=20 2.39.0 From nobody Fri Dec 19 02:49:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DEEBC3DA7D for ; Tue, 3 Jan 2023 18:25:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238788AbjACSYp (ORCPT ); Tue, 3 Jan 2023 13:24:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238561AbjACSYQ (ORCPT ); Tue, 3 Jan 2023 13:24:16 -0500 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56CB113EA2 for ; Tue, 3 Jan 2023 10:22:53 -0800 (PST) DKIM-Signature: v=1; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:22:49 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 05/10] arm64: dts: qcom: sc8280xp: rename qup0_i2c4 to i2c4 Date: Tue, 3 Jan 2023 13:22:24 -0500 Message-Id: <20230103182229.37169-6-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup0_i2c4 to i2c4. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Additionally, the properties within the pinctrl state node are sorted to match the expected order that's typically done in other DTs. Signed-off-by: Brian Masney Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.= com/ Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold Tested-by: Steev Klimaszewski --- No changes in v4 arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 57 +++++++++--------- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 58 +++++++++---------- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 3 files changed, 58 insertions(+), 59 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index 03e3814f2722..dfd8c42d8ca0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -228,6 +228,27 @@ vreg_l9d: ldo9 { }; }; =20 +&i2c4 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_default>; + + status =3D "okay"; + + touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts0_default>; + }; +}; + &i2c21 { clock-frequency =3D <400000>; =20 @@ -334,27 +355,6 @@ &qup0 { status =3D "okay"; }; =20 -&qup0_i2c4 { - clock-frequency =3D <400000>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qup0_i2c4_default>; - - status =3D "okay"; - - touchscreen@10 { - compatible =3D "hid-over-i2c"; - reg =3D <0x10>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ts0_default>; - }; -}; - &qup1 { status =3D "okay"; }; @@ -494,6 +494,13 @@ hastings_reg_en: hastings-reg-en-state { &tlmm { gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; =20 + i2c4_default: i2c4-default-state { + pins =3D "gpio171", "gpio172"; + function =3D "qup4"; + drive-strength =3D <16>; + bias-disable; + }; + i2c21_default: i2c21-default-state { pins =3D "gpio81", "gpio82"; function =3D "qup21"; @@ -597,14 +604,6 @@ wake-n-pins { }; }; =20 - qup0_i2c4_default: qup0-i2c4-default-state { - pins =3D "gpio171", "gpio172"; - function =3D "qup4"; - - bias-disable; - drive-strength =3D <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins =3D "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index ad66a87141be..2c360e52dae5 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -282,6 +282,28 @@ vreg_l9d: ldo9 { }; }; =20 +&i2c4 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_default>; + + status =3D "okay"; + + /* FIXME: verify */ + touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts0_default>; + }; +}; + &i2c21 { clock-frequency =3D <400000>; =20 @@ -554,28 +576,6 @@ &qup0 { status =3D "okay"; }; =20 -&qup0_i2c4 { - clock-frequency =3D <400000>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qup0_i2c4_default>; - - status =3D "okay"; - - /* FIXME: verify */ - touchscreen@10 { - compatible =3D "hid-over-i2c"; - reg =3D <0x10>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ts0_default>; - }; -}; - &qup1 { status =3D "okay"; }; @@ -698,6 +698,13 @@ hall_int_n_default: hall-int-n-state { bias-disable; }; =20 + i2c4_default: i2c4-default-state { + pins =3D "gpio171", "gpio172"; + function =3D "qup4"; + drive-strength =3D <16>; + bias-disable; + }; + i2c21_default: i2c21-default-state { pins =3D "gpio81", "gpio82"; function =3D "qup21"; @@ -801,13 +808,6 @@ wake-n-pins { }; }; =20 - qup0_i2c4_default: qup0-i2c4-default-state { - pins =3D "gpio171", "gpio172"; - function =3D "qup4"; - bias-disable; - drive-strength =3D <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins =3D "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index d4a7a4c3fdee..6f652ec9cfb1 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -858,7 +858,7 @@ qup0: geniqup@9c0000 { =20 status =3D "disabled"; =20 - qup0_i2c4: i2c@990000 { + i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00990000 0 0x4000>; #address-cells =3D <1>; --=20 2.39.0 From nobody Fri Dec 19 02:49:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1593CC54EBD for ; Tue, 3 Jan 2023 18:25:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238817AbjACSZI (ORCPT ); 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:22:51 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 06/10] arm64: dts: qcom: sc8280xp: add missing i2c nodes Date: Tue, 3 Jan 2023 13:22:25 -0500 Message-Id: <20230103182229.37169-7-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the missing nodes for the i2c buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney --- Changes in v4: - Move #address-cells and #size-cells properties below reg (Johan) arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 352 +++++++++++++++++++++++++ 1 file changed, 352 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 6f652ec9cfb1..a0974b7ad9b1 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -813,6 +813,38 @@ qup2: geniqup@8c0000 { =20 status =3D "disabled"; =20 + i2c16: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00880000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c17: i2c@884000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00884000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + uart17: serial@884000 { compatible =3D "qcom,geni-uart"; reg =3D <0 0x00884000 0 0x4000>; @@ -827,6 +859,54 @@ uart17: serial@884000 { status =3D "disabled"; }; =20 + i2c18: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00888000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c19: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0088c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c20: i2c@890000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00890000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c21: i2c@894000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00894000 0 0x4000>; @@ -842,6 +922,38 @@ i2c21: i2c@894000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + i2c22: i2c@898000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00898000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c23: i2c@89c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0089c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 qup0: geniqup@9c0000 { @@ -858,6 +970,70 @@ qup0: geniqup@9c0000 { =20 status =3D "disabled"; =20 + i2c0: i2c@980000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00980000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c1: i2c@984000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00984000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c2: i2c@988000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00988000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c3: i2c@98c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0098c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00990000 0 0x4000>; @@ -873,6 +1049,54 @@ i2c4: i2c@990000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + i2c5: i2c@994000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00994000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c6: i2c@998000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00998000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c7: i2c@99c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0099c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 qup1: geniqup@ac0000 { @@ -888,6 +1112,134 @@ qup1: geniqup@ac0000 { ranges; =20 status =3D "disabled"; + + i2c8: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a80000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c9: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a84000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c10: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a88000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a8c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c12: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a90000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c13: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a94000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c14: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a98000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a9c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:22:53 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 07/10] arm64: dts: qcom: sc8280xp: add missing spi nodes Date: Tue, 3 Jan 2023 13:22:26 -0500 Message-Id: <20230103182229.37169-8-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the missing nodes for the spi buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney --- Changes in v4: - Move #address-cells and #size-cells properties below reg (Johan) - Add missing power-domains property (Johan) arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 384 +++++++++++++++++++++++++ 1 file changed, 384 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index a0974b7ad9b1..7f316c3918bd 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -829,6 +829,22 @@ i2c16: i2c@880000 { status =3D "disabled"; }; =20 + spi16: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00880000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c17: i2c@884000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00884000 0 0x4000>; @@ -845,6 +861,22 @@ i2c17: i2c@884000 { status =3D "disabled"; }; =20 + spi17: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00884000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + uart17: serial@884000 { compatible =3D "qcom,geni-uart"; reg =3D <0 0x00884000 0 0x4000>; @@ -875,6 +907,22 @@ i2c18: i2c@888000 { status =3D "disabled"; }; =20 + spi18: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00888000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c19: i2c@88c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0088c000 0 0x4000>; @@ -891,6 +939,22 @@ i2c19: i2c@88c000 { status =3D "disabled"; }; =20 + spi19: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0088c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c20: i2c@890000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00890000 0 0x4000>; @@ -907,6 +971,22 @@ i2c20: i2c@890000 { status =3D "disabled"; }; =20 + spi20: spi@890000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00890000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c21: i2c@894000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00894000 0 0x4000>; @@ -923,6 +1003,22 @@ i2c21: i2c@894000 { status =3D "disabled"; }; =20 + spi21: spi@894000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00894000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c22: i2c@898000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00898000 0 0x4000>; @@ -939,6 +1035,22 @@ i2c22: i2c@898000 { status =3D "disabled"; }; =20 + spi22: spi@898000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00898000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c23: i2c@89c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0089c000 0 0x4000>; @@ -954,6 +1066,22 @@ i2c23: i2c@89c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + spi23: spi@89c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0089c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 qup0: geniqup@9c0000 { @@ -986,6 +1114,22 @@ i2c0: i2c@980000 { status =3D "disabled"; }; =20 + spi0: spi@980000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00980000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c1: i2c@984000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00984000 0 0x4000>; @@ -1002,6 +1146,22 @@ i2c1: i2c@984000 { status =3D "disabled"; }; =20 + spi1: spi@984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00984000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c2: i2c@988000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00988000 0 0x4000>; @@ -1018,6 +1178,22 @@ i2c2: i2c@988000 { status =3D "disabled"; }; =20 + spi2: spi@988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00988000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c3: i2c@98c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0098c000 0 0x4000>; @@ -1034,6 +1210,22 @@ i2c3: i2c@98c000 { status =3D "disabled"; }; =20 + spi3: spi@98c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0098c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00990000 0 0x4000>; @@ -1050,6 +1242,22 @@ i2c4: i2c@990000 { status =3D "disabled"; }; =20 + spi4: spi@990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00990000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c5: i2c@994000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00994000 0 0x4000>; @@ -1066,6 +1274,22 @@ i2c5: i2c@994000 { status =3D "disabled"; }; =20 + spi5: spi@994000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00994000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c6: i2c@998000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00998000 0 0x4000>; @@ -1082,6 +1306,22 @@ i2c6: i2c@998000 { status =3D "disabled"; }; =20 + spi6: spi@998000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00998000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c7: i2c@99c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0099c000 0 0x4000>; @@ -1097,6 +1337,22 @@ i2c7: i2c@99c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + spi7: spi@99c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0099c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 qup1: geniqup@ac0000 { @@ -1129,6 +1385,22 @@ i2c8: i2c@a80000 { status =3D "disabled"; }; =20 + spi8: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a80000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c9: i2c@a84000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a84000 0 0x4000>; @@ -1145,6 +1417,22 @@ i2c9: i2c@a84000 { status =3D "disabled"; }; =20 + spi9: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a84000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c10: i2c@a88000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a88000 0 0x4000>; @@ -1161,6 +1449,22 @@ i2c10: i2c@a88000 { status =3D "disabled"; }; =20 + spi10: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a88000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c11: i2c@a8c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a8c000 0 0x4000>; @@ -1177,6 +1481,22 @@ i2c11: i2c@a8c000 { status =3D "disabled"; }; =20 + spi11: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a8c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c12: i2c@a90000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a90000 0 0x4000>; @@ -1193,6 +1513,22 @@ i2c12: i2c@a90000 { status =3D "disabled"; }; =20 + spi12: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a90000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c13: i2c@a94000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a94000 0 0x4000>; @@ -1209,6 +1545,22 @@ i2c13: i2c@a94000 { status =3D "disabled"; }; =20 + spi13: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a94000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c14: i2c@a98000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a98000 0 0x4000>; @@ -1225,6 +1577,22 @@ i2c14: i2c@a98000 { status =3D "disabled"; }; =20 + spi14: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a98000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c15: i2c@a9c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a9c000 0 0x4000>; @@ -1240,6 +1608,22 @@ i2c15: i2c@a9c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + spi15: spi@a9c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a9c000 0 0x4000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 pcie4: pcie@1c00000 { --=20 2.39.0 From nobody Fri Dec 19 02:49:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C3FBC53210 for ; Tue, 3 Jan 2023 18:26:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238893AbjACSZu (ORCPT ); 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:22:55 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 08/10] arm64: dts: qcom: sa8540p-ride: add i2c nodes Date: Tue, 3 Jan 2023 13:22:27 -0500 Message-Id: <20230103182229.37169-9-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the necessary nodes in order to get i2c0, i2c1, i2c12, i2c15, and i2c18 functioning on the automotive board and exposed to userspace. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. This change was validated by using i2c-tools 4.3.3 on CentOS Stream 9: [root@localhost ~]# i2cdetect -l i2c-0 i2c Geni-I2C I2C adapter i2c-1 i2c Geni-I2C I2C adapter i2c-12 i2c Geni-I2C I2C adapter i2c-15 i2c Geni-I2C I2C adapter i2c-18 i2c Geni-I2C I2C adapter [root@localhost ~]# i2cdetect -a -y 15 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Signed-off-by: Brian Masney Reviewed-by: Konrad Dybcio Tested-by: Shazad Hussain --- No changes in v4 arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 83 +++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8540p-ride.dts index d19af74f5057..e4badf6f7a52 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -17,6 +17,11 @@ / { compatible =3D "qcom,sa8540p-ride", "qcom,sa8540p"; =20 aliases { + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c12 =3D &i2c12; + i2c15 =3D &i2c15; + i2c18 =3D &i2c18; serial0 =3D &uart17; }; =20 @@ -146,6 +151,41 @@ vreg_l8g: ldo8 { }; }; =20 +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_default>; + + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_default>; + + status =3D "okay"; +}; + +&i2c12 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c12_default>; + + status =3D "okay"; +}; + +&i2c15 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c15_default>; + + status =3D "okay"; +}; + +&i2c18 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c18_default>; + + status =3D "okay"; +}; + &pcie2a { ranges =3D <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, @@ -188,6 +228,14 @@ &pcie3a_phy { status =3D "okay"; }; =20 +&qup0 { + status =3D "okay"; +}; + +&qup1 { + status =3D "okay"; +}; + &qup2 { status =3D "okay"; }; @@ -268,6 +316,41 @@ &xo_board_clk { /* PINCTRL */ =20 &tlmm { + i2c0_default: i2c0-default-state { + pins =3D "gpio135", "gpio136"; + function =3D "qup15"; + drive-strength =3D <2>; + bias-pull-up; + }; + + i2c1_default: i2c1-default-state { + pins =3D "gpio158", "gpio159"; + function =3D "qup15"; + drive-strength =3D <2>; + bias-pull-up; + }; + + i2c12_default: i2c12-default-state { + pins =3D "gpio0", "gpio1"; + function =3D "qup15"; + drive-strength =3D <2>; + bias-pull-up; + }; + + i2c15_default: i2c15-default-state { + pins =3D "gpio36", "gpio37"; + function =3D "qup15"; + drive-strength =3D <2>; + bias-pull-up; + }; + + i2c18_default: i2c18-default-state { + pins =3D "gpio66", "gpio67"; + function =3D "qup18"; + drive-strength =3D <2>; + bias-pull-up; + }; + pcie2a_default: pcie2a-default-state { perst-pins { pins =3D "gpio143"; --=20 2.39.0 From nobody Fri Dec 19 02:49:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73241C54EBE for ; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:22:58 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 09/10] arm64: dts: qcom: sc8280xp: add aliases for i2c4 and i2c21 Date: Tue, 3 Jan 2023 13:22:28 -0500 Message-Id: <20230103182229.37169-10-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add aliases for i2c4 and i2c21 to the crd and x13s DTS files so that what's exposed to userspace doesn't change in the future if additional i2c buses are enabled on these platforms. Signed-off-by: Brian Masney --- New patch introduced in v4 arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 2 ++ arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index dfd8c42d8ca0..92d410af6cf3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -17,6 +17,8 @@ / { compatible =3D "qcom,sc8280xp-crd", "qcom,sc8280xp"; =20 aliases { + i2c4 =3D &i2c4; + i2c21 =3D &i2c21; serial0 =3D &uart17; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 2c360e52dae5..f9da3ee54545 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -21,6 +21,11 @@ / { model =3D "Lenovo ThinkPad X13s"; compatible =3D "lenovo,thinkpad-x13s", "qcom,sc8280xp"; =20 + aliases { + i2c4 =3D &i2c4; + i2c21 =3D &i2c21; + }; + backlight { compatible =3D "pwm-backlight"; pwms =3D <&pmc8280c_lpg 3 1000000>; --=20 2.39.0 From nobody Fri Dec 19 02:49:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64662C4708D for ; Tue, 3 Jan 2023 18:25:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238862AbjACSZl (ORCPT ); Tue, 3 Jan 2023 13:25:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238892AbjACSZC (ORCPT ); Tue, 3 Jan 2023 13:25:02 -0500 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D63B613EBF for ; Tue, 3 Jan 2023 10:23:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1672770183; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Tt+pdRFwqN8VH88+PGfu+O8CtSAML4FLnYQjY76G08c=; b=b3Y6f9iAYvpSxvDVxjtsWJs2A99IqNS13jY0X6vTOe8qnHCTyc5DmpFgRvt0wiELJhnSBI PIFqYZbbLZZlLKn5BYWwuiQaR9UR18dBhsQmHI5JHVpa1oHURqoTaJcSJacycoPwwGfx4B Vksoj+LHAAaI0EDPdxWKWSqeIXS/Mlo= Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-606-gDRIZObwMmuM-9zAGfcK_A-1; Tue, 03 Jan 2023 13:23:02 -0500 X-MC-Unique: gDRIZObwMmuM-9zAGfcK_A-1 Received: by mail-qt1-f199.google.com with SMTP id fp22-20020a05622a509600b003ab920c4c89so6547161qtb.1 for ; Tue, 03 Jan 2023 10:23:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tt+pdRFwqN8VH88+PGfu+O8CtSAML4FLnYQjY76G08c=; b=zT6UJ8dfDSXNA5zzefWosH8zJOljWvKDvfgG1yqGLBU3toWZw0ktuOp+V3gcSd8a6F ZVo+vzQ+24Gip7vQdTcwKjohaZxkIRtTVoEkxlmd4n+WSVUP9bTBunoXgVrbWch1PDki aEZ4RDX1vSeDF9ijUGIb1B4dd4YZktPb75k5nUJKvDUS0DkZCUMQdYcr4dy1dLL7Eqtp O+hBMBnFzJReOTHR0FEBoakwxaRQjSDgA41snYFSSK6vUBZYhd8dYOPw2o6yZ4xyyvzf 7EqAjjUNwKkmrARi3XWJ6k5BN5wP0vIKMzi318Ol6a/Nfh4AJIQaCRC208RIQIfra5bD uoWg== X-Gm-Message-State: AFqh2krOig/Tsdd9GzrSfnpyjEk8J/8FMS5P+ikvBXYNJo8BvwJbx1pA 4+1Vglozk0x1iy3jEH9vg19XNsj/rzenfFVBUfBkUkOSChccPb/6HFBMzS6QVv8rVRfiGByLe8Q gD/Yz4bLAfeOQONgeAh3NcxAN X-Received: by 2002:ac8:7598:0:b0:3a5:63ef:cf4e with SMTP id s24-20020ac87598000000b003a563efcf4emr68534226qtq.16.1672770182230; Tue, 03 Jan 2023 10:23:02 -0800 (PST) X-Google-Smtp-Source: AMrXdXujwLFY/CRb243+DbBgit9aoC27M7uLVbd8/5ea/dPxHl86nTLOIaT52IuagtOHBBdSQJ8RLg== X-Received: by 2002:ac8:7598:0:b0:3a5:63ef:cf4e with SMTP id s24-20020ac87598000000b003a563efcf4emr68534207qtq.16.1672770182018; Tue, 03 Jan 2023 10:23:02 -0800 (PST) Received: from x1.. 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t13-20020a05620a450d00b006fba0a389a4sm22819675qkp.88.2023.01.03.10.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 10:23:01 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, robh+dt@kernel.org, konrad.dybcio@linaro.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.co Subject: [PATCH v4 10/10] arm64: dts: qcom: sc8280xp: add rng device tree node Date: Tue, 3 Jan 2023 13:22:29 -0500 Message-Id: <20230103182229.37169-11-bmasney@redhat.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103182229.37169-1-bmasney@redhat.com> References: <20230103182229.37169-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the necessary device tree node for qcom,prng-ee so we can use the hardware random number generator. This functionality was tested on a SA8540p automotive development board using kcapi-rng from libkcapi. Signed-off-by: Brian Masney Reviewed-by: Konrad Dybcio --- No changes in v4 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 7f316c3918bd..b713c0126164 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1626,6 +1626,13 @@ spi15: spi@a9c000 { }; }; =20 + rng: rng@10d3000 { + compatible =3D "qcom,prng-ee"; + reg =3D <0 0x010d3000 0 0x1000>; + clocks =3D <&rpmhcc RPMH_HWKM_CLK>; + clock-names =3D "core"; + }; + pcie4: pcie@1c00000 { device_type =3D "pci"; compatible =3D "qcom,pcie-sc8280xp"; --=20 2.39.0