From nobody Tue Sep 16 14:21:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83D43C3DA7D for ; Tue, 3 Jan 2023 14:13:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237865AbjACONW (ORCPT ); Tue, 3 Jan 2023 09:13:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237815AbjACONH (ORCPT ); Tue, 3 Jan 2023 09:13:07 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25A3F1117B for ; Tue, 3 Jan 2023 06:13:06 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id o31-20020a17090a0a2200b00223fedffb30so31209104pjo.3 for ; Tue, 03 Jan 2023 06:13:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UyYgBnGIgCz0adPXlD9wrM9sYGYzSlN2q//39kO7eCQ=; b=VFrCfQGvUaFBTByIk9Fw+SoRN2adKAy5nq1pk3GknMGICwVIeq6PqVcguH2UT7fw14 scTfEiPCmS5EzqItFCCz3rcibVJcuNQ2y5jWui8Whhs1MAG7NkznD1dP+mLOxBglEv/Q gmleGq2bTYjk+2DCP2SnIOYTMUk/rkE5BTphu1CXzN7nSQxD6hc2f9QyvgaqcHYR1t/q zAMczPc1mVjoTPuXRUXL90hUwUJJ0GvIiejgH+mIbnfVvlDT7OivXJm00f8S9D+AhWF0 3+PLUFoH+qxDSD5zwV7z3ThGwTPIeCrpIN/mI6txHvOc0J7WxwvvKSwQ/G2/6uzfapKl 5jkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UyYgBnGIgCz0adPXlD9wrM9sYGYzSlN2q//39kO7eCQ=; b=bGVfLIqLsEdCAC7+pigTk7/lABjYORGDmaXTY84Lvc1mnWyV1OwONtHX+XTSkn+Dxl hgvLV9FYmiemIS2a7mMye6rNhuU556lsBYws4dMXMtTyrF7tWiUidEgjLfq8LzilY0JV anl6SHqp1ixMBXW3wn03gWkcPHCwBjpQa7mukMwti9p+doAof4nMpr79sjuv1F8M+O80 HEJbc1qOn8kXjzVIFfjmpes14RJn9ZD6cmRs4MOdWHCnB5fOAqMsCTpNZ0wcroz8gK97 UCXUTovWJPEx3eW43s4VQl7Rn/OyDJ2no5jmAhd4U2qateII5yh6+Mlk5wR+xCYVbCNX ywlA== X-Gm-Message-State: AFqh2krgd+pb6i5mS8HFIJudjlHU9HRPYgekSBheKV7NimQFOWBaATMO dYl+IAfuRiO2SgSdwJIi0tf4Ng== X-Google-Smtp-Source: AMrXdXttb+oVh5eibKiteLalBjeH5MUTIPsfMvziRRV5ZsaGNN266xnWVWLFBygP/lCOLay51PTgqg== X-Received: by 2002:a17:903:200b:b0:192:467e:7379 with SMTP id s11-20020a170903200b00b00192467e7379mr39572832pla.49.1672755185537; Tue, 03 Jan 2023 06:13:05 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.241]) by smtp.gmail.com with ESMTPSA id x16-20020a1709027c1000b00192b0a07891sm8598286pll.101.2023.01.03.06.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 06:13:05 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Hector Martin , Sven Peter , Alyssa Rosenzweig , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, Anup Patel , Atish Patra Subject: [PATCH v16 6/9] RISC-V: Use IPIs for remote TLB flush when possible Date: Tue, 3 Jan 2023 19:42:18 +0530 Message-Id: <20230103141221.772261-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103141221.772261-1-apatel@ventanamicro.com> References: <20230103141221.772261-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we have specialized interrupt controller (such as AIA IMSIC) which allows supervisor mode to directly inject IPIs without any assistance from M-mode or HS-mode then using such specialized interrupt controller, we can do remote TLB flushes directly from supervisor mode instead of using the SBI RFENCE calls. This patch extends remote TLB flush functions to use supervisor mode IPIs whenever direct supervisor mode IPIs.are supported by interrupt controller. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/mm/tlbflush.c | 93 +++++++++++++++++++++++++++++++++------- 1 file changed, 78 insertions(+), 15 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index ce7dfc81bb3f..91078377344d 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -7,14 +7,62 @@ #include #include =20 +static inline void local_flush_tlb_range(unsigned long start, + unsigned long size, unsigned long stride) +{ + if (size <=3D stride) + local_flush_tlb_page(start); + else + local_flush_tlb_all(); +} + +static inline void local_flush_tlb_range_asid(unsigned long start, + unsigned long size, unsigned long stride, unsigned long asid) +{ + if (size <=3D stride) + local_flush_tlb_page_asid(start, asid); + else + local_flush_tlb_all_asid(asid); +} + +static void __ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (riscv_use_ipi_for_rfence()) + on_each_cpu(__ipi_flush_tlb_all, NULL, 1); + else + sbi_remote_sfence_vma(NULL, 0, -1); +} + +struct flush_tlb_range_data { + unsigned long asid; + unsigned long start; + unsigned long size; + unsigned long stride; +}; + +static void __ipi_flush_tlb_range_asid(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid); +} + +static void __ipi_flush_tlb_range(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range(d->start, d->size, d->stride); } =20 -static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long star= t, - unsigned long size, unsigned long stride) +static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, + unsigned long size, unsigned long stride) { + struct flush_tlb_range_data ftd; struct cpumask *pmask =3D &mm->context.tlb_stale_mask; struct cpumask *cmask =3D mm_cpumask(mm); unsigned int cpuid; @@ -39,19 +87,34 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm,= unsigned long start, cpumask_andnot(pmask, pmask, cmask); =20 if (broadcast) { - sbi_remote_sfence_vma_asid(cmask, start, size, asid); - } else if (size <=3D stride) { - local_flush_tlb_page_asid(start, asid); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D asid; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range_asid, + &ftd, 1); + } else + sbi_remote_sfence_vma_asid(cmask, + start, size, asid); } else { - local_flush_tlb_all_asid(asid); + local_flush_tlb_range_asid(start, size, stride, asid); } } else { if (broadcast) { - sbi_remote_sfence_vma(cmask, start, size); - } else if (size <=3D stride) { - local_flush_tlb_page(start); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D 0; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range, + &ftd, 1); + } else + sbi_remote_sfence_vma(cmask, start, size); } else { - local_flush_tlb_all(); + local_flush_tlb_range(start, size, stride); } } =20 @@ -60,23 +123,23 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm= , unsigned long start, =20 void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE); + __flush_tlb_range(mm, 0, -1, PAGE_SIZE); } =20 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); } =20 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE); } #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); } #endif --=20 2.34.1