From nobody Tue Sep 16 14:11:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1AC4C3DA7D for ; Tue, 3 Jan 2023 14:13:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237811AbjACONG (ORCPT ); Tue, 3 Jan 2023 09:13:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237818AbjACOMq (ORCPT ); Tue, 3 Jan 2023 09:12:46 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D43721117F for ; Tue, 3 Jan 2023 06:12:44 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso36041857pjt.0 for ; Tue, 03 Jan 2023 06:12:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GBh16wlKK1pVBXMjv15TuW7j92X6+xaNPp74Ke5cwzg=; b=ag2VYZdi8sHLadDfTOWomK5QgMIp5UxmtALzG6C+VynD9m/7Y1X1UTRRMNa1SLWudR fsKqlD5togrJ6kiHvfsCqE121VmJzDJS4OvJpZT49IeV1uoNPMuy3lPB7mmhACLJ377C sSnhYyWZN3HBMbt3l4rlQWsYKweAVSL+AgdyQr6/jobS5f64v+Y/jJTHZopbYCZmGExD +ITdd8Wp5MEOBw17CkhiQDkBEdt9hL6zz/QfFan4eCTh4ufZMW+SEW+RirbywdY/cLgc mDZt0aeayvg/vFK0p78cMcIs7WgabCpHW+aYgYlFKLMgT2FvmzXhuQgPmfHbNlXLKxTp Voig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GBh16wlKK1pVBXMjv15TuW7j92X6+xaNPp74Ke5cwzg=; b=zB+x7xGBor9Rm/2cxoF7/wdzGUe4xE1llNp9WMQ6EBTzpTklSs+5jEOol6cdiQT/xP DEMPixvdY7y0T84gyvW2AkBRK63r/FbTUDGmXlCmJqsy5TT2jYYfH7VDJd6lUpmyzvFk 7bP4VEsogm8qoEN+2cozRdVmezaTPRUzDBXZqLVgiUpls31u48er+bXnDcXWUFAVe6pm PomXWmqmNmmYO6HdHHyoUNXgi0jN5Xxtmpbk7N2VBsTWMfL79kuMUfwbaDMdPxFT2ZBp hoHAqAwJ3qxFEPpjR1+0e2p2NLO8Rz3ZA3I+wXfcOpC87FiA6IFoWIRhELEdFgt8y6T2 as7w== X-Gm-Message-State: AFqh2kr0gUatTPjUbGIRiZO5Yx+VTfuASDKlOgpzkHGSEWNgozRmbCao 0Z103/UuXW9o3+6dMfx2XbdCVQ== X-Google-Smtp-Source: AMrXdXuLqYi4hbftZX6Ald4rvwIshOeG5B3xI5B05B6I0NSM8AMUySmbHh3I2kBz7X9fDRWmiUfGUg== X-Received: by 2002:a17:902:b20b:b0:186:7a6b:24d9 with SMTP id t11-20020a170902b20b00b001867a6b24d9mr50119651plr.23.1672755164157; Tue, 03 Jan 2023 06:12:44 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.241]) by smtp.gmail.com with ESMTPSA id x16-20020a1709027c1000b00192b0a07891sm8598286pll.101.2023.01.03.06.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 06:12:43 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Hector Martin , Sven Peter , Alyssa Rosenzweig , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, Anup Patel , Atish Patra Subject: [PATCH v16 2/9] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Date: Tue, 3 Jan 2023 19:42:14 +0530 Message-Id: <20230103141221.772261-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103141221.772261-1-apatel@ventanamicro.com> References: <20230103141221.772261-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and KVM RISC-V) don't have associated DT node but these drivers need standard per-CPU (local) interrupts defined by the RISC-V privileged specification. We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V drivers not having DT node to discover INTC hwnode which in-turn helps these drivers to map per-CPU (local) interrupts provided by the INTC driver. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/include/asm/irq.h | 4 ++++ arch/riscv/kernel/irq.c | 18 ++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 7 +++++++ 3 files changed, 29 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index e4c435509983..43b9ebfbd943 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,10 @@ =20 #include =20 +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); + +struct fwnode_handle *riscv_get_intc_hwnode(void); + extern void __init init_IRQ(void); =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 7207fa08d78f..96d3171f0ca1 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -7,9 +7,27 @@ =20 #include #include +#include +#include #include #include =20 +static struct fwnode_handle *(*__get_intc_node)(void); + +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)) +{ + __get_intc_node =3D fn; +} + +struct fwnode_handle *riscv_get_intc_hwnode(void) +{ + if (__get_intc_node) + return __get_intc_node(); + + return NULL; +} +EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 499e5f81b3fe..9066467e99e4 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops= =3D { .xlate =3D irq_domain_xlate_onecell, }; =20 +static struct fwnode_handle *riscv_intc_hwnode(void) +{ + return intc_domain->fwnode; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -126,6 +131,8 @@ static int __init riscv_intc_init(struct device_node *n= ode, return rc; } =20 + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, "irqchip/riscv/intc:starting", riscv_intc_cpu_starting, --=20 2.34.1