From nobody Tue Sep 16 14:11:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91FB6C3DA7D for ; Tue, 3 Jan 2023 14:12:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237688AbjACOL1 (ORCPT ); Tue, 3 Jan 2023 09:11:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237589AbjACOLX (ORCPT ); Tue, 3 Jan 2023 09:11:23 -0500 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED2846365 for ; Tue, 3 Jan 2023 06:11:18 -0800 (PST) Received: by mail-pj1-x1029.google.com with SMTP id o21so2858277pjw.0 for ; Tue, 03 Jan 2023 06:11:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Dlh2CMNdSoUIQxTaEwlbl5D9rexWqbuQ4H+cWHRWlxo=; b=gzxbqIdlnLfc3CYwtD5PIBA+jLZSmjFqO8TrRQZJuC42pQak+JX3HPhYh9kRLnYkaQ IaNUcVXwgUgpIb7WxUwbVgIZTjHbJrnm6mkhnhjO3DW6Zg/KlWGnVI4/aNBMGdR2Lusq JBoCwrorLqqrMfcK9UZRKP8m6KfWIgDYLVLMIutcA9c7n3zw1DeAgC+FR88evKH7XaiP J5OC6TsRJ13W6bv21/QL4g+jkB3ZNW1N5XNfxobqRPNJgkHoS+m/sLHIWLbijyCJtlxB kNl7QDifcdudr9IwAvQj38CfDJ6gjsGhJKHdo6UfuELXzch5CTYyyl97H1pfxicIvnSV WBLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dlh2CMNdSoUIQxTaEwlbl5D9rexWqbuQ4H+cWHRWlxo=; b=K+A7jjTI7opX9gN2fHqkDv4SQzfum9eCRVqQbDDwlxPuf6+1bS1L77gkwQHFfjP8YA HLahMIruRAP2K5PedfcYXMfDwKSkeLuZfsCc8YBtjna2qFLmRr3IddiKKK/yDer0KQds Nup2lK5FhBUIuPHVBsZxRyhhP+X2AYC9rj8THz8GfMoy+QOWPZSTvuA40GM+Qc1kbyBm CRUR6pIuLBYo53uIYdrxmAbv/JR8kCfUZRPvVpZdBnxkPmLUUbomD7XAoLJMu+B6Vqqo uoph01wdlBSPP1aeRN8cKTSxoWyFQ/d6M7xMbPGnwU9kB8mk4mno0BQHIgwzGeNmjHL/ jJ/w== X-Gm-Message-State: AFqh2kpVCzVx9kXJcMcqCugRfrEhytX8nwDNMSymIe/j91F2cjOXRC8L iAekLct1FcV8EUoZqHelEYXWcw== X-Google-Smtp-Source: AMrXdXvvhbldGv1zoWD3s9+n/qqO1/Vrk7Z3TW+8cYf8u4sdHtpTbSDvzlPBk4S/2Jm8tkENFlkpOQ== X-Received: by 2002:a17:902:d3cc:b0:192:9141:ace5 with SMTP id w12-20020a170902d3cc00b001929141ace5mr25598340plb.13.1672755078370; Tue, 03 Jan 2023 06:11:18 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.241]) by smtp.gmail.com with ESMTPSA id l3-20020a170902e2c300b00192bf7eaf28sm6146117plc.286.2023.01.03.06.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 06:11:17 -0800 (PST) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Conor Dooley , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Palmer Dabbelt Subject: [PATCH v6 1/3] RISC-V: time: initialize hrtimer based broadcast clock event device Date: Tue, 3 Jan 2023 19:41:00 +0530 Message-Id: <20230103141102.772228-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103141102.772228-1-apatel@ventanamicro.com> References: <20230103141102.772228-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Similarly to commit 022eb8ae8b5e ("ARM: 8938/1: kernel: initialize broadcast hrtimer based clock event device"), RISC-V needs to initiate hrtimer based broadcast clock event device before C3STOP can be used. Otherwise, the introduction of C3STOP for the RISC-V arch timer in commit 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during CPU suspend") leaves us without any broadcast timer registered. This prevents the kernel from entering oneshot mode, which breaks timer behaviour, for example clock_nanosleep(). A test app that sleeps each cpu for 6, 5, 4, 3 ms respectively, HZ=3D250 & C3STOP enabled, the sleep times are rounded up to the next jiffy: =3D=3D CPU: 1 =3D=3D =3D=3D CPU: 2 =3D=3D =3D=3D CPU: 3 =3D=3D = =3D=3D CPU: 4 =3D=3D Mean: 7.974992 Mean: 7.976534 Mean: 7.962591 Mean: 3.952179 Std Dev: 0.154374 Std Dev: 0.156082 Std Dev: 0.171018 Std Dev: 0.076193 Hi: 9.472000 Hi: 10.495000 Hi: 8.864000 Hi: 4.736000 Lo: 6.087000 Lo: 6.380000 Lo: 4.872000 Lo: 3.403000 Samples: 521 Samples: 521 Samples: 521 Samples: 521 Link: https://lore.kernel.org/linux-riscv/YzYTNQRxLr7Q9JR0@spud/ Fixes: 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during = CPU suspend") Suggested-by: Samuel Holland Signed-off-by: Conor Dooley Signed-off-by: Anup Patel Reviewed-by: Samuel Holland Acked-by: Palmer Dabbelt --- arch/riscv/kernel/time.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index 8217b0f67c6c..1cf21db4fcc7 100644 --- a/arch/riscv/kernel/time.c +++ b/arch/riscv/kernel/time.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -29,6 +30,8 @@ void __init time_init(void) =20 of_clk_init(NULL); timer_probe(); + + tick_setup_hrtimer_broadcast(); } =20 void clocksource_arch_init(struct clocksource *cs) --=20 2.34.1 From nobody Tue Sep 16 14:11:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 920C9C54EBC for ; Tue, 3 Jan 2023 14:12:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237803AbjACOLa (ORCPT ); Tue, 3 Jan 2023 09:11:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237756AbjACOL0 (ORCPT ); Tue, 3 Jan 2023 09:11:26 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FFC511175 for ; Tue, 3 Jan 2023 06:11:24 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id p24so10193024plw.11 for ; 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Tue, 03 Jan 2023 06:11:23 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.241]) by smtp.gmail.com with ESMTPSA id l3-20020a170902e2c300b00192bf7eaf28sm6146117plc.286.2023.01.03.06.11.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 06:11:23 -0800 (PST) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Conor Dooley , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Rob Herring , Palmer Dabbelt Subject: [PATCH v6 2/3] dt-bindings: timer: Add bindings for the RISC-V timer device Date: Tue, 3 Jan 2023 19:41:01 +0530 Message-Id: <20230103141102.772228-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103141102.772228-1-apatel@ventanamicro.com> References: <20230103141102.772228-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add DT bindings for a separate RISC-V timer DT node which can be used to describe implementation specific behaviour (such as timer interrupt not triggered during non-retentive suspend). Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Rob Herring Acked-by: Palmer Dabbelt --- .../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Doc= umentation/devicetree/bindings/timer/riscv,timer.yaml new file mode 100644 index 000000000000..38d67e1a5a79 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V timer + +maintainers: + - Anup Patel + +description: |+ + RISC-V platforms always have a RISC-V timer device for the supervisor-mo= de + based on the time CSR defined by the RISC-V privileged specification. The + timer interrupts of this device are configured using the RISC-V SBI Time + extension or the RISC-V Sstc extension. + + The clock frequency of RISC-V timer device is specified via the + "timebase-frequency" DT property of "/cpus" DT node which is described + in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + enum: + - riscv,timer + + interrupts-extended: + minItems: 1 + maxItems: 4096 # Should be enough? + + riscv,timer-cannot-wake-cpu: + type: boolean + description: + If present, the timer interrupt cannot wake up the CPU from one or + more suspend/idle states. + +additionalProperties: false + +required: + - compatible + - interrupts-extended + +examples: + - | + timer { + compatible =3D "riscv,timer"; + interrupts-extended =3D <&cpu1intc 5>, + <&cpu2intc 5>, + <&cpu3intc 5>, + <&cpu4intc 5>; + }; +... --=20 2.34.1 From nobody Tue Sep 16 14:11:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52F7CC46467 for ; Tue, 3 Jan 2023 14:12:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237812AbjACOMG (ORCPT ); Tue, 3 Jan 2023 09:12:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237804AbjACOLb (ORCPT ); Tue, 3 Jan 2023 09:11:31 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65A5010B67 for ; Tue, 3 Jan 2023 06:11:29 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id o31-20020a17090a0a2200b00223fedffb30so31203028pjo.3 for ; Tue, 03 Jan 2023 06:11:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bVqqR8oYcz8ddBS+TT8ZlpXaMsGagFVr9rYdfxP/rIg=; b=kW8IcmMw6snEgGMOnD3J92gTuk6kXiuNTjEsajrxn76hj89qmb0gT/j1/qFeeaZcTK J7LFnoEKURv0KZL/X29slpZTSrySPN5sRBqG+GbClcwUnXFtzoS6NbTHnUJ8vGga4irf 9lxRXfjRRUsTze6dbDeO3NxWQPkVIvEoltyCBU1H9fZNrbEqGBmVyV/XBJpp3FSgVUTH Yil5BTK+LuQ0bQZ80GE9sQ//XmF1G1yIs+uwTCzAZyhAXRaLkvK+gWt2lO/sVASuB8KD qTS7RFi9IQW6i5O1skxC9zShTpxzBKgZj+Y6P81xB5o6I+lZJxTCH2jgccHosXEmTglz TJPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bVqqR8oYcz8ddBS+TT8ZlpXaMsGagFVr9rYdfxP/rIg=; b=WLwO1GJRkrjKifikYdcIQayUSOEpwTvXqVAasGiMAK0rn8jf0vhkL6/XPvLrFIyUq7 +vX81tqiR52P8Eq2pCxlCk0haEkkUQdrrTpaE+JpD6J+P6ri0koajTJf3FYZZJyg1NRu wEMVcNnAfW+h/eH3EowCBNlhR2mC5U/l4bm/sAKCmnrUMprJ65Wl8LSRgqC0iHw0EJ9w 2Bd4DFp/NehA/hG7odMuhj0IcDDnMRa564NGtNe8hqIiG4AOKwSQ+YKy4hQL6HrM5T3L 0z6h2XnmX7+YfqpHUokL2kixb/ft6ZGNOLX1c3s0Ut3Md+NjmlxGIAgY+Ky0dSVltKXp D1BA== X-Gm-Message-State: AFqh2kqJr7RS3dEpxPdfyGkYwwZV1x3elQ47F2NiTdIAjq2iSQ6xeGjq XTZUyJjo+2TDOQMVvCMMw0MOI/YcNB92298K X-Google-Smtp-Source: AMrXdXvHiZ2mubjd6ktVYDES2Wzs1jni6FSXsvkL3Z/HXI4YqE6gXpPnnbII14HUfEZDsTFUbo5JNw== X-Received: by 2002:a17:902:7610:b0:192:751d:b2e4 with SMTP id k16-20020a170902761000b00192751db2e4mr28680533pll.48.1672755088680; Tue, 03 Jan 2023 06:11:28 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([171.76.85.241]) by smtp.gmail.com with ESMTPSA id l3-20020a170902e2c300b00192bf7eaf28sm6146117plc.286.2023.01.03.06.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jan 2023 06:11:28 -0800 (PST) From: Anup Patel To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Daniel Lezcano , Thomas Gleixner Cc: Andrew Jones , Atish Patra , Samuel Holland , Conor Dooley , Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Palmer Dabbelt Subject: [PATCH v6 3/3] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT Date: Tue, 3 Jan 2023 19:41:02 +0530 Message-Id: <20230103141102.772228-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103141102.772228-1-apatel@ventanamicro.com> References: <20230103141102.772228-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only when riscv,timer-cannot-wake-cpu DT property is present in the RISC-V timer DT node. This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device based on RISC-V platform capabilities rather than having it set for all RISC-V platforms. Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt --- drivers/clocksource/timer-riscv.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index a0d66fabf073..1b4b36df5484 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -28,6 +28,7 @@ #include =20 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available); +static bool riscv_timer_cannot_wake_cpu; =20 static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu) =20 ce->cpumask =3D cpumask_of(cpu); ce->irq =3D riscv_clock_event_irq; + if (riscv_timer_cannot_wake_cpu) + ce->features |=3D CLOCK_EVT_FEAT_C3STOP; clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); =20 enable_percpu_irq(riscv_clock_event_irq, @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_no= de *n) if (cpuid !=3D smp_processor_id()) return 0; =20 + child =3D of_find_compatible_node(NULL, NULL, "riscv,timer"); + if (child) { + riscv_timer_cannot_wake_cpu =3D of_property_read_bool(child, + "riscv,timer-cannot-wake-cpu"); + of_node_put(child); + } + domain =3D NULL; child =3D of_get_compatible_child(n, "riscv,cpu-intc"); if (!child) { --=20 2.34.1