From nobody Wed Sep 3 20:36:33 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B63CC3DA7D for ; Tue, 3 Jan 2023 04:21:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232602AbjACEVo (ORCPT ); Mon, 2 Jan 2023 23:21:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232790AbjACEVe (ORCPT ); Mon, 2 Jan 2023 23:21:34 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6411237; Mon, 2 Jan 2023 20:21:31 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3034LNKs119502; Mon, 2 Jan 2023 22:21:23 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1672719683; bh=DPrpSmIW2y5MH7j5wtzLt5gWoOX3ZEnZJS4bV9emXDo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rHKX02MiGt3HtCDxWZLQ7ObkMjecutLSV4kaSIsMP81Dj/LWuKvfJIHjjSJGNyyKY CihSalWx3BvtsfzTts5hkADivH/e79p6ToPUAUAOYdv2Ojved0srXjCxLKBMqzJVIb giZzz3U4NHbatP/XbENsCTOTXl98ur4jgkFHdPnA= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3034LMxD025957 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 2 Jan 2023 22:21:23 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 2 Jan 2023 22:21:22 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 2 Jan 2023 22:21:22 -0600 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3034LDwt084970; Mon, 2 Jan 2023 22:21:19 -0600 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski CC: , , , Subject: [PATCH 2/4] arm64: dts: ti: k3-am62a-main: Add more peripheral nodes Date: Tue, 3 Jan 2023 09:51:08 +0530 Message-ID: <20230103042110.1092122-3-vigneshr@ti.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230103042110.1092122-1-vigneshr@ti.com> References: <20230103042110.1092122-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add DT nodes for main domain SPI, PWM, DMA, CPSW (ethernet), mailbox, spinlock, USB and CAN. Co-developed-by: Bryan Brattlof Signed-off-by: Bryan Brattlof Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 365 ++++++++++++++++++++++ 1 file changed, 365 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index bc4b50bcd177..393a1a40b68b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -48,6 +48,18 @@ main_conf: syscon@100000 { #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x00 0x00 0x00100000 0x20000>; + + phy_gmii_sel: phy@4044 { + compatible =3D "ti,am654-phy-gmii-sel"; + reg =3D <0x4044 0x8>; + #phy-cells =3D <1>; + }; + + epwm_tbclk: clock-controller@4130 { + compatible =3D "ti,am62-epwm-tbclk", "syscon"; + reg =3D <0x4130 0x4>; + #clock-cells =3D <1>; + }; }; =20 dmss: bus@48000000 { @@ -69,6 +81,67 @@ secure_proxy_main: mailbox@4d000000 { interrupt-names =3D "rx_012"; interrupts =3D ; }; + + inta_main_dmss: interrupt-controller@48000000 { + compatible =3D "ti,sci-inta"; + reg =3D <0x00 0x48000000 0x00 0x100000>; + #interrupt-cells =3D <0>; + interrupt-controller; + interrupt-parent =3D <&gic500>; + msi-controller; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <28>; + ti,interrupt-ranges =3D <6 70 34>; + ti,unmapped-event-sources =3D <&main_bcdma>, <&main_pktdma>; + }; + + main_bcdma: dma-controller@485c0100 { + compatible =3D "ti,am64-dmss-bcdma"; + reg =3D <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>; + reg-names =3D "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + msi-parent =3D <&inta_main_dmss>; + #dma-cells =3D <3>; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <26>; + ti,sci-rm-range-bchan =3D <0x20>; /* BLOCK_COPY_CHAN */ + ti,sci-rm-range-rchan =3D <0x21>; /* SPLIT_TR_RX_CHAN */ + ti,sci-rm-range-tchan =3D <0x22>; /* SPLIT_TR_TX_CHAN */ + }; + + main_pktdma: dma-controller@485c0000 { + compatible =3D "ti,am64-dmss-pktdma"; + reg =3D <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>; + reg-names =3D "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent =3D <&inta_main_dmss>; + #dma-cells =3D <2>; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <30>; + ti,sci-rm-range-tchan =3D <0x23>, /* UNMAPPED_TX_CHAN */ + <0x24>, /* CPSW_TX_CHAN */ + <0x25>, /* SAUL_TX_0_CHAN */ + <0x26>; /* SAUL_TX_1_CHAN */ + ti,sci-rm-range-tflow =3D <0x10>, /* RING_UNMAPPED_TX_CHAN */ + <0x11>, /* RING_CPSW_TX_CHAN */ + <0x12>, /* RING_SAUL_TX_0_CHAN */ + <0x13>; /* RING_SAUL_TX_1_CHAN */ + ti,sci-rm-range-rchan =3D <0x29>, /* UNMAPPED_RX_CHAN */ + <0x2b>, /* CPSW_RX_CHAN */ + <0x2d>, /* SAUL_RX_0_CHAN */ + <0x2f>, /* SAUL_RX_1_CHAN */ + <0x31>, /* SAUL_RX_2_CHAN */ + <0x33>; /* SAUL_RX_3_CHAN */ + ti,sci-rm-range-rflow =3D <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ + <0x2c>, /* FLOW_CPSW_RX_CHAN */ + <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ + <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ + }; }; =20 dmsc: system-controller@44043000 { @@ -222,6 +295,39 @@ main_i2c3: i2c@20030000 { status =3D "disabled"; }; =20 + main_spi0: spi@20100000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x20100000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 141 0>; + status =3D "disabled"; + }; + + main_spi1: spi@20110000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x20110000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 142 0>; + status =3D "disabled"; + }; + + main_spi2: spi@20120000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x20120000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 143 0>; + status =3D "disabled"; + }; + main_gpio_intr: interrupt-controller@a00000 { compatible =3D "ti,sci-intr"; reg =3D <0x00 0x00a00000 0x00 0x800>; @@ -295,4 +401,263 @@ sdhci1: mmc@fa00000 { no-1-8-v; status =3D "disabled"; }; + + usbss0: dwc3-usb@f900000 { + compatible =3D "ti,am62-usb"; + reg =3D <0x00 0x0f900000 0x00 0x800>; + clocks =3D <&k3_clks 161 3>; + clock-names =3D "ref"; + ti,syscon-phy-pll-refclk =3D <&wkup_conf 0x4008>; + #address-cells =3D <2>; + #size-cells =3D <2>; + power-domains =3D <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + ranges; + status =3D "disabled"; + + usb0: usb@31000000 { + compatible =3D "snps,dwc3"; + reg =3D<0x00 0x31000000 0x00 0x50000>; + interrupts =3D , /* irq.0 */ + ; /* irq.0 */ + interrupt-names =3D "host", "peripheral"; + maximum-speed =3D "high-speed"; + dr_mode =3D "otg"; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible =3D "ti,am62-usb"; + reg =3D <0x00 0x0f910000 0x00 0x800>; + clocks =3D <&k3_clks 162 3>; + clock-names =3D "ref"; + ti,syscon-phy-pll-refclk =3D <&wkup_conf 0x4018>; + #address-cells =3D <2>; + #size-cells =3D <2>; + power-domains =3D <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status =3D "disabled"; + + usb1: usb@31100000 { + compatible =3D "snps,dwc3"; + reg =3D<0x00 0x31100000 0x00 0x50000>; + interrupts =3D , /* irq.0 */ + ; /* irq.0 */ + interrupt-names =3D "host", "peripheral"; + maximum-speed =3D "high-speed"; + dr_mode =3D "otg"; + }; + }; + + fss: bus@fc00000 { + compatible =3D "simple-bus"; + reg =3D <0x00 0x0fc00000 0x00 0x70000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + ospi0: spi@fc40000 { + compatible =3D "ti,am654-ospi", "cdns,qspi-nor"; + reg =3D <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts =3D ; + cdns,fifo-depth =3D <256>; + cdns,fifo-width =3D <4>; + cdns,trigger-address =3D <0x0>; + clocks =3D <&k3_clks 75 7>; + assigned-clocks =3D <&k3_clks 75 7>; + assigned-clock-parents =3D <&k3_clks 75 8>; + assigned-clock-rates =3D <166666666>; + power-domains =3D <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cpsw3g: ethernet@8000000 { + compatible =3D "ti,am642-cpsw-nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + reg =3D <0x0 0x8000000 0x0 0x200000>; + reg-names =3D "cpsw_nuss"; + ranges =3D <0x0 0x0 0x0 0x8000000 0x0 0x200000>; + clocks =3D <&k3_clks 13 0>; + assigned-clocks =3D <&k3_clks 13 3>; + assigned-clock-parents =3D <&k3_clks 13 11>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + dmas =3D <&main_pktdma 0xc600 15>, + <&main_pktdma 0xc601 15>, + <&main_pktdma 0xc602 15>, + <&main_pktdma 0xc603 15>, + <&main_pktdma 0xc604 15>, + <&main_pktdma 0xc605 15>, + <&main_pktdma 0xc606 15>, + <&main_pktdma 0xc607 15>, + <&main_pktdma 0x4600 15>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpsw_port1: port@1 { + reg =3D <1>; + ti,mac-only; + label =3D "port1"; + phys =3D <&phy_gmii_sel 1>; + mac-address =3D [00 00 00 00 00 00]; + ti,syscon-efuse =3D <&wkup_conf 0x200>; + }; + + cpsw_port2: port@2 { + reg =3D <2>; + ti,mac-only; + label =3D "port2"; + phys =3D <&phy_gmii_sel 2>; + mac-address =3D [00 00 00 00 00 00]; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio","ti,davinci_mdio"; + reg =3D <0x0 0xf00 0x0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 13 0>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + }; + + cpts@3d000 { + compatible =3D "ti,j721e-cpts"; + reg =3D <0x0 0x3d000 0x0 0x400>; + clocks =3D <&k3_clks 13 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + + hwspinlock: spinlock@2a000000 { + compatible =3D "ti,am64-hwspinlock"; + reg =3D <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells =3D <1>; + }; + + mailbox0_cluster0: mailbox@29000000 { + compatible =3D "ti,am64-mailbox"; + reg =3D <0x00 0x29000000 0x00 0x200>; + interrupts =3D ; + #mbox-cells =3D <1>; + ti,mbox-num-users =3D <4>; + ti,mbox-num-fifos =3D <16>; + }; + + mailbox0_cluster1: mailbox@29010000 { + compatible =3D "ti,am64-mailbox"; + reg =3D <0x00 0x29010000 0x00 0x200>; + interrupts =3D ; + #mbox-cells =3D <1>; + ti,mbox-num-users =3D <4>; + ti,mbox-num-fifos =3D <16>; + }; + + mailbox0_cluster2: mailbox@29020000 { + compatible =3D "ti,am64-mailbox"; + reg =3D <0x00 0x29020000 0x00 0x200>; + interrupts =3D ; + #mbox-cells =3D <1>; + ti,mbox-num-users =3D <4>; + ti,mbox-num-fifos =3D <16>; + }; + + mailbox0_cluster3: mailbox@29030000 { + compatible =3D "ti,am64-mailbox"; + reg =3D <0x00 0x29030000 0x00 0x200>; + interrupts =3D ; + #mbox-cells =3D <1>; + ti,mbox-num-users =3D <4>; + ti,mbox-num-fifos =3D <16>; + }; + + main_mcan0: can@20701000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 98 6>, <&k3_clks 98 1>; + clock-names =3D "hclk", "cclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + status =3D "disabled"; + }; + + epwm0: pwm@23000000 { + compatible =3D "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x23000000 0x00 0x100>; + power-domains =3D <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&epwm_tbclk 0>, <&k3_clks 86 0>; + clock-names =3D "tbclk", "fck"; + status =3D "disabled"; + }; + + epwm1: pwm@23010000 { + compatible =3D "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x23010000 0x00 0x100>; + power-domains =3D <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&epwm_tbclk 1>, <&k3_clks 87 0>; + clock-names =3D "tbclk", "fck"; + status =3D "disabled"; + }; + + epwm2: pwm@23020000 { + compatible =3D "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x23020000 0x00 0x100>; + power-domains =3D <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&epwm_tbclk 2>, <&k3_clks 88 0>; + clock-names =3D "tbclk", "fck"; + status =3D "disabled"; + }; + + ecap0: pwm@23100000 { + compatible =3D "ti,am3352-ecap"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x23100000 0x00 0x100>; + power-domains =3D <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 51 0>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + + ecap1: pwm@23110000 { + compatible =3D "ti,am3352-ecap"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x23110000 0x00 0x100>; + power-domains =3D <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 52 0>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + + ecap2: pwm@23120000 { + compatible =3D "ti,am3352-ecap"; + #pwm-cells =3D <3>; + reg =3D <0x00 0x23120000 0x00 0x100>; + power-domains =3D <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 53 0>; + clock-names =3D "fck"; + status =3D "disabled"; + }; }; --=20 2.39.0