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[2001:1c06:2302:5600:b443:9db7:1e5c:4fd5]) by smtp.gmail.com with ESMTPSA id q26-20020a17090676da00b008302732f569sm13564648ejn.78.2023.01.02.17.09.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 17:09:10 -0800 (PST) From: Bryan O'Donoghue To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, djakov@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: bryan.odonoghue@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benl@squareup.com, shawn.guo@linaro.org, fabien.parent@linaro.org, leo.yan@linaro.org, dmitry.baryshkov@linaro.org Subject: [PATCH v2 1/7] dt-bindings: interconnect: Move interconnect child node definition Date: Tue, 3 Jan 2023 01:08:58 +0000 Message-Id: <20230103010904.3201835-2-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> References: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" New properties should be defined before the allOf. Move the patternProperties definition to before the additionalProperties: false in this file. Fixes: dfeef93fe3ee ("dt-bindings: interconnect: Convert snoc-mm to a sub-n= ode of snoc") Signed-off-by: Bryan O'Donoghue --- .../bindings/interconnect/qcom,rpm.yaml | 62 +++++++++---------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b= /Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 4b37aa88a375b..50b80ca07e433 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -62,6 +62,37 @@ properties: power-domains: maxItems: 1 =20 +# Child node's properties +patternProperties: + '^interconnect-[a-z0-9]+$': + type: object + description: + snoc-mm is a child of snoc, sharing snoc's register address space. + + properties: + compatible: + enum: + - qcom,msm8939-snoc-mm + + '#interconnect-cells': + const: 1 + + clock-names: + items: + - const: bus + - const: bus_a + + clocks: + items: + - description: Bus Clock + - description: Bus A Clock + + required: + - compatible + - '#interconnect-cells' + - clock-names + - clocks + required: - compatible - reg @@ -109,37 +140,6 @@ allOf: - description: Bus Clock - description: Bus A Clock =20 - # Child node's properties - patternProperties: - '^interconnect-[a-z0-9]+$': - type: object - description: - snoc-mm is a child of snoc, sharing snoc's register address sp= ace. - - properties: - compatible: - enum: - - qcom,msm8939-snoc-mm - - '#interconnect-cells': - const: 1 - - clock-names: - items: - - const: bus - - const: bus_a - - clocks: - items: - - description: Bus Clock - - description: Bus A Clock - - required: - - compatible - - '#interconnect-cells' - - clock-names - - clocks - - if: properties: compatible: --=20 2.34.1 From nobody Sat Feb 7 02:58:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74E97C3DA7A for ; Tue, 3 Jan 2023 01:09:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232712AbjACBJq (ORCPT ); Mon, 2 Jan 2023 20:09:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236371AbjACBJR (ORCPT ); Mon, 2 Jan 2023 20:09:17 -0500 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 522ED95BD for ; Mon, 2 Jan 2023 17:09:13 -0800 (PST) Received: by mail-ej1-x636.google.com with SMTP id vm8so63216876ejc.2 for ; Mon, 02 Jan 2023 17:09:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VA+8K2hv48fLrDkZSZadZsjZ4I4yG7EsHjILu1Lcy8k=; b=Wss+XeFlnyffhaqysFEayCASUdOiUCysj/G4AwdIknXzjKiDrI+u2Mu+mWGLeQl/By vLi0ZELEt7uaPV03lIxrPKbiFg2xh/UxaaVCn9DLiwOXLC9gXK7mSDnbU7rzSjBDA6Yw 6WKYJ9LIebrRDM4BW82GoeBBbd5+DncUkuZwdKFMhW3UqhWRwn+xvtJLG/tZmyS6yrpk YrH3UhcSVVpojnW5HrIOhlrLlZUWeqOK0y6UPHoU1igidlNfd6eGv5YKeSQpSXO24aGT x4af2T+bkNT4+wTFTJ1mCXMETidRhl3PVukhtT91So2sWhWuVeeqfEoM33zh4Q0A0VoY 2uKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VA+8K2hv48fLrDkZSZadZsjZ4I4yG7EsHjILu1Lcy8k=; b=DfqBZam6k3VHeXMIB4ZwWwoQ1vZewGDEOkTyexOay0a+yvmhElbpn0lPbjdE/Hxa31 oR8qRD1DO4DJtMLhEZ0AVS/AsBh1PpvP1WZl3O2B21kbnRLU+jUjO1sp+6PtNvo4kj8o pcGPjX1ZIlv+JYruAkQXYirCBJXtCdO9gLz24VxAzp+jRYKfWu6/NpMaXAqUjyPLe8aw EE/Q0JhJKN0qswnHKTaiB3a3t7c15xCPsiz3obFTtQdZTjc2tNskx0B0DrrXI724wMQE vM9HYpZPEYSDW2I4T2uMgqUeu2nxKmRyq8xjsHE3cipjp/fSr8LkMXsBE5UUGvr9P2xW h5bQ== X-Gm-Message-State: AFqh2kpBCT61+RjCwUAo1w9eM758Xud4Ao3DH8lk8zZfXBLOzhtruD0s L6Sl/JAiQdBLo569CrEsuaZIoQ== X-Google-Smtp-Source: AMrXdXtv38Mvh9+DDu01Iy912rW8xdF/I3+IYPN7USkF4WcOK19pg9rzTdweuTptiQXe8m/pAc6FRQ== X-Received: by 2002:a17:906:e2d3:b0:7c0:deb3:596a with SMTP id gr19-20020a170906e2d300b007c0deb3596amr39743561ejb.70.1672708151926; Mon, 02 Jan 2023 17:09:11 -0800 (PST) Received: from planet9.chello.ie (2001-1c06-2302-5600-b443-9db7-1e5c-4fd5.cable.dynamic.v6.ziggo.nl. [2001:1c06:2302:5600:b443:9db7:1e5c:4fd5]) by smtp.gmail.com with ESMTPSA id q26-20020a17090676da00b008302732f569sm13564648ejn.78.2023.01.02.17.09.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 17:09:11 -0800 (PST) From: Bryan O'Donoghue To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, djakov@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: bryan.odonoghue@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benl@squareup.com, shawn.guo@linaro.org, fabien.parent@linaro.org, leo.yan@linaro.org, dmitry.baryshkov@linaro.org Subject: [PATCH v2 2/7] dt-bindings: arm: qcom: Document MSM8939 SoC binding Date: Tue, 3 Jan 2023 01:08:59 +0000 Message-Id: <20230103010904.3201835-3-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> References: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the MSM8939 and supported boards in upstream Sony "Tulip" M4 Aqua and Square APQ8039 T2. MSM8939 is one of the older SoCs so we need to expand the list of qcom,board-ids to allow for the bootloader DTS board-id matching dependency. Signed-off-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 27063a045bd0a..300b56718a8d3 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -35,6 +35,7 @@ description: | mdm9615 msm8226 msm8916 + msm8939 msm8956 msm8974 msm8976 @@ -160,6 +161,12 @@ properties: - samsung,s3ve3g - const: qcom,msm8226 =20 + - items: + - enum: + - sony,kanuti-tulip + - square,apq8039-t2 + - const: qcom,msm8939 + - items: - enum: - sony,kugo-row @@ -922,6 +929,7 @@ allOf: - qcom,apq8026 - qcom,apq8094 - qcom,apq8096 + - qcom,msm8939 - qcom,msm8992 - qcom,msm8994 - qcom,msm8996 --=20 2.34.1 From nobody Sat Feb 7 02:58:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 247BBC3DA7A for ; Tue, 3 Jan 2023 01:09:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236628AbjACBJ4 (ORCPT ); Mon, 2 Jan 2023 20:09:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236451AbjACBJU (ORCPT ); Mon, 2 Jan 2023 20:09:20 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C3F2A443 for ; Mon, 2 Jan 2023 17:09:14 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id x22so70100371ejs.11 for ; Mon, 02 Jan 2023 17:09:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+balc+MRgedWafjUxob4M65cvBwrRUb1ln9bhd9UBPw=; b=KUblhxszEPc8VviOgPBZQSF/dWySeQ+15/+JKg3M6LwC+KjmP4oNWnY7AGHUI2UqN6 xbfHaj15VgVoSVboOCncvwIg44dhDIF4dx1aU+u9oa2bpX0YCB4qsh/fanJuTeZOKbXb CxhthhdL2tv9CO+pCmnvOZFclIy6NVWAi0vKsU7XNX1vDXd2a+QIuhBFtyf4fX6RWJ7H +okSSjcIlkE4bp7LPS44K8yKYZZoiSUhKZwKdFLhPO4Ft337ZG+0Zqfg/JxUCQM+nZNj /ockMyzHX7fnZOAZ+3iBblIneXsfC9KjPmsa878yLLe9XP2XP0qmIAwgONwn3Rip2d/T s3vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+balc+MRgedWafjUxob4M65cvBwrRUb1ln9bhd9UBPw=; b=T6HHiPCIZ1oxuI0Iia840HX7MkPsNv41taJLULbQe5WPsVQeoj2ZW+CgNsu32wtKXi +AYVGrCgikEGtrfCaUehPxSLwaYrRt6aX7sX/Ns/Vykc2MXZlGfKuJfVVYgaF5GIKi+b CyiUyi5kBrNIiuSMyd57bmmirreRMHBg6XlhbzMu0+wGgpZd8BTnLhXdL6bTf9W6kLZ8 q5FHUFelMhvut9dat+QvAP75kJYQgTzsAh7AkfzHFSDiP8W3vz4wt7An+klWglrX4cez lxqSzr/Pw5YY7okpBStRi6kkvNesErUuelIBXBDcw3Hka8FfvxYAKcnjFsU85lTUG0a6 9b6Q== X-Gm-Message-State: AFqh2kqBKL2iVsHpXt1+TthjAlrBEhC5cLJela7Nptiwcv0db75+Pc1M Xpst3tV/k1/w52bR96kgB4MHAQ== X-Google-Smtp-Source: AMrXdXt/04HbPLb4VObsdtgNjvhaI1eQZZhOUZBAY5X+BNtFSISQyXoy0yIulyZu2RM7fVR3FEmXlg== X-Received: by 2002:a17:906:6d47:b0:7c0:c312:acaa with SMTP id a7-20020a1709066d4700b007c0c312acaamr35522054ejt.49.1672708152930; Mon, 02 Jan 2023 17:09:12 -0800 (PST) Received: from planet9.chello.ie (2001-1c06-2302-5600-b443-9db7-1e5c-4fd5.cable.dynamic.v6.ziggo.nl. [2001:1c06:2302:5600:b443:9db7:1e5c:4fd5]) by smtp.gmail.com with ESMTPSA id q26-20020a17090676da00b008302732f569sm13564648ejn.78.2023.01.02.17.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 17:09:12 -0800 (PST) From: Bryan O'Donoghue To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, djakov@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: bryan.odonoghue@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benl@squareup.com, shawn.guo@linaro.org, fabien.parent@linaro.org, leo.yan@linaro.org, dmitry.baryshkov@linaro.org Subject: [PATCH v2 3/7] dt-bindings: soc: qcom: smd-rpm: Exclude MSM8936 from glink-channels Date: Tue, 3 Jan 2023 01:09:00 +0000 Message-Id: <20230103010904.3201835-4-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> References: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MSM8936/MSM8939 should like MSM8916 not require glink-channels. Signed-off-by: Bryan O'Donoghue Acked-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b= /Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 11c0f4dd797ce..16fd67c0bd1fd 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -80,6 +80,7 @@ if: enum: - qcom,rpm-apq8084 - qcom,rpm-msm8916 + - qcom,rpm-msm8936 - qcom,rpm-msm8974 - qcom,rpm-msm8976 - qcom,rpm-msm8953 --=20 2.34.1 From nobody Sat Feb 7 02:58:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA7D7C3DA7A for ; Tue, 3 Jan 2023 01:10:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236721AbjACBK0 (ORCPT ); Mon, 2 Jan 2023 20:10:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236482AbjACBJW (ORCPT ); Mon, 2 Jan 2023 20:09:22 -0500 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB03F6462 for ; Mon, 2 Jan 2023 17:09:15 -0800 (PST) Received: by mail-ej1-x62b.google.com with SMTP id x22so70100456ejs.11 for ; Mon, 02 Jan 2023 17:09:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M4tskESB+OutNeK0l07yDB7qa3x+enacxIfn3VQe8AQ=; b=Nz6tsdNQQjC5lRQzcoGs0hPvA4yk57Vd+9bUpElQ2go5gTorG6r8iIZx5ozHCpndGs WIH9fpFFWSo7/M3sRNifNx4IxyTzQWZwbp11LPXOJv46E0IINpKrt8uPTw1bcmdoyzNN HJTac9Azdm+LxopILtKKvPGFv5BJRn3vbRbuxYzys8OgNZ532VXxxJGRUjI2YyhIB9We ia+pOZ2Nkkm9m9cazWOudgK0wGA6zJBHCOFIs9frRzRb/gm8Rhz6XyIMtURWwWW0km4F ZVXIyYPJQHcJj1G+ucltGxWEj3gyxwgfAuhMNFWMatnCmFbinbnXdmaXzPao2uV2ltl6 JL8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M4tskESB+OutNeK0l07yDB7qa3x+enacxIfn3VQe8AQ=; b=Xvju5WVhmOAVV1peIYBIZq0ePa73KYJVQdStmzX/pv4hSoNdYimADJQTeLN1mbddVi aMZryttZADGers55mynsu/NRQBlfVl1MEj093o55sYnTbUKFIlTOouJxFdzL3VV3mnQA gF4yeGoJ/jcMsDSJuY/B4k1uBnNnLAqk6ug7ajaxb59/j1cNtwxNLjnzVltSR0OV7ijS M/6p8iNskM9QxX7QcMgtW3N81SKqS37eXscUsfbaAvgBsWvpWv+kJr4AV/x26Pe83TEj Y1Ck+iJ8jOfHLpuMmtNNtNcACpcirYsgb0D2bEmqX9Ec1NcjyTDopX1ylGKYmoIWf7CE 7T6Q== X-Gm-Message-State: AFqh2kq5LKE4ASU865323IqUyAnEAwcQmZsyzhqnNx69HO3/a3MizEha 7DM4RzycPdJvLP2BSdiHwO7nSQ== X-Google-Smtp-Source: AMrXdXsk4x9iQAy1Abh69wbCb0YxxuLQPPqhad9utNPb8F0L7g2xULi5YdsHrijLyGiSEn3p28RMfg== X-Received: by 2002:a17:907:c315:b0:7c1:b65:11d with SMTP id tl21-20020a170907c31500b007c10b65011dmr32639667ejc.12.1672708154227; Mon, 02 Jan 2023 17:09:14 -0800 (PST) Received: from planet9.chello.ie (2001-1c06-2302-5600-b443-9db7-1e5c-4fd5.cable.dynamic.v6.ziggo.nl. [2001:1c06:2302:5600:b443:9db7:1e5c:4fd5]) by smtp.gmail.com with ESMTPSA id q26-20020a17090676da00b008302732f569sm13564648ejn.78.2023.01.02.17.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 17:09:13 -0800 (PST) From: Bryan O'Donoghue To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, djakov@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: bryan.odonoghue@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benl@squareup.com, shawn.guo@linaro.org, fabien.parent@linaro.org, leo.yan@linaro.org, dmitry.baryshkov@linaro.org, Jun Nie , James Willcox , Joseph Gates , Max Chen , Zac Crosby , Vincent Knecht , Stephan Gerhold Subject: [PATCH v2 4/7] arm64: dts: qcom: Add msm8939 SoC Date: Tue, 3 Jan 2023 01:09:01 +0000 Message-Id: <20230103010904.3201835-5-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> References: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add msm8939 a derivative SoC of msm8916. This SoC contains a number of key differences to msm8916. - big.LITTLE Octa Core - quad 1.5GHz + quad 1.0GHz - DRAM 1x800 LPDDR3 - Camera 4+4 lane CSI - Venus @ 1080p60 HEVC - DSI x 2 - Adreno A405 - WiFi wcn3660/wcn3680b 802.11ac Co-developed-by: Shawn Guo Signed-off-by: Shawn Guo Co-developed-by: Jun Nie Signed-off-by: Jun Nie Co-developed-by: Benjamin Li Signed-off-by: Benjamin Li Co-developed-by: James Willcox Signed-off-by: James Willcox Co-developed-by: Leo Yan Signed-off-by: Leo Yan Co-developed-by: Joseph Gates Signed-off-by: Joseph Gates Co-developed-by: Max Chen Signed-off-by: Max Chen Co-developed-by: Zac Crosby Signed-off-by: Zac Crosby Co-developed-by: Vincent Knecht Signed-off-by: Vincent Knecht Co-developed-by: Stephan Gerhold Signed-off-by: Stephan Gerhold Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 2470 +++++++++++++++++++++++++ 1 file changed, 2470 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8939.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qc= om/msm8939.dtsi new file mode 100644 index 0000000000000..03714cdb8b69e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -0,0 +1,2470 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + qcom,msm-id =3D <239 0>, <239 0x30000>, <241 0x30000>, <263 0x30000>; + + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + mmc0 =3D &sdhc_1; /* SDC1 eMMC slot */ + mmc1 =3D &sdhc_2; /* SDC2 SD card slot */ + }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + clock-output-names =3D "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "sleep_clk"; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@100 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + enable-method =3D "spin-table"; + reg =3D <0x100>; + next-level-cache =3D <&L2_1>; + power-domains =3D <&vreg_dummy>; + power-domain-names =3D "cpr"; + qcom,acc =3D <&acc0>; + qcom,saw =3D <&saw0>; + cpu-idle-states =3D <&CPU_SLEEP_0>; + clocks =3D <&apcs1_mbox>; + #cooling-cells =3D <2>; + L2_1: l2-cache@1 { + compatible =3D "cache"; + cache-level =3D <2>; + }; + }; + + cpu1: cpu@101 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + enable-method =3D "spin-table"; + reg =3D <0x101>; + next-level-cache =3D <&L2_1>; + power-domains =3D <&vreg_dummy>; + power-domain-names =3D "cpr"; + qcom,acc =3D <&acc1>; + qcom,saw =3D <&saw1>; + cpu-idle-states =3D <&CPU_SLEEP_0>; + clocks =3D <&apcs1_mbox>; + #cooling-cells =3D <2>; + }; + + cpu2: cpu@102 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + enable-method =3D "spin-table"; + reg =3D <0x102>; + next-level-cache =3D <&L2_1>; + power-domains =3D <&vreg_dummy>; + power-domain-names =3D "cpr"; + qcom,acc =3D <&acc2>; + qcom,saw =3D <&saw2>; + cpu-idle-states =3D <&CPU_SLEEP_0>; + clocks =3D <&apcs1_mbox>; + #cooling-cells =3D <2>; + }; + + cpu3: cpu@103 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + enable-method =3D "spin-table"; + reg =3D <0x103>; + next-level-cache =3D <&L2_1>; + power-domains =3D <&vreg_dummy>; + power-domain-names =3D "cpr"; + qcom,acc =3D <&acc3>; + qcom,saw =3D <&saw3>; + cpu-idle-states =3D <&CPU_SLEEP_0>; + clocks =3D <&apcs1_mbox>; + #cooling-cells =3D <2>; + }; + + cpu4: cpu@0 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + enable-method =3D "spin-table"; + reg =3D <0x0>; + qcom,acc =3D <&acc4>; + qcom,saw =3D <&saw4>; + cpu-idle-states =3D <&CPU_SLEEP_0>; + clocks =3D <&apcs0_mbox>; + #cooling-cells =3D <2>; + next-level-cache =3D <&L2_0>; + power-domains =3D <&vreg_dummy>; + power-domain-names =3D "cpr"; + L2_0: l2-cache@0 { + compatible =3D "cache"; + cache-level =3D <2>; + }; + }; + + cpu5: cpu@1 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + enable-method =3D "spin-table"; + reg =3D <0x1>; + next-level-cache =3D <&L2_0>; + power-domains =3D <&vreg_dummy>; + power-domain-names =3D "cpr"; + qcom,acc =3D <&acc5>; + qcom,saw =3D <&saw5>; + cpu-idle-states =3D <&CPU_SLEEP_0>; + clocks =3D <&apcs0_mbox>; + #cooling-cells =3D <2>; + }; + + cpu6: cpu@2 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + enable-method =3D "spin-table"; + reg =3D <0x2>; + next-level-cache =3D <&L2_0>; + power-domains =3D <&vreg_dummy>; + power-domain-names =3D "cpr"; + qcom,acc =3D <&acc6>; + qcom,saw =3D <&saw6>; + cpu-idle-states =3D <&CPU_SLEEP_0>; + clocks =3D <&apcs0_mbox>; + #cooling-cells =3D <2>; + }; + + cpu7: cpu@3 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + enable-method =3D "spin-table"; + reg =3D <0x3>; + next-level-cache =3D <&L2_0>; + power-domains =3D <&vreg_dummy>; + power-domain-names =3D "cpr"; + qcom,acc =3D <&acc7>; + qcom,saw =3D <&saw7>; + cpu-idle-states =3D <&CPU_SLEEP_0>; + clocks =3D <&apcs0_mbox>; + #cooling-cells =3D <2>; + }; + + idle-states { + CPU_SLEEP_0: cpu-sleep-0 { + compatible =3D"qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us =3D <130>; + exit-latency-us =3D <150>; + min-residency-us =3D <2000>; + local-timer-stop; + }; + }; + }; + + /* + * MSM8939 has a big.LITTLE heterogeneous computing architecture, + * consisting of two clusters of four ARM Cortex-A53s each. The + * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs + * at 1.5-1.7GHz. + * + * The enable method used here is spin-table which presupposes use + * of a 2nd stage boot shim such as lk2nd to have installed a + * spin-table, the downstream non-psci/non-spin-table method that + * default msm8916/msm8936/msm8939 will not be supported upstream. + */ + cpu-map { + /* LITTLE (efficiency) cluster */ + cluster0 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + + /* big (performance) cluster */ + /* Boot CPU is cluster 1 core 0 */ + cluster1 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-msm8916", "qcom,scm"; + clocks =3D <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names =3D "core", "bus", "iface"; + #reset-cells =3D <1>; + + qcom,dload-mode =3D <&tcsr 0x6100>; + }; + }; + + hexagon-smp2p { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + + interrupts =3D ; + + mboxes =3D <&apcs1_mbox 14>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + hexagon_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the reg */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + tz-apps@86000000 { + reg =3D <0x0 0x86000000 0x0 0x300000>; + no-map; + }; + + smem_mem: smem@86300000 { + reg =3D <0x0 0x86300000 0x0 0x100000>; + no-map; + }; + + hypervisor@86400000 { + reg =3D <0x0 0x86400000 0x0 0x100000>; + no-map; + }; + + tz@86500000 { + reg =3D <0x0 0x86500000 0x0 0x180000>; + no-map; + }; + + reserved@86680000 { + reg =3D <0x0 0x86680000 0x0 0x80000>; + no-map; + }; + + rmtfs@86700000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0x86700000 0x0 0xe0000>; + no-map; + + qcom,client-id =3D <1>; + }; + + rfsa@867e0000 { + reg =3D <0x0 0x867e0000 0x0 0x20000>; + no-map; + }; + + mpss_mem: mpss@86800000 { + reg =3D <0x0 0x86800000 0x0 0x5500000>; + no-map; + }; + + wcnss_mem: wcnss@8bd00000 { + reg =3D <0x0 0x8bd00000 0x0 0x600000>; + no-map; + }; + + venus_mem: venus@8c300000 { + reg =3D <0x0 0x8c300000 0x0 0x800000>; + no-map; + }; + + mba_mem: mba@8cb00000 { + no-map; + reg =3D <0x0 0x8cb00000 0x0 0x100000>; + }; + }; + + smem { + compatible =3D "qcom,smem"; + + memory-region =3D <&smem_mem>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + + hwlocks =3D <&tcsr_mutex 3>; + }; + + smsm { + compatible =3D "qcom,smsm"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + qcom,ipc-1 =3D <&apcs1_mbox 8 13>; + qcom,ipc-3 =3D <&apcs1_mbox 8 19>; + + apps_smsm: apps@0 { + reg =3D <0>; + + #qcom,smem-state-cells =3D <1>; + }; + + hexagon_smsm: hexagon@1 { + reg =3D <1>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wcnss_smsm: wcnss@6 { + reg =3D <6>; + interrupts =3D ; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0 0xffffffff>; + + rng@22000 { + compatible =3D "qcom,prng"; + reg =3D <0x00022000 0x200>; + clocks =3D <&gcc GCC_PRNG_AHB_CLK>; + clock-names =3D "core"; + }; + + qfprom: qfprom@5c000 { + compatible =3D "qcom,msm8916-qfprom", "qcom,qfprom"; + reg =3D <0x0005c000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + tsens_caldata: caldata@a0 { + reg =3D <0xa0 0x5c>; + }; + cpr_efuse_init_voltage1: ivoltage1@dc { + reg =3D <0xdc 0x4>; + bits =3D <4 6>; + }; + cpr_efuse_init_voltage2: ivoltage2@da { + reg =3D <0xda 0x4>; + bits =3D <2 6>; + }; + cpr_efuse_init_voltage3: ivoltage3@d8 { + reg =3D <0xd8 0x4>; + bits =3D <0 6>; + }; + cpr_efuse_quot1: quot1@dc { + reg =3D <0xdd 0x8>; + bits =3D <2 12>; + }; + cpr_efuse_quot2: quot2@da { + reg =3D <0xdb 0x8>; + bits =3D <0x0 12>; + }; + cpr_efuse_quot3: quot3@d8 { + reg =3D <0xd8 0x8>; + bits =3D <6 12>; + }; + cpr_efuse_ring1: ring1@de { + reg =3D <0xde 0x4>; + bits =3D <6 3>; + }; + cpr_efuse_ring2: ring2@de { + reg =3D <0xde 0x4>; + bits =3D <6 3>; + }; + cpr_efuse_ring3: ring3@de { + reg =3D <0xde 0x4>; + bits =3D <6 3>; + }; + cpr_efuse_revision: revision@4 { + reg =3D <0x5 0x1>; + bits =3D <5 1>; + }; + cpr_efuse_revision_high: revision-high@4 { + reg =3D <0x7 0x1>; + bits =3D <0 1>; + }; + cpr_efuse_pvs_version: pvs@4 { + reg =3D <0x3 0x1>; + bits =3D <5 1>; + }; + cpr_efuse_pvs_version_high: pvs-high@4 { + reg =3D <0x6 0x1>; + bits =3D <2 2>; + }; + cpr_efuse_speedbin: speedbin@c { + reg =3D <0xc 0x1>; + bits =3D <2 3>; + }; + + }; + + rpm_msg_ram: sram@60000 { + compatible =3D "qcom,rpm-msg-ram"; + reg =3D <0x00060000 0x8000>; + }; + + bimc: interconnect@400000 { + compatible =3D "qcom,msm8939-bimc"; + reg =3D <0x00400000 0x62000>; + clock-names =3D "bus", "bus_a"; + clocks =3D <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + #interconnect-cells =3D <1>; + status =3D "okay"; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,msm8939-tsens", "qcom,tsens-v0_1"; + reg =3D <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells =3D <&tsens_caldata>; + nvmem-cell-names =3D "calib"; + #qcom,sensors =3D <10>; + interrupts =3D ; + interrupt-names =3D "uplow"; + #thermal-sensor-cells =3D <1>; + }; + + restart@4ab000 { + compatible =3D "qcom,pshold"; + reg =3D <0x004ab000 0x4>; + }; + + pcnoc: interconnect@500000 { + compatible =3D "qcom,msm8939-pcnoc"; + reg =3D <0x00500000 0x11000>; + clock-names =3D "bus", "bus_a"; + clocks =3D <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + #interconnect-cells =3D <1>; + status =3D "okay"; + }; + + snoc: interconnect@580000 { + compatible =3D "qcom,msm8939-snoc"; + reg =3D <0x00580000 0x14080>; + clock-names =3D "bus", "bus_a"; + clocks =3D <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + #interconnect-cells =3D <1>; + status =3D "okay"; + + snoc_mm: interconnect-snoc { + compatible =3D "qcom,msm8939-snoc-mm"; + clock-names =3D "bus", "bus_a"; + clocks =3D <&rpmcc RPM_SMD_SYSMMNOC_CLK>, + <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>; + #interconnect-cells =3D <1>; + status =3D "okay"; + }; + + }; + + msmgpio: pinctrl@1000000 { + compatible =3D "qcom,msm8916-pinctrl"; + reg =3D <0x01000000 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&msmgpio 0 0 122>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "blsp_uart1"; + + drive-strength =3D <16>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + blsp1_uart2_default: blsp1-uart2-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "blsp_uart2"; + + drive-strength =3D <16>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep-state { + pins =3D "gpio4", "gpio5"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + camera_front_default: camera-front-default-state { + pwdn-pins { + pins =3D "gpio33"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + }; + rst-pins { + pins =3D "gpio28"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + }; + mclk1-pins { + pins =3D "gpio27"; + function =3D "cam_mclk1"; + + drive-strength =3D <16>; + bias-disable; + }; + }; + + camera_rear_default: camera-rear-default-state { + pwdn-pins { + pins =3D "gpio34"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + }; + rst-pins { + pins =3D "gpio35"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + }; + mclk0-pins { + pins =3D "gpio26"; + function =3D "cam_mclk0"; + + drive-strength =3D <16>; + bias-disable; + }; + }; + + cci0_default: cci0-default-state { + pins =3D "gpio29", "gpio30"; + function =3D "cci_i2c"; + + drive-strength =3D <16>; + bias-disable; + }; + + cdc-pdm-lines-state { + cdc_pdm_lines_act: pdm-lines-on-pins { + pins =3D "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function =3D "cdc_pdm0"; + + drive-strength =3D <8>; + bias-disable; + }; + cdc_pdm_lines_sus: pdm-lines-off-pins { + pins =3D "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function =3D "cdc_pdm0"; + + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cdc_dmic_lines_act: cdc-dmic-lines-on-state { + clk-pins { + pins =3D "gpio0"; + function =3D "dmic0_clk"; + + drive-strength =3D <8>; + }; + data-pins { + pins =3D "gpio1"; + function =3D "dmic0_data"; + + drive-strength =3D <8>; + }; + }; + cdc_dmic_lines_sus: cdc-dmic-lines-off-state { + clk-pins { + pins =3D "gpio0"; + function =3D "dmic0_clk"; + + drive-strength =3D <2>; + bias-disable; + }; + data-pins { + pins =3D "gpio1"; + function =3D "dmic0_data"; + + drive-strength =3D <2>; + bias-disable; + }; + }; + + ext-mclk-tlmm-lines-state { + ext_mclk_tlmm_lines_act: mclk-lines-on-pins { + pins =3D "gpio116"; + function =3D "pri_mi2s"; + + drive-strength =3D <8>; + bias-disable; + }; + ext_mclk_tlmm_lines_sus: mclk-lines-off-pins { + pins =3D "gpio116"; + function =3D "pri_mi2s"; + + drive-strength =3D <2>; + bias-disable; + }; + }; + + ext-pri-tlmm-lines-state { + ext_pri_tlmm_lines_act: ext-pa-on-pins { + pins =3D "gpio113", "gpio114", "gpio115", "gpio116"; + function =3D "pri_mi2s"; + + drive-strength =3D <8>; + bias-disable; + }; + ext_pri_tlmm_lines_sus: ext-pa-off-pins { + pins =3D "gpio113", "gpio114", "gpio115", "gpio116"; + function =3D "pri_mi2s"; + + drive-strength =3D <2>; + bias-disable; + }; + }; + + ext-pri-ws-line-state { + ext_pri_ws_act: ext-pa-on-pins { + pins =3D "gpio110"; + function =3D "pri_mi2s_ws"; + + drive-strength =3D <8>; + bias-disable; + }; + ext_pri_ws_sus: ext-pa-off-pins { + pins =3D "gpio110"; + function =3D "pri_mi2s_ws"; + + drive-strength =3D <2>; + bias-disable; + }; + }; + + /* secondary Mi2S */ + ext-sec-tlmm-lines-state { + ext_sec_tlmm_lines_act: tlmm-lines-on-pins { + pins =3D "gpio112", "gpio117", "gpio118", "gpio119"; + function =3D "sec_mi2s"; + + drive-strength =3D <8>; + bias-disable; + }; + ext_sec_tlmm_lines_sus: tlmm-lines-off-pins { + pins =3D "gpio112", "gpio117", "gpio118", "gpio119"; + function =3D "sec_mi2s"; + + drive-strength =3D <2>; + bias-disable; + }; + }; + + i2c1_default: i2c1-default-state { + pins =3D "gpio2", "gpio3"; + function =3D "blsp_i2c1"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c1_sleep: i2c1-sleep-state { + pins =3D "gpio2", "gpio3"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c2_default: i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "blsp_i2c2"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c2_sleep: i2c2-sleep-state { + pins =3D "gpio6", "gpio7"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c3_default: i2c3-default-state { + pins =3D "gpio10", "gpio11"; + function =3D "blsp_i2c3"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c3_sleep: i2c3-sleep-state { + pins =3D "gpio10", "gpio11"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c4_default: i2c4-default-state { + pins =3D "gpio14", "gpio15"; + function =3D "blsp_i2c4"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c4_sleep: i2c4-sleep-state { + pins =3D "gpio14", "gpio15"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c5_default: i2c5-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "blsp_i2c5"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c5_sleep: i2c5-sleep-state { + pins =3D "gpio18", "gpio19"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c6_default: i2c6-default-state { + pins =3D "gpio22", "gpio23"; + function =3D "blsp_i2c6"; + + drive-strength =3D <2>; + bias-disable; + }; + + i2c6_sleep: i2c6-sleep-state { + pins =3D "gpio22", "gpio23"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + + pmx-sdc1-clk-state { + sdc1_clk_on: clk-on-pins { + pins =3D "sdc1_clk"; + + bias-disable; + drive-strength =3D <16>; + }; + sdc1_clk_off: clk-off-pins { + pins =3D "sdc1_clk"; + + bias-disable; + drive-strength =3D <2>; + }; + }; + + pmx-sdc1-cmd-state { + sdc1_cmd_on: cmd-on-pins { + pins =3D "sdc1_cmd"; + + bias-pull-up; + drive-strength =3D <10>; + }; + sdc1_cmd_off: cmd-off-pins { + pins =3D "sdc1_cmd"; + + bias-pull-up; + drive-strength =3D <2>; + }; + }; + + pmx-sdc1-data-state { + sdc1_data_on: data-on-pins { + pins =3D "sdc1_data"; + + bias-pull-up; + drive-strength =3D <10>; + }; + sdc1_data_off: data-off-pins { + pins =3D "sdc1_data"; + + bias-pull-up; + drive-strength =3D <2>; + }; + }; + + pmx-sdc2-clk-state { + sdc2_clk_on: clk-on-pins { + pins =3D "sdc2_clk"; + + bias-disable; + drive-strength =3D <16>; + }; + sdc2_clk_off: clk-off-pins { + pins =3D "sdc2_clk"; + + bias-disable; + drive-strength =3D <2>; + }; + }; + + pmx-sdc2-cmd-state { + sdc2_cmd_on: cmd-on-pins { + pins =3D "sdc2_cmd"; + + bias-pull-up; + drive-strength =3D <10>; + }; + sdc2_cmd_off: cmd-off-pins { + pins =3D "sdc2_cmd"; + + bias-pull-up; + drive-strength =3D <2>; + }; + }; + + pmx-sdc2-data-state { + sdc2_data_on: data-on-pins { + pins =3D "sdc2_data"; + + bias-pull-up; + drive-strength =3D <10>; + }; + sdc2_data_off: data-off-pins { + pins =3D "sdc2_data"; + + bias-pull-up; + drive-strength =3D <2>; + }; + }; + + pmx-sdc2-cd-pin-state { + sdc2_cd_on: cd-on-pins { + pins =3D "gpio38"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-up; + }; + sdc2_cd_off: cd-off-pins { + pins =3D "gpio38"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-disable; + }; + }; + + spi1_default: spi1-default-state { + spi-pins { + pins =3D "gpio0", "gpio1", "gpio3"; + function =3D "blsp_spi1"; + + drive-strength =3D <12>; + bias-disable; + }; + cs-pins { + pins =3D "gpio2"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + output-high; + }; + }; + + spi1_sleep: spi1-sleep-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + spi2_default: spi2-default-state { + spi-pins { + pins =3D "gpio4", "gpio5", "gpio7"; + function =3D "blsp_spi2"; + + drive-strength =3D <12>; + bias-disable; + }; + cs-pins { + pins =3D "gpio6"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + output-high; + }; + }; + + spi2_sleep: spi2-sleep-state { + pins =3D "gpio4", "gpio5", "gpio6", "gpio7"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + spi3_default: spi3-default-state { + spi-pins { + pins =3D "gpio8", "gpio9", "gpio11"; + function =3D "blsp_spi3"; + + drive-strength =3D <12>; + bias-disable; + }; + cs-pins { + pins =3D "gpio10"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + output-high; + }; + }; + + spi3_sleep: spi3-sleep-state { + pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + spi4_default: spi4-default-state { + spi-pins { + pins =3D "gpio12", "gpio13", "gpio15"; + function =3D "blsp_spi4"; + + drive-strength =3D <12>; + bias-disable; + }; + cs-pins { + pins =3D "gpio14"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + output-high; + }; + }; + + spi4_sleep: spi4-sleep-state { + pins =3D "gpio12", "gpio13", "gpio14", "gpio15"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + spi5_default: spi5-default-state { + spi-pins { + pins =3D "gpio16", "gpio17", "gpio19"; + function =3D "blsp_spi5"; + + drive-strength =3D <12>; + bias-disable; + }; + cs-pins { + pins =3D "gpio18"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + output-high; + }; + }; + + spi5_sleep: spi5-sleep-state { + pins =3D "gpio16", "gpio17", "gpio18", "gpio19"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + spi6_default: spi6-default-state { + spi-pins { + pins =3D "gpio20", "gpio21", "gpio23"; + function =3D "blsp_spi6"; + + drive-strength =3D <12>; + bias-disable; + }; + cs-pins { + pins =3D "gpio22"; + function =3D "gpio"; + + drive-strength =3D <16>; + bias-disable; + output-high; + }; + }; + + spi6_sleep: spi6-sleep-state { + pins =3D "gpio20", "gpio21", "gpio22", "gpio23"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + wcnss_pin_a: wcnss-active-state { + pins =3D "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; + function =3D "wcss_wlan"; + + drive-strength =3D <6>; + bias-pull-up; + }; + }; + + gcc: clock-controller@1800000 { + compatible =3D "qcom,gcc-msm8939"; + reg =3D <0x01800000 0x80000>; + clocks =3D <&xo_board>, + <&sleep_clk>, + <&dsi_phy0 1>, + <&dsi_phy0 0>, + <0>, + <0>, + <0>; + clock-names =3D "xo", + "sleep_clk", + "dsi0pll", + "dsi0pllbyte", + "ext_mclk", + "ext_pri_i2s", + "ext_sec_i2s"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01905000 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1937000 { + compatible =3D "qcom,tcsr-msm8916", "syscon"; + reg =3D <0x01937000 0x30000>; + }; + + mdss: mdss@1a00000 { + compatible =3D "qcom,mdss"; + reg =3D <0x01a00000 0x1000>, + <0x01ac8000 0x3000>; + reg-names =3D "mdss_phys", "vbif_phys"; + + interrupts =3D ; + interrupt-controller; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names =3D "iface", + "bus", + "vsync"; + + power-domains =3D <&gcc MDSS_GDSC>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + #interrupt-cells =3D <1>; + ranges; + + mdp: mdp@1a01000 { + compatible =3D "qcom,mdp5"; + reg =3D <0x01a01000 0x89000>; + reg-names =3D "mdp_phys"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDP_TBU_CLK>, + <&gcc GCC_MDP_RT_TBU_CLK>; + clock-names =3D "iface", + "bus", + "core", + "vsync", + "tbu", + "tbu_rt"; + + iommus =3D <&apps_iommu 4>; + + interconnects =3D <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, + <&pcnoc MASTER_SPDM &snoc SLAVE_IMEM>; + interconnect-names =3D "mdp0-mem", "mdp1-mem", "register-mem"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mdp5_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + mdp5_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi@1a98000 { + compatible =3D "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x01a98000 0x25c>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + assigned-clocks =3D <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&dsi_phy0 0>, + <&dsi_phy0 1>; + + phys =3D <&dsi_phy0>; + status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi_phy0: phy@1a98300 { + compatible =3D "qcom,dsi-phy-28nm-lp"; + reg =3D <0x01a98300 0xd4>, + <0x01a98500 0x280>, + <0x01a98780 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names =3D "iface", "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + dsi1: dsi@1aa0000 { + compatible =3D "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x01aa0000 0x25c>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <5>; + + power-domains =3D <&gcc MDSS_GDSC>; + + clocks =3D <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names =3D "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + assigned-clocks =3D <&gcc BYTE1_CLK_SRC>, + <&gcc PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&dsi_phy1 0>, + <&dsi_phy1 1>; + phys =3D <&dsi_phy1>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi1_in: endpoint { + remote-endpoint =3D <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi_phy1: phy@1aa0300 { + compatible =3D "qcom,dsi-phy-28nm-lp"; + reg =3D <0x01aa0300 0xd4>, + <0x01aa0500 0x280>, + <0x01aa0780 0x30>; + reg-names =3D "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + clocks =3D <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names =3D "iface", "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + }; + + gpu@1c00000 { + compatible =3D "qcom,adreno-405.0", "qcom,adreno"; + reg =3D <0x01c00000 0x10000>; + reg-names =3D "kgsl_3d0_reg_memory"; + interrupts =3D ; + interrupt-names =3D "kgsl_3d0_irq"; + clock-names =3D "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d", + "rbbmtimer"; + clocks =3D <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>, + <&gcc GCC_OXILI_TIMER_CLK>; + power-domains =3D <&gcc OXILI_GDSC>; + operating-points-v2 =3D <&opp_table>; + iommus =3D <&gpu_iommu 1>, <&gpu_iommu 2>; + + opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-550000000 { + opp-hz =3D /bits/ 64 <550000000>; + }; + + opp-465000000 { + opp-hz =3D /bits/ 64 <465000000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + }; + + opp-220000000 { + opp-hz =3D /bits/ 64 <220000000>; + }; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + }; + }; + }; + + apps_iommu: iommu@1ef0000 { + compatible =3D "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + reg =3D <0x01ef0000 0x3000>; + ranges =3D <0 0x1e20000 0x40000>; + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names =3D "iface", "bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + qcom,iommu-secure-id =3D <17>; + + /* mdp_0: */ + iommu-ctx@4000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x4000 0x1000>; + interrupts =3D ; + }; + + /* venus_ns: */ + iommu-ctx@5000 { + compatible =3D "qcom,msm-iommu-v1-sec"; + reg =3D <0x5000 0x1000>; + interrupts =3D ; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible =3D "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges =3D <0 0x1f08000 0x10000>; + clocks =3D <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>, + <&gcc GCC_GFX_TBU_CLK>; + clock-names =3D "iface", "bus", "tbu"; + #address-cells =3D <1>; + #size-cells =3D <1>; + #iommu-cells =3D <1>; + qcom,iommu-secure-id =3D <18>; + + /* gfx3d_user: */ + iommu-ctx@1000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x1000 0x1000>; + interrupts =3D ; + }; + + /* gfx3d_priv: */ + iommu-ctx@2000 { + compatible =3D "qcom,msm-iommu-v1-ns"; + reg =3D <0x2000 0x1000>; + interrupts =3D ; + }; + }; + + spmi_bus: spmi@200f000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0200f000 0x001000>, + <0x02400000 0x400000>, + <0x02c00000 0x400000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names =3D "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names =3D "periph_irq"; + interrupts =3D ; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + mpss: remoteproc@4080000 { + compatible =3D "qcom,msm8916-mss-pil"; + reg =3D <0x04080000 0x100>, + <0x04020000 0x040>; + + reg-names =3D "qdsp6", "rmb"; + + interrupts-extended =3D <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks =3D <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names =3D "iface", "bus", "mem", "xo"; + + power-domains =3D <&rpmpd MSM8939_VDDMDCX>, + <&rpmpd MSM8939_VDDMX>; + power-domain-names =3D "cx", "mx"; + + qcom,smem-states =3D <&hexagon_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + resets =3D <&scm 0>; + reset-names =3D "mss_restart"; + + qcom,halt-regs =3D <&tcsr 0x18000 0x19000 0x1a000>; + + status =3D "disabled"; + + mba { + memory-region =3D <&mba_mem>; + }; + + mpss { + memory-region =3D <&mpss_mem>; + }; + + smd-edge { + interrupts =3D ; + + qcom,smd-edge =3D <0>; + mboxes =3D <&apcs1_mbox 12>; + qcom,remote-pid =3D <1>; + + label =3D "hexagon"; + }; + }; + + sound: sound@7702000 { + compatible =3D "qcom,apq8016-sbc-sndcard"; + reg =3D <0x07702000 0x4>, + <0x07702004 0x4>; + reg-names =3D "mic-iomux", "spkr-iomux"; + status =3D "disabled"; + }; + + lpass: audio-controller@7708000 { + compatible =3D "qcom,apq8016-lpass-cpu"; + reg =3D <0x07708000 0x10000>; + reg-names =3D "lpass-lpaif"; + interrupts =3D ; + interrupt-names =3D "lpass-irq-lpaif"; + clocks =3D <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; + clock-names =3D "ahbix-clk", + "mi2s-bit-clk0", + "mi2s-bit-clk1", + "mi2s-bit-clk2", + "mi2s-bit-clk3", + "pcnoc-mport-clk", + "pcnoc-sway-clk"; + #sound-dai-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + lpass_codec: audio-codec@771c000 { + compatible =3D "qcom,msm8916-wcd-digital-codec"; + reg =3D <0x0771c000 0x400>; + clocks =3D <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names =3D "ahbix-clk", "mclk"; + #sound-dai-cells =3D <1>; + }; + + blsp_dma: dma-controller@7884000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x07884000 0x23000>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + status =3D "disabled"; + }; + + blsp1_uart1: serial@78af000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078af000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 0>, <&blsp_dma 1>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp1_uart1_default>; + pinctrl-1 =3D <&blsp1_uart1_sleep>; + status =3D "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible =3D "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg =3D <0x078b0000 0x200>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 2>, <&blsp_dma 3>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp1_uart2_default>; + pinctrl-1 =3D <&blsp1_uart2_sleep>; + status =3D "disabled"; + }; + + blsp_i2c1: i2c@78b5000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b5000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 4>, <&blsp_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c1_default>; + pinctrl-1 =3D <&i2c1_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c2: i2c@78b6000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b6000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 6>, <&blsp_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c2_default>; + pinctrl-1 =3D <&i2c2_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c3: i2c@78b7000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b7000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 8>, <&blsp_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c3_default>; + pinctrl-1 =3D <&i2c3_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c4: i2c@78b8000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b8000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 10>, <&blsp_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c4_default>; + pinctrl-1 =3D <&i2c4_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c5: i2c@78b9000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078b9000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 12>, <&blsp_dma 13>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c5_default>; + pinctrl-1 =3D <&i2c5_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_i2c6: i2c@78ba000 { + compatible =3D "qcom,i2c-qup-v2.2.1"; + reg =3D <0x078ba000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 14>, <&blsp_dma 15>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c6_default>; + pinctrl-1 =3D <&i2c6_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi1: spi@78b5000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b5000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 4>, <&blsp_dma 5>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi1_default>; + pinctrl-1 =3D <&spi1_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi2: spi@78b6000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b6000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 6>, <&blsp_dma 7>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi2_default>; + pinctrl-1 =3D <&spi2_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi3: spi@78b7000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b7000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 8>, <&blsp_dma 9>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi3_default>; + pinctrl-1 =3D <&spi3_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi4: spi@78b8000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b8000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 10>, <&blsp_dma 11>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi4_default>; + pinctrl-1 =3D <&spi4_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi5: spi@78b9000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078b9000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 12>, <&blsp_dma 13>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi5_default>; + pinctrl-1 =3D <&spi5_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + blsp_spi6: spi@78ba000 { + compatible =3D "qcom,spi-qup-v2.2.1"; + reg =3D <0x078ba000 0x500>; + interrupts =3D ; + clocks =3D <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names =3D "core", "iface"; + dmas =3D <&blsp_dma 14>, <&blsp_dma 15>; + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi6_default>; + pinctrl-1 =3D <&spi6_sleep>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + sdhc_1: mmc@7824000 { + compatible =3D "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07824900 0x11c>, + <0x07824000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , <0 138 IRQ_TYPE_LEVEL= _HIGH>; + interrupt-names =3D "hc_irq", "pwr_irq"; + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; + resets =3D <&gcc GCC_SDCC1_BCR>; + mmc-ddr-1_8v; + bus-width =3D <8>; + non-removable; + status =3D "disabled"; + }; + + sdhc_2: mmc@7864000 { + compatible =3D "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; + reg =3D <0x07864900 0x11c>, + <0x07864000 0x800>; + reg-names =3D "hc", "core"; + + interrupts =3D , <0 221 IRQ_TYPE_LEVEL= _HIGH>; + interrupt-names =3D "hc_irq", "pwr_irq"; + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; + resets =3D <&gcc GCC_SDCC2_BCR>; + bus-width =3D <4>; + status =3D "disabled"; + }; + + usb: usb@78d9000 { + compatible =3D "qcom,ci-hdrc"; + reg =3D <0x078d9000 0x200>, + <0x078d9200 0x200>; + interrupts =3D , + ; + clocks =3D <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names =3D "iface", "core"; + assigned-clocks =3D <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates =3D <80000000>; + resets =3D <&gcc GCC_USB_HS_BCR>; + reset-names =3D "core"; + #reset-cells =3D <1>; + phy_type =3D "ulpi"; + dr_mode =3D "otg"; + ahb-burst-config =3D <0>; + phy-names =3D "usb-phy"; + phys =3D <&usb_hs_phy>; + status =3D "disabled"; + + ulpi { + usb_hs_phy: phy { + compatible =3D "qcom,usb-hs-phy-msm8916", + "qcom,usb-hs-phy"; + clocks =3D <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names =3D "ref", "sleep"; + resets =3D <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; + reset-names =3D "phy", "por"; + #phy-cells =3D <0>; + qcom,init-seq =3D /bits/ 8 <0x0 0x44 + 0x1 0x6b 0x2 0x24 0x3 0x13>; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible =3D "qcom,msm-qgic2"; + reg =3D <0x0b000000 0x1000>, <0x0b002000 0x2000>, + <0x0b001000 0x1000>, <0x0b004000 0x2000>; + interrupt-controller; + #interrupt-cells =3D <3>; + interrupts =3D ; + }; + + apcs1_mbox: mailbox@b011000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b011000 0x1000>; + clocks =3D <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&xo_board>; + clock-names =3D "pll", "aux", "ref"; + #clock-cells =3D <0>; + assigned-clocks =3D <&apcs2>; + assigned-clock-rates =3D <297600000>; + #mbox-cells =3D <1>; + }; + + a53pll_c1: clock@b016000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b016000 0x40>; + #clock-cells =3D <0>; + }; + + acc0: clock-controller@b088000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b088000 0x1000>; + }; + + saw0: power-manager@b089000 { + compatible =3D "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg =3D <0x0b089000 0x1000>; + }; + + acc1: clock-controller@b098000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b098000 0x1000>; + }; + + saw1: power-manager@b099000 { + compatible =3D "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg =3D <0x0b099000 0x1000>; + }; + + acc2: clock-controller@b0a8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b0a8000 0x1000>; + }; + + saw2: power-manager@b0a9000 { + compatible =3D "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg =3D <0x0b0a9000 0x1000>; + }; + + acc3: clock-controller@b0b8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b0b8000 0x1000>; + }; + + saw3: power-manager@b0b9000 { + compatible =3D "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg =3D <0x0b0b9000 0x1000>; + }; + + apcs0_mbox: mailbox@b111000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b111000 0x1000>; + clocks =3D <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&xo_board>; + clock-names =3D "pll", "aux", "ref"; + #clock-cells =3D <0>; + #mbox-cells =3D <1>; + }; + + a53pll_c0: clock@b116000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b116000 0x40>; + #clock-cells =3D <0>; + }; + + acc4: clock-controller@b188000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b188000 0x1000>; + }; + + saw4: power-manager@b189000 { + compatible =3D "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg =3D <0x0b189000 0x1000>; + }; + + acc5: clock-controller@b198000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b198000 0x1000>; + }; + + saw5: power-manager@b199000 { + compatible =3D "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg =3D <0x0b199000 0x1000>; + }; + + acc6: clock-controller@b1a8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b1a8000 0x1000>; + }; + + saw6: power-manager@b1a9000 { + compatible =3D "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg =3D <0x0b1a9000 0x1000>; + }; + + acc7: clock-controller@b1b8000 { + compatible =3D "qcom,kpss-acc-v2"; + reg =3D <0x0b1b8000 0x1000>; + }; + + saw7: power-manager@b1b9000 { + compatible =3D "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; + reg =3D <0x0b1b9000 0x1000>; + }; + + a53pll_cci: clock@b1d0000 { + compatible =3D "qcom,msm8939-a53pll"; + reg =3D <0x0b1d0000 0x40>; + #clock-cells =3D <0>; + }; + + apcs2: mailbox@b1d1000 { + compatible =3D "qcom,msm8939-apcs-kpss-global", "syscon"; + reg =3D <0x0b1d1000 0x1000>; + clocks =3D <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&xo_board>; + clock-names =3D "pll", "aux", "ref"; + #clock-cells =3D <0>; + #mbox-cells =3D <1>; + }; + + timer@b020000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0b020000 0x1000>; + clock-frequency =3D <19200000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + frame@b021000 { + frame-number =3D <0>; + interrupts =3D , + ; + reg =3D <0x0b021000 0x1000>, + <0x0b022000 0x1000>; + }; + + frame@b023000 { + frame-number =3D <1>; + interrupts =3D ; + reg =3D <0x0b023000 0x1000>; + status =3D "disabled"; + }; + + frame@b024000 { + frame-number =3D <2>; + interrupts =3D ; + reg =3D <0x0b024000 0x1000>; + status =3D "disabled"; + }; + + frame@b025000 { + frame-number =3D <3>; + interrupts =3D ; + reg =3D <0x0b025000 0x1000>; + status =3D "disabled"; + }; + + frame@b026000 { + frame-number =3D <4>; + interrupts =3D ; + reg =3D <0x0b026000 0x1000>; + status =3D "disabled"; + }; + + frame@b027000 { + frame-number =3D <5>; + interrupts =3D ; + reg =3D <0x0b027000 0x1000>; + status =3D "disabled"; + }; + + frame@b028000 { + frame-number =3D <6>; + interrupts =3D ; + reg =3D <0x0b028000 0x1000>; + status =3D "disabled"; + }; + }; + + pronto: remoteproc@a204000 { + compatible =3D "qcom,pronto-v2-pil", "qcom,pronto"; + reg =3D <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names =3D "ccu", "dxe", "pmu"; + + interrupts-extended =3D <&intc 0 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", "fatal", "ready", "handover", "stop-ack"; + + memory-region =3D <&wcnss_mem>; + + power-domains =3D <&rpmpd MSM8939_VDDCX>, + <&rpmpd MSM8939_VDDMX_AO>; + power-domain-names =3D "cx", "mx"; + + qcom,smem-states =3D <&wcnss_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wcnss_pin_a>; + + status =3D "disabled"; + + iris { + compatible =3D "qcom,wcn3620"; + + clocks =3D <&rpmcc RPM_SMD_RF_CLK2>; + clock-names =3D "xo"; + }; + + smd-edge { + interrupts =3D ; + + qcom,ipc =3D <&apcs1_mbox 8 17>; + qcom,smd-edge =3D <6>; + qcom,remote-pid =3D <4>; + + label =3D "pronto"; + + wcnss { + compatible =3D "qcom,wcnss"; + qcom,smd-channels =3D "WCNSS_CTRL"; + + qcom,mmio =3D <&pronto>; + + bluetooth { + compatible =3D "qcom,wcnss-bt"; + }; + + wifi { + compatible =3D "qcom,wcnss-wlan"; + + interrupts =3D , + ; + interrupt-names =3D "tx", "rx"; + + qcom,smem-states =3D <&apps_smsm 10>, + <&apps_smsm 9>; + qcom,smem-state-names =3D "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + }; + + smd { + compatible =3D "qcom,smd"; + + rpm { + interrupts =3D ; + qcom,ipc =3D <&apcs1_mbox 8 0>; + qcom,smd-edge =3D <15>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-msm8936"; + qcom,smd-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-msm8936", "qcom,rpmcc"; + #clock-cells =3D <1>; + }; + + rpmpd: power-controller { + compatible =3D "qcom,msm8939-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level =3D <1>; + }; + + rpmpd_opp_svs_krait: opp2 { + opp-level =3D <2>; + }; + + rpmpd_opp_svs_soc: opp3 { + opp-level =3D <3>; + }; + + rpmpd_opp_nom: opp4 { + opp-level =3D <4>; + }; + + rpmpd_opp_turbo: opp5 { + opp-level =3D <5>; + }; + + rpmpd_opp_super_turbo: opp6 { + opp-level =3D <6>; + }; + }; + }; + }; + }; + }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 5>; + + trips { + cpu0_alert: trip0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu0_crit: trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 6>; + + trips { + cpu1_alert: trip0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu1_crit: trip1 { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu1_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 7>; + + trips { + cpu2_alert: trip0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu2_crit: trip1 { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu2_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 8>; + + trips { + cpu3_alert: trip0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu3_crit: trip1 { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu3_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4567-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 9>; + + trips { + cpu4567_alert: trip0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + cpu4567_crit: trip1 { + temperature =3D <110000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu4567_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 3>; + + trips { + gpu_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + gpu_crit: gpu_crit { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 0>; + + trips { + modem1_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 2>; + + trips { + modem2_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + + camera-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + + thermal-sensors =3D <&tsens 1>; + + trips { + cam_alert0: trip-point0 { + temperature =3D <75000>; + hysteresis =3D <2000>; + type =3D "hot"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + vreg_dummy: regulator-dummy { + #power-domain-cells =3D <0>; + }; + + wcnss-smp2p { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <451>, <431>; + + interrupts =3D ; + + mboxes =3D <&apcs1_mbox 18>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + + #qcom,smem-state-cells =3D <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; +}; --=20 2.34.1 From nobody Sat Feb 7 02:58:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40316C3DA7A for ; Tue, 3 Jan 2023 01:10:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236643AbjACBKE (ORCPT ); Mon, 2 Jan 2023 20:10:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236473AbjACBJU (ORCPT ); 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[2001:1c06:2302:5600:b443:9db7:1e5c:4fd5]) by smtp.gmail.com with ESMTPSA id q26-20020a17090676da00b008302732f569sm13564648ejn.78.2023.01.02.17.09.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 17:09:14 -0800 (PST) From: Bryan O'Donoghue To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, djakov@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: bryan.odonoghue@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benl@squareup.com, shawn.guo@linaro.org, fabien.parent@linaro.org, leo.yan@linaro.org, dmitry.baryshkov@linaro.org, Stephan Gerhold Subject: [PATCH v2 5/7] arm64: dts: qcom: Add msm8939-pm8916.dtsi include Date: Tue, 3 Jan 2023 01:09:02 +0000 Message-Id: <20230103010904.3201835-6-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> References: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Stephan Gerhold The msm8939-pm8916.dtsi include configures the regulator supplies of MSM8939 used together with PM8916, as recommended by Qualcomm. In rare cases where boards deviate from the recommended design they can just avoid using this include. Signed-off-by: Stephan Gerhold Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 82 ++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot= /dts/qcom/msm8939-pm8916.dtsi new file mode 100644 index 0000000000000..18a1b3cca01d6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8939.dtsi" +#include "pm8916.dtsi" + +&dsi0 { + vdda-supply =3D <&pm8916_l2>; + vddio-supply =3D <&pm8916_l6>; +}; + +&dsi1 { + vdda-supply =3D <&pm8916_l2>; + vddio-supply =3D <&pm8916_l6>; +}; + +&dsi_phy0 { + vddio-supply =3D <&pm8916_l6>; +}; + +&dsi_phy1 { + vddio-supply =3D <&pm8916_l6>; +}; + +&mpss { + pll-supply =3D <&pm8916_l7>; +}; + +&pronto { + vddpx-supply =3D <&pm8916_l7>; + + iris { + vddxo-supply =3D <&pm8916_l7>; + vddrfa-supply =3D <&pm8916_s3>; + vddpa-supply =3D <&pm8916_l9>; + vdddig-supply =3D <&pm8916_l5>; + }; +}; + +&sdhc_1 { + vmmc-supply =3D <&pm8916_l8>; + vqmmc-supply =3D <&pm8916_l5>; +}; + +&sdhc_2 { + vmmc-supply =3D <&pm8916_l11>; + vqmmc-supply =3D <&pm8916_l12>; +}; + +&usb_hs_phy { + v1p8-supply =3D <&pm8916_l7>; + v3p3-supply =3D <&pm8916_l13>; +}; + +&rpm_requests { + smd_rpm_regulators: regulators { + compatible =3D "qcom,rpm-pm8916-regulators"; + + /* pm8916_s1 is managed by rpmpd (MSM8939_VDDMDCX) */ + /* pm8916_s2 is managed by rpmpd (MSM8939_VDDCX) */ + pm8916_s3: s3 {}; + pm8916_s4: s4 {}; + + pm8916_l1: l1 {}; + pm8916_l2: l2 {}; + /* pm8916_l3 is managed by rpmpd (MSM8939_VDDMX) */ + pm8916_l4: l4 {}; + pm8916_l5: l5 {}; + pm8916_l6: l6 {}; + pm8916_l7: l7 {}; + pm8916_l8: l8 {}; + pm8916_l9: l9 {}; + pm8916_l10: l10 {}; + pm8916_l11: l11 {}; + pm8916_l12: l12 {}; + pm8916_l13: l13 {}; + pm8916_l14: l14 {}; + pm8916_l15: l15 {}; + pm8916_l16: l16 {}; + pm8916_l17: l17 {}; + pm8916_l18: l18 {}; + }; +}; --=20 2.34.1 From nobody Sat Feb 7 02:58:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EFB0C53210 for ; Tue, 3 Jan 2023 01:10:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236726AbjACBK3 (ORCPT ); Mon, 2 Jan 2023 20:10:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236499AbjACBJY (ORCPT ); Mon, 2 Jan 2023 20:09:24 -0500 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5801959F for ; Mon, 2 Jan 2023 17:09:17 -0800 (PST) Received: by mail-ed1-x535.google.com with SMTP id s5so41887625edc.12 for ; Mon, 02 Jan 2023 17:09:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mmNEjkcHpLgPp1FCBr7Fg0WylwllqOSo93TuymTmm9M=; b=AhCniROSwx7x00gJxTu3i07ZCheMippqaXsnVG7jA4Y8Z2prXu/2jyGQqq8u/FGYlX XlMVHnjOVe/Ho4Njw61ZDzS7b4zkhslHI83qm2NTV7NpeimBSxmTmUtFrUNQvSPjlV2i cVieRdC5bKunBJJog6q6MxYYS/b7EflTUWdiF47wtBzHZTV22KupJar7zSdV8xnQn+vw JUkDA3vL773WHim+KfXtg10Hs0wHyFfspiyOblbTC40W3/Omn6A0CTwx+TkaKrz6D9Sv MRmzyvC8oxeYbq6JFYS+erIB0GWerRP6rnOEirWTft/KlzjUQgW3UEVYNchBqSeFcJSj zFOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mmNEjkcHpLgPp1FCBr7Fg0WylwllqOSo93TuymTmm9M=; b=NnTXKtVFoHbfm2vMTmM1luMgt8FjCjxvS5cHpSqUdvZEp2PAsMNkXzmrDEN+TfZ+Kp wudoKWQukW9dp4qc84wbDea+3UbEAGjkRUJM6LjrpauB8LZdYP11MZ+lO4Z9/7dgjiN4 9odmrlDA3ICgjJzc6kKYa+3JPyRZS8O6RtruVlAHw0gTQNBxgLtoXYpO017mGOb/IrpN KuFK/08Ula7WJ2z6CL014icpb8EFoQg27QjEOXmPYsXK96NX9GCUJPlKkbzxlVW1uGiz vDkKp0pet2OkY4kq/KpuM1S83SqY8f+oQl6/efqJVavaSuJhWHGHvbfajLScRvxojsRf gYCA== X-Gm-Message-State: AFqh2krB4neeQ8BkLm7hee9omt4zAUnOdFFRvYPQcUAYE1AJeNuX8Ryl ezh3lvWUQ7dsHB7fBPbc2uuWkQ== X-Google-Smtp-Source: AMrXdXsTiFP8Dx8IZgRvnksMLMCD9wV3Y4uYNGn1PGibJiTuM2gYoP5Dr3Zf7mS0yn7DNIsezHwX2A== X-Received: by 2002:a05:6402:528f:b0:47e:eaae:9a69 with SMTP id en15-20020a056402528f00b0047eeaae9a69mr36369715edb.41.1672708156174; Mon, 02 Jan 2023 17:09:16 -0800 (PST) Received: from planet9.chello.ie (2001-1c06-2302-5600-b443-9db7-1e5c-4fd5.cable.dynamic.v6.ziggo.nl. [2001:1c06:2302:5600:b443:9db7:1e5c:4fd5]) by smtp.gmail.com with ESMTPSA id q26-20020a17090676da00b008302732f569sm13564648ejn.78.2023.01.02.17.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 17:09:15 -0800 (PST) From: Bryan O'Donoghue To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, djakov@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: bryan.odonoghue@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benl@squareup.com, shawn.guo@linaro.org, fabien.parent@linaro.org, leo.yan@linaro.org, dmitry.baryshkov@linaro.org, Jun Nie , James Willcox , Joseph Gates , Max Chen , Zac Crosby Subject: [PATCH v2 6/7] arm64: dts: qcom: Add Square apq8039-t2 board Date: Tue, 3 Jan 2023 01:09:03 +0000 Message-Id: <20230103010904.3201835-7-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> References: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The apq8039-t2 is an apq8039 based board paired with a wcn3680b WiFi chipset. Co-developed-by: Shawn Guo Signed-off-by: Shawn Guo Co-developed-by: Jun Nie Signed-off-by: Jun Nie Co-developed-by: Benjamin Li Signed-off-by: Benjamin Li Co-developed-by: James Willcox Signed-off-by: James Willcox Co-developed-by: Leo Yan Signed-off-by: Leo Yan Co-developed-by: Joseph Gates Signed-off-by: Joseph Gates Co-developed-by: Max Chen Signed-off-by: Max Chen Co-developed-by: Zac Crosby Signed-off-by: Zac Crosby Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/apq8039-t2.dts | 557 ++++++++++++++++++++++++ 2 files changed, 558 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/apq8039-t2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 3e79496292e7a..8d8dab62c66df 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_QCOM) +=3D apq8016-sbc.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D apq8096-ifc6640.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/= qcom/apq8039-t2.dts new file mode 100644 index 0000000000000..04a2fdd1b1194 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2023, Linaro Ltd. + * + */ + +/dts-v1/; + +#include "msm8939.dtsi" +#include "msm8939-pm8916.dtsi" +#include +#include +#include + +/ { + model =3D "Square, Inc. T2 Devkit"; + compatible =3D "square,apq8039-t2", "qcom,msm8939"; + qcom,board-id =3D <0x53 0x54>; + + aliases { + serial0 =3D &blsp1_uart1; + serial1 =3D &blsp1_uart2; + }; + + bl: backlight { + compatible =3D "gpio-backlight"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_backlight>; + gpios =3D <&msmgpio 98 GPIO_ACTIVE_HIGH>; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + lcd_iovcc_reg: lcd-iovcc-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "lcd_iovcc"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd_iovcc_reg>; + gpio =3D <&msmgpio 9 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <300>; + enable-active-high; + }; + + lcd_avdd_reg: lcd-avdd-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "lcd_avdd"; + regulator-min-microvolt =3D <5600000>; + regulator-max-microvolt =3D <5600000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd_avdd_reg>; + gpio =3D <&msmgpio 86 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <300>; + enable-active-high; + }; + + lcd_avee_reg: lcd-avee-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "lcd_avee"; + regulator-min-microvolt =3D <5600000>; + regulator-max-microvolt =3D <5600000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lcd_avee_reg>; + gpio =3D <&msmgpio 87 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <300>; + enable-active-high; + }; + + pp_spe_3v3_reg: pp-spe-3v3-regulator { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&msmgpio_spe_reg>; + regulator-name =3D "pp_spe_3v3"; + gpio =3D <&msmgpio 108 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <0>; + enable-active-high; + }; + + pp_crq_3v3_reg: pp-crq-3v3-regulator { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&msmgpio_crq_reg>; + regulator-name =3D "pp_crq_3v3"; + gpio =3D <&msmgpio 12 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <0>; + enable-active-high; + }; +}; + +&blsp_dma { + status =3D "okay"; +}; + +&blsp_i2c1 { + status =3D "okay"; +}; + +&blsp_i2c2 { + status =3D "okay"; +}; + +&blsp_i2c3 { + status =3D "okay"; + tps6598x: tps6598x@38 { + compatible =3D "ti,tps6598x"; + reg =3D <0x38>; + + interrupt-parent =3D <&msmgpio>; + interrupts =3D <107 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&typec_irq>; + + typec_con: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + port { + typec_ep: endpoint { + remote-endpoint =3D <&otg_ep>; + }; + }; + }; + }; +}; + +&blsp_i2c5 { + status =3D "okay"; +}; + +&blsp1_uart1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp1_uart1_default>; + pinctrl-1 =3D <&blsp1_uart1_sleep>; + status =3D "okay"; +}; + +&blsp1_uart2 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&blsp1_uart2_default>; + pinctrl-1 =3D <&blsp1_uart2_sleep>; + status =3D "okay"; +}; + +&lpass { + status =3D "okay"; +}; + +/* + * Line names are taken from the schematic of T2, Ver X03. + * July 14, 2018. Page 4 in particular. + */ + +&msmgpio { + gpio-line-names =3D + "APQ_UART1_TX", /* GPIO_0 */ + "APQ_UART1_RX", + "APQ_I2C1_SDA", + "APQ_I2C1_SCL", + "APQ_UART2_TX_1V8", + "APQ_UART2_RX_1V8", + "APQ_I2C2_SDA", + "APQ_I2C2_SCL", + "NC", + "APQ_LCD_IOVCC_EN", + "APQ_I2C3_SDA", /* GPIO_10 */ + "APQ_I2C3_SCL", + "TOUCH_RST_1V8_L", + "NC", + "APQ_I2C4_SDA", + "APQ_I2C4_SCL", + "APQ_ID5", + "USB_DISCONNECT", + "APQ_I2C5_SDA", + "APQ_I2C5_SCL", + "APQ_USBC_SPI_MOSI", /* GPIO_20 */ + "APQ_USBC_SPI_MISO", + "APQ_USBC_SPI_SS_L", + "APQ_USBC_SPI_CLK", + "APQ_LCD_TE0", + "APQ_LCD_RST_L", + "NC", + "NC", + "ACCELEROMETER_INT1", + "APQ_CAM_I2C0_SDA", + "APQ_CAM_I2C0_SCL", /* GPIO_30 */ + "ACCELEROMETER_INT2", + "NC", + "NC", + "NC", + "APQ_K21_RST_1V8_L", + "NC", + "APQ_EDL_1V8", + "TP145", + "BT_SSBI", + "NC", /* GPIO_40 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "BT_CTRL", + "BT_DAT", + "PWR_GPIO_IN", + "PWR_GPIO_OUT", /* GPIO_50 */ + "CARD_DET_MLB_L", + "HALL_SENSOR", + "TP63", + "TP64", + "TP65", + "NC", + "NC", + "NC", + "NC", + "NC", /* GPIO_60 */ + "NC", + "APQ_K21_GPIO0_1V8", + "CDC_PDM_CLK", + "CDC_PDM_SYNC", + "CDC_PDM_TX", + "CDC_PDM_RX0", + "CDC_PDM_RX1", + "CDC_PDM_RX2", + "APQ_K21_GPIO1_1V8", + "NC", /* GPIO_70 */ + "APQ_HUB_SEL_1V8", + "APQ_K21_GPIO2_1V8", + "APQ_K21_GPIO3_1V8", + "APQ_ID0", + "APQ_ID1", + "APQ_ID2", + "APQ_ID3", + "APQ_ID4", + "APQ_HUB_SUSP_IND", + "BOOT_CONFIG_0", /* GPIO_80 */ + "BOOT_CONFIG_1", + "BOOT_CONFIG_2", + "BOOT_CONFIG_3", + "NC", + "NC", + "APQ_LCD_AVDD_EN", + "APQ_LCD_AVEE_EN", + "TP70", + "NC", + "APQ_DEBUG0", /* GPIO_90 */ + "APQ_DEBUG1", + "APQ_DEBUG2", + "APQ_DEBUG3", + "TP165", + "NC", + "APQ_LNA_PWR_EN", + "NC", + "APQ_LCD_BL_EN", + "NC", + "APQ_LCD_ID0", /* GPIO_100 */ + "APQ_LCD_ID1", + "USBC_GPIO5_1V8", + "NC", + "NC", + "NC", + "APQ_HUB_RST_1V8_L", + "USBC_I2C_IRQ_1V8_L", + "SPE_PWR_EN", + "NC", + "APQ_USB_ID", /* GPIO_110 */ + "APQ_EXT_BUCK_VSEL", + "APQ_USB_ID_OUT", + "NC", + "PRNT_RST_L", + "APQ_CRQ_I2C_RDY_1V8", + "TYPEC_RST_1V8_H", + "CHG_BACKPWR_EN", + "CHG_PROCHOT_L", + "NC", + "USBC_GPIO7_1V8", /* GPIO_120 */ + "NC"; + + blsp1_uart1_default: blsp1-uart1-default-state { + pins =3D "gpio0", "gpio1"; + function =3D "blsp_uart1"; + + drive-strength =3D <16>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep-state { + pins =3D "gpio0", "gpio1"; + function =3D "gpio"; + + drive-strength =3D <2>; + bias-pull-down; + }; + + pinctrl_lcd_iovcc_reg: lcd-iovcc-reg-state { + pins =3D "gpio9"; + function =3D "gpio"; + }; + + pinctrl_lcd_avdd_reg: lcd-avdd-reg-state { + pins =3D "gpio86"; + function =3D "gpio"; + }; + + pinctrl_lcd_avee_reg: lcd-avee-reg-state { + pins =3D "gpio87"; + function =3D "gpio"; + }; + + pinctrl_backlight: backlight-state { + pins =3D "gpio98"; + function =3D "gpio"; + }; + + pinctrl_lcd_rst: lcd-rst-state { + pins =3D "gpio25"; + function =3D "gpio"; + }; + + msmgpio_spe_reg: msmgpio-spe-reg-state { + pins =3D "gpio108"; + function =3D "gpio"; + output-high; + }; + + sq_spe_enable: sq-spe-enable-state { + pins =3D "gpio35"; + function =3D "gpio"; + output-low; + }; + + msmgpio_crq_reg: msmgpio-crq-reg-state { + function =3D "gpio"; + pins =3D "gpio12"; + output-high; + }; + + typec_irq: typec-irq-state { + function =3D "gpio"; + pins =3D "gpio107"; + bias-pull-up; + input-enable; + }; + + pinctrl_otg_default: otg-default-state { + function =3D "gpio"; + pins =3D "gpio17"; + output-high; + }; + + pinctrl_otg_host: otg-host-state { + function =3D "gpio"; + pins =3D "gpio17"; + output-low; + }; + + pinctrl_otg_device: otg-device-state { + function =3D "gpio"; + pins =3D "gpio17"; + output-low; + }; + + ext_buck_vsel_reg: ext-buck-vsel-reg-state { + function =3D "gpio"; + pins =3D "gpio111"; + drive-strength =3D <2>; + }; +}; + +&pm8916_gpios { + gpio-line-names =3D + "PM_GPIO1", /* WIFI_GPIO1_PRE */ + "PM_GPIO2", /* WIFI_GPIO2_PRE */ + "PM_GPIO3", + "PM_GPIO4"; +}; + +&pronto { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wcnss_pin_a>; + status =3D "okay"; + + iris { + compatible =3D "qcom,wcn3680"; + }; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply =3D <&pm8916_s3>; + vdd_l4_l5_l6-supply =3D <&pm8916_s4>; + vdd_l7-supply =3D <&pm8916_s4>; + + pm8916_s3: s3 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + }; + + pm8916_s4: s4 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2100000>; + }; + + /* l1 is fixed to 1225000, but not connected in schematic */ + + pm8916_l2: l2 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + pm8916_l4: l4 { + regulator-min-microvolt =3D <2050000>; + regulator-max-microvolt =3D <2050000>; + }; + + pm8916_l5: l5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8916_l6: l6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8916_l7: l7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8916_l8: l8 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8916_l10: l10 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8916_l11: l11 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8916_l12: l12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt =3D <3075000>; + regulator-max-microvolt =3D <3075000>; + }; + + pm8916_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8916_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8916_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2850000>; + }; + + pm8916_l18: l18 { + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2700000>; + }; +}; + +&sdhc_1 { + vmmc-supply =3D <&pm8916_l8>; + vqmmc-supply =3D <&pm8916_l5>; + + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 =3D <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + status =3D "okay"; +}; + +&sound { + status =3D "okay"; + pinctrl-0 =3D <&cdc_pdm_lines_act>; + pinctrl-1 =3D <&cdc_pdm_lines_sus>; + pinctrl-names =3D "default", "sleep"; + model =3D "apq8039-square-sndcard"; + audio-routing =3D "AMIC2", "MIC BIAS Internal2"; + + internal-codec-playback-dai-link { + link-name =3D "WCD"; + cpu { + sound-dai =3D <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai =3D <&lpass_codec 0>, <&wcd_codec 0>; + }; + }; + + internal-codec-capture-dai-link { + link-name =3D "WCD-Capture"; + cpu { + sound-dai =3D <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai =3D <&lpass_codec 1>, <&wcd_codec 1>; + }; + }; +}; + +&usb { + status =3D "okay"; + usb-role-switch; + + pinctrl-names =3D "default", "host", "device"; + pinctrl-0 =3D <&pinctrl_otg_default>; + pinctrl-1 =3D <&pinctrl_otg_host>; + pinctrl-2 =3D <&pinctrl_otg_device>; + pin-switch-delay-us =3D <100000>; + + ulpi { + usb_hs_phy: phy { + v1p8-supply =3D <&pm8916_l7>; + v3p3-supply =3D <&pm8916_l13>; + }; + }; + port { + otg_ep: endpoint { + remote-endpoint =3D <&typec_ep>; + }; + }; +}; + +&wcd_codec { + status =3D "okay"; + qcom,hphl-jack-type-normally-open; + qcom,mbhc-vthreshold-low =3D <75 150 237 450 500>; + qcom,mbhc-vthreshold-high =3D <75 150 237 450 500>; +}; --=20 2.34.1 From nobody Sat Feb 7 02:58:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B847C3DA7A for ; Tue, 3 Jan 2023 01:10:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231169AbjACBKI (ORCPT ); Mon, 2 Jan 2023 20:10:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236491AbjACBJY (ORCPT ); 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[2001:1c06:2302:5600:b443:9db7:1e5c:4fd5]) by smtp.gmail.com with ESMTPSA id q26-20020a17090676da00b008302732f569sm13564648ejn.78.2023.01.02.17.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 17:09:16 -0800 (PST) From: Bryan O'Donoghue To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, djakov@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: bryan.odonoghue@linaro.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, benl@squareup.com, shawn.guo@linaro.org, fabien.parent@linaro.org, leo.yan@linaro.org, dmitry.baryshkov@linaro.org Subject: [PATCH v2 7/7] arm64: dts: qcom: Add msm8939 Sony Xperia M4 Aqua Date: Tue, 3 Jan 2023 01:09:04 +0000 Message-Id: <20230103010904.3201835-8-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> References: <20230103010904.3201835-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a basic booting DTS for the Sony Xperia M4 Aqua aka "tulip". Tulip is paired with: - wcn3660 - smb1360 battery charger - 720p Truly NT35521 Panel Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/msm8939-sony-xperia-kanuti-tulip.dts | 472 ++++++++++++++++++ 2 files changed, 473 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tul= ip.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 8d8dab62c66df..7056036351df8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-samsung-grandmax.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8956-sony-xperia-loire-kugo.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8956-sony-xperia-loire-suzu.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8992-lg-bullhead-rev-10.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts = b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts new file mode 100644 index 0000000000000..ff93b69bda679 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Bryan O'Donoghue. + * + */ + +/dts-v1/; + +#include "msm8939.dtsi" +#include "msm8939-pm8916.dtsi" +#include +#include + +/ { + model =3D "Sony Xperia M4 Aqua"; + compatible =3D "sony,kanuti-tulip", "qcom,msm8939"; + qcom,board-id =3D <8 0>; + + aliases { + serial0 =3D &blsp1_uart2; + mmc0 =3D &sdhc_1; /* SDC1 eMMC slot */ + mmc1 =3D &sdhc_2; /* SDC2 SD card slot */ + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + negative5_reg: negative5-regulator { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&negative5_reg_default>; + regulator-name =3D "negative5_reg"; + gpio =3D <&msmgpio 17 GPIO_ACTIVE_LOW>; + startup-delay-us =3D <0>; + }; + + positive5_reg: positive5-regulator { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&positive5_reg_default>; + regulator-name =3D "positive5_reg"; + gpio =3D <&msmgpio 114 GPIO_ACTIVE_LOW>; + startup-delay-us =3D <0>; + }; + + usb_id: usb-id { + compatible =3D "linux,extcon-usb-gpio"; + id-gpio =3D <&msmgpio 110 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_id_default>; + }; +}; + +&blsp_dma { + status =3D "okay"; +}; + +&dsi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + vdda-supply =3D <&pm8916_l2>; + vddio-supply =3D <&pm8916_l16>; + status =3D "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint =3D <&panel_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; + + panel@0 { + compatible =3D "sony,tulip-truly-nt35521"; + reg =3D <0>; + positive5-supply =3D <&positive5_reg>; + negative5-supply =3D <&negative5_reg>; + reset-gpios =3D <&msmgpio 25 GPIO_ACTIVE_LOW>; + enable-gpios =3D <&msmgpio 10 GPIO_ACTIVE_LOW>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + panel_in: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + }; + + }; +}; + +&dsi_phy0 { + vddio-supply =3D <&pm8916_l16>; + status =3D "okay"; +}; + +&msmgpio { + + ak8963_default: ak8963-default-state { + pins =3D "gpio69"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + ak8963_sleep: ak8963-sleep-state { + pins =3D "gpio69"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + /* Ambient light and proximity sensor apds9930 and apds9900 */ + apds99xx_default: apds99xx-default-state { + pins =3D "gpio113"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + apds99xx_sleep: apds99xx-sleep-state { + pins =3D "gpio113"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cam_sensor_flash_default: cam-sensor-flash-default-state { + pins =3D "gpio98", "gpio97"; + function =3D "gpio"; + bias-disable; + drive-strength =3D <2>; + }; + + cci1_default: cci1-default-state { + pins =3D "gpio31", "gpio32"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-disable; + }; + + cdc_ext_spk_pa_active: cdc-ext-spk-pa-on-state { + pins =3D "gpio0"; + function =3D "gpio"; + drive-strength =3D <8>; + output-low; + }; + + cdc_ext_spk_pa_sus: cdc-ext-spk-pa-off-state { + pins =3D "gpio0"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cdc_slim_lines_act: lines-on-state { + pins =3D "gpio63"; + function =3D "cdc_pdm0"; + drive-strength =3D <8>; + output-high; + }; + + cdc_slim_lines_sus: lines-off-state { + pins =3D "gpio63"; + function =3D "cdc_pdm0"; + drive-strength =3D <2>; + bias-disable; + }; + + cross_conn_det_act: lines-on-state { + pins =3D "gpio120"; + function =3D "gpio"; + drive-strength =3D <8>; + output-low; + bias-pull-down; + }; + + cross_conn_det_sus: lines-off-state { + pins =3D "gpio120"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + ext_buck_vsel: vsel0-state { + pins =3D "gpio111"; + function =3D "gpio"; + drive-strength =3D <2>; + }; + + ext_cdc_tlmm_lines_act: tlmm-lines-on-state { + pins =3D "gpio116", "gpio112", "gpio117", "gpio118", "gpio119"; + function =3D "gpio"; + drive-strength =3D <8>; + }; + + ext_cdc_tlmm_lines_sus: tlmm-lines-off-state { + pins =3D "gpio116", "gpio112", "gpio117", "gpio118", "gpio119"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + gpio_key_suspend: gpio-key-suspend-state { + pins =3D "gpio107", "gpio108", "gpio109"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + negative5_reg_default: negative5-reg-default-state { + pins =3D "gpio17"; + function =3D "gpio"; + output-low; + }; + + positive5_reg_default: positive5-reg-default-state { + pins =3D "gpio114"; + function =3D "gpio"; + output-low; + }; + + /* Gyroscope and accelerometer sensor combo */ + mpu6050_default: mpu6050-default-state { + pins =3D "gpio115"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + mpu6050_sleep: mpu6050-sleep-state { + pins =3D "gpio115"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + nfc_disable_active: nfc-disable-active-state { + pins =3D "gpio20"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + nfc_disable_suspend: nfc-disable-suspend-state { + pins =3D "gpio20"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-disable; + }; + + nfc_int_active: nfc-int-active-state { + pins =3D "gpio21"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + nfc_int_suspend: nfc-int-suspend-state { + pins =3D "gpio21"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-up; + }; + + nt35521_te_default: nt35521-te-default-state { + pins =3D "gpio24"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-down; + }; + + nt35521_backlight: nt35521-backlight-default-state { + pins =3D "gpio10"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-down; + }; + + smb_int: smb-int-default-state { + pins =3D "gpio62"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + /* add pingrp for touchscreen */ + ts_int_active: ts-int-active-state { + pins =3D "gpio13"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ts_int_suspend: ts-int-suspend-state { + pins =3D "gpio13"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + ts_reset_active: ts-reset-active-state { + pins =3D "gpio12"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ts_reset_suspend: ts-reset-suspend-state { + pins =3D "gpio12"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + ts_release: ts-release-default-state { + pins =3D "gpio13", "gpio12"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + usb_id_default: usb-id-default-state { + pins =3D "gpio110"; + function =3D "gpio"; + + drive-strength =3D <8>; + bias-pull-up; + }; +}; + +&pronto { + status =3D "okay"; + iris { + compatible =3D "qcom,wcn3660"; + }; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply =3D <&pm8916_s3>; + vdd_l4_l5_l6-supply =3D <&pm8916_s4>; + vdd_l7-supply =3D <&pm8916_s4>; + + pm8916_s3: s3 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + }; + + pm8916_s4: s4 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2100000>; + }; + + pm8916_l2: l2 { + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + }; + + pm8916_l4: l4 { + regulator-min-microvolt =3D <2050000>; + regulator-max-microvolt =3D <2050000>; + }; + + pm8916_l5: l5 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8916_l6: l6 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + }; + + pm8916_l7: l7 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm8916_l8: l8 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8916_l10: l10 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8916_l11: l11 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8916_l12: l12 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2950000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt =3D <3075000>; + regulator-max-microvolt =3D <3075000>; + }; + + pm8916_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8916_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8916_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt =3D <2850000>; + regulator-max-microvolt =3D <2850000>; + }; + + pm8916_l18: l18 { + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2700000>; + }; +}; + +&sdhc_1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 =3D <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + status =3D "okay"; +}; + +&sdhc_2 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 =3D <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + cd-gpios =3D <&msmgpio 38 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&usb { + status =3D "okay"; + extcon =3D <&usb_id>, <&usb_id>; + + ulpi { + usb_hs_phy: phy { + v1p8-supply =3D <&pm8916_l7>; + v3p3-supply =3D <&pm8916_l13>; + }; + }; +}; + +&usb_hs_phy { + extcon =3D <&usb_id>; +}; --=20 2.34.1