From nobody Tue Sep 16 01:13:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01B73C678D7 for ; Mon, 9 Jan 2023 10:16:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236449AbjAIKQ2 (ORCPT ); Mon, 9 Jan 2023 05:16:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230005AbjAIKPt (ORCPT ); Mon, 9 Jan 2023 05:15:49 -0500 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1E5F1868A for ; Mon, 9 Jan 2023 02:15:23 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id g10so5884297wmo.1 for ; Mon, 09 Jan 2023 02:15:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ED7fYuzAB7f5fc2VJPjwBawtAk4y6MtSvcIIzbfF72M=; b=kPYXWX+xudX2E0Xv91YZXlYwgltLNyURmxLuYkmocyIaB1+Soqs/XCTHQTaobDacfw G2E8xXtvVTMkm3191d74/rrY5HARVJvByfxmmXBA6PNojywxasa2JDDB0+xVelXgrxpf 4Wstr8pbT9M5zZTfEl3RaCG/VdvFoPTYzTCk7DJotNzJ1hZu5Wo+CccEz4wgMOEFgemn 2WVqWus2QBhPFBQq92lEMTMhmzajCZ1OSnGVpAOZp6n+X/D3IZD40g7tVqamreDaYeSB SWAOURhwqVt5HQ7vZ5/BQSm+G+EUDh3MalBFAKOgK9BMoMbtC3JQJpFXWlIqB5UqlT2U utKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ED7fYuzAB7f5fc2VJPjwBawtAk4y6MtSvcIIzbfF72M=; b=SiJeMsWVEcO+aQtk3BX9zcONyZd1KCsIfl9fUH/ZP+GVx46iRYvDt9Et7QELtXzqx6 5fiHooeEBLNbt9FW7TzsQrF93RQjBhkRgki0rjuDDrmXkc7B/Wk/JxdXHOKzaZ+2QDmK BhYWTm2K4H1yDhCsw1gtUE1jG8za2JrtJGbJ5yFRst1Cu2vtv/AWVWGpBwMRkkf5c1G3 mJPcw3gyWKaFWTHpniwC2iU/qGDum5i/oyzmR158LQOd+p40x4PfPUG2j1BA7EPGiEQ1 exLkRuC5SnHvr3kWECmQjKxNYp4RQAaUwMW5CeLTKaJRgB8ieVQSJ/oj1jigOC9WXxOm 1YbQ== X-Gm-Message-State: AFqh2kqSF1bNfuUEA8nbzDbuRpC3x2YllQZCrR8wVbg+JHoklBi9K1Eh RKgA5W2E0eWdhOrhPdUCgAWMKg== X-Google-Smtp-Source: AMrXdXsR8ooi+sQn7m8YAPss+LI9GO3rYcVfny7y77mEFwYiQZIUflbvZwITRfndQkLICMPntESAtQ== X-Received: by 2002:a05:600c:4f83:b0:3d2:3f55:f73f with SMTP id n3-20020a05600c4f8300b003d23f55f73fmr46215333wmq.8.1673259322217; Mon, 09 Jan 2023 02:15:22 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id h10-20020a05600c2caa00b003cfd58409desm15815376wmc.13.2023.01.09.02.15.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 02:15:21 -0800 (PST) From: Neil Armstrong Date: Mon, 09 Jan 2023 11:15:18 +0100 Subject: [PATCH v3 2/7] dt-bindings: display/msm: document DPU on SM8550 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230103-topic-sm8550-upstream-mdss-dsi-v3-2-660c3bcb127f@linaro.org> References: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the DPU hardware found on the Qualcomm SM8550 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- .../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +++++++++++++++++= ++++ 1 file changed, 134 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml new file mode 100644 index 000000000000..c3d5a98fe3c0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Display DPU + +maintainers: + - Neil Armstrong + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8550-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AHB + - description: Display hf axi + - description: Display MDSS ahb + - description: Display lut + - description: Display core + - description: Display vsync + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible =3D "qcom,sm8550-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM8550_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz =3D /bits/ 64 <325000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; +... --=20 2.34.1