From nobody Mon Sep 15 23:32:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20303C678D8 for ; Mon, 9 Jan 2023 10:16:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236768AbjAIKQi (ORCPT ); Mon, 9 Jan 2023 05:16:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236621AbjAIKPt (ORCPT ); Mon, 9 Jan 2023 05:15:49 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 996D0183B2 for ; Mon, 9 Jan 2023 02:15:22 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id m26-20020a05600c3b1a00b003d9811fcaafso6219508wms.5 for ; Mon, 09 Jan 2023 02:15:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=QlhGmizCHZNPVGwfruBY+PeERtpdL8MSQYu3IWaB+cA=; b=j5PWfI7hsNtLqGEvCNPY5JQApEL9P/X1UTjpCN88sltlumSHiIXHyKOBSeLnxieBWx AC9XpMdFy2Iv14XmQ4NmW++g6X531fnFHTSLbTcsI2FfwbKZ3+WkCJ/iOVr27BuNFpWg 7xreIrL7KJf/JKaBkiC1jspPo6o+rcX5MyHfn+2wOcRkoNgko/en+SV1z6/qI9AFI3cU joOhqZTK/qzhKFh1hJwWfh19buHL5V0PbC5/+5YENh+EZ9iMETY7Y7acXynhWlmThmzZ 48TTlRw5xHRHTxUzcywXLKUHpqnAeZmrv3ijT4eBTxHP0ZRjLOhiJKG0rrdskieeGN6A WL4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QlhGmizCHZNPVGwfruBY+PeERtpdL8MSQYu3IWaB+cA=; b=a52N265HUg2wKiDhdwGVovIZTCSNbyAoRke8O1W/3jBFuzobYQ0mv1cCV0v27ZV5Ff Yx3iPfyw+a0gMUELbhqnjpFCwcJZs1UnOasATLY1z5HhYCnDWRGnNyjKb7DLCn0uRHrf rbX6Q2CJnllpKqJGLXY7b+AyhLlN/1RiHpyXbGdCSXcvqAc+YZysUfU7jXVt4awcvMIV wlQGI7t/3vYrPoQ8C8ivB7L3qfYLKoqASE1/ATRvUaSwbMCIwqU1saaxWh6LU5hRTX7A PnTvLXXagMM/OMMwYLxIbUTdjhyh1YLEdrLlJQGqNizyhFuCNO+kUlIQDPnrf2I7IUpS F/Dw== X-Gm-Message-State: AFqh2kp/S7yKkc207ZgRfkc7rmW3+7RjW0hM1cKhBe2mL0iSCr0zwRv8 sZlCODNAgrhIcIVizJ7AYZWkXw== X-Google-Smtp-Source: AMrXdXtDoONLJwlEgCJ4mzpaWkhPvOuI1P7RAAoqCz2lzMDj3a4D3B8uK5HPlPweG/T18A5/NqGCDw== X-Received: by 2002:a05:600c:5022:b0:3c6:e61e:ae8c with SMTP id n34-20020a05600c502200b003c6e61eae8cmr55951404wmr.28.1673259321222; Mon, 09 Jan 2023 02:15:21 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id h10-20020a05600c2caa00b003cfd58409desm15815376wmc.13.2023.01.09.02.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 02:15:20 -0800 (PST) From: Neil Armstrong Date: Mon, 09 Jan 2023 11:15:17 +0100 Subject: [PATCH v3 1/7] dt-bindings: display/msm: document the SM8550 DSI PHY MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230103-topic-sm8550-upstream-mdss-dsi-v3-1-660c3bcb127f@linaro.org> References: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the SM8550 DSI PHY which is very close from the 7nm and 5nm DSI PHYs found in earlier platforms. Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml= b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 299751a9caea..78ab8c410ccd 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc7280-dsi-phy-7nm - qcom,sm8350-dsi-phy-5nm - qcom,sm8450-dsi-phy-5nm + - qcom,sm8550-dsi-phy-4nm =20 reg: items: --=20 2.34.1 From nobody Mon Sep 15 23:32:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01B73C678D7 for ; Mon, 9 Jan 2023 10:16:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236449AbjAIKQ2 (ORCPT ); Mon, 9 Jan 2023 05:16:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230005AbjAIKPt (ORCPT ); Mon, 9 Jan 2023 05:15:49 -0500 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1E5F1868A for ; Mon, 9 Jan 2023 02:15:23 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id g10so5884297wmo.1 for ; Mon, 09 Jan 2023 02:15:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ED7fYuzAB7f5fc2VJPjwBawtAk4y6MtSvcIIzbfF72M=; b=kPYXWX+xudX2E0Xv91YZXlYwgltLNyURmxLuYkmocyIaB1+Soqs/XCTHQTaobDacfw G2E8xXtvVTMkm3191d74/rrY5HARVJvByfxmmXBA6PNojywxasa2JDDB0+xVelXgrxpf 4Wstr8pbT9M5zZTfEl3RaCG/VdvFoPTYzTCk7DJotNzJ1hZu5Wo+CccEz4wgMOEFgemn 2WVqWus2QBhPFBQq92lEMTMhmzajCZ1OSnGVpAOZp6n+X/D3IZD40g7tVqamreDaYeSB SWAOURhwqVt5HQ7vZ5/BQSm+G+EUDh3MalBFAKOgK9BMoMbtC3JQJpFXWlIqB5UqlT2U utKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ED7fYuzAB7f5fc2VJPjwBawtAk4y6MtSvcIIzbfF72M=; b=SiJeMsWVEcO+aQtk3BX9zcONyZd1KCsIfl9fUH/ZP+GVx46iRYvDt9Et7QELtXzqx6 5fiHooeEBLNbt9FW7TzsQrF93RQjBhkRgki0rjuDDrmXkc7B/Wk/JxdXHOKzaZ+2QDmK BhYWTm2K4H1yDhCsw1gtUE1jG8za2JrtJGbJ5yFRst1Cu2vtv/AWVWGpBwMRkkf5c1G3 mJPcw3gyWKaFWTHpniwC2iU/qGDum5i/oyzmR158LQOd+p40x4PfPUG2j1BA7EPGiEQ1 exLkRuC5SnHvr3kWECmQjKxNYp4RQAaUwMW5CeLTKaJRgB8ieVQSJ/oj1jigOC9WXxOm 1YbQ== X-Gm-Message-State: AFqh2kqSF1bNfuUEA8nbzDbuRpC3x2YllQZCrR8wVbg+JHoklBi9K1Eh RKgA5W2E0eWdhOrhPdUCgAWMKg== X-Google-Smtp-Source: AMrXdXsR8ooi+sQn7m8YAPss+LI9GO3rYcVfny7y77mEFwYiQZIUflbvZwITRfndQkLICMPntESAtQ== X-Received: by 2002:a05:600c:4f83:b0:3d2:3f55:f73f with SMTP id n3-20020a05600c4f8300b003d23f55f73fmr46215333wmq.8.1673259322217; Mon, 09 Jan 2023 02:15:22 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id h10-20020a05600c2caa00b003cfd58409desm15815376wmc.13.2023.01.09.02.15.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 02:15:21 -0800 (PST) From: Neil Armstrong Date: Mon, 09 Jan 2023 11:15:18 +0100 Subject: [PATCH v3 2/7] dt-bindings: display/msm: document DPU on SM8550 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230103-topic-sm8550-upstream-mdss-dsi-v3-2-660c3bcb127f@linaro.org> References: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the DPU hardware found on the Qualcomm SM8550 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- .../bindings/display/msm/qcom,sm8550-dpu.yaml | 134 +++++++++++++++++= ++++ 1 file changed, 134 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml new file mode 100644 index 000000000000..c3d5a98fe3c0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Display DPU + +maintainers: + - Neil Armstrong + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8550-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AHB + - description: Display hf axi + - description: Display MDSS ahb + - description: Display lut + - description: Display core + - description: Display vsync + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible =3D "qcom,sm8550-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM8550_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz =3D /bits/ 64 <325000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; +... --=20 2.34.1 From nobody Mon Sep 15 23:32:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 494F7C678D7 for ; Mon, 9 Jan 2023 10:17:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234183AbjAIKQ4 (ORCPT ); Mon, 9 Jan 2023 05:16:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236937AbjAIKPw (ORCPT ); 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Mon, 09 Jan 2023 02:15:22 -0800 (PST) From: Neil Armstrong Date: Mon, 09 Jan 2023 11:15:19 +0100 Subject: [PATCH v3 3/7] dt-bindings: display/msm: document MDSS on SM8550 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230103-topic-sm8550-upstream-mdss-dsi-v3-3-660c3bcb127f@linaro.org> References: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the MDSS hardware found on the Qualcomm SM8550 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- .../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +++++++++++++++++= ++++ 1 file changed, 331 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml new file mode 100644 index 000000000000..6286e08bb941 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml @@ -0,0 +1,331 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Display MDSS + +maintainers: + - Neil Armstrong + +description: + SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks= like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8550-mdss + + clocks: + items: + - description: Display MDSS AHB + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8550-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8550-dsi-phy-4nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm8550-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0> + interconnect-names =3D "mdp0-mem", "mdp1-mem"; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "nrt_bus", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x1c00 0x2>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm8550-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM8550_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz =3D /bits/ 64 <325000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM8550_MMCX>; + + phys =3D <&dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible =3D "qcom,dsi-phy-4nm-8550"; + reg =3D <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + }; + + dsi@ae96000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae96000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <5>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM8550_MMCX>; + + phys =3D <&dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible =3D "qcom,dsi-phy-4nm-8550"; + reg =3D <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; 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Mon, 09 Jan 2023 02:15:24 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id h10-20020a05600c2caa00b003cfd58409desm15815376wmc.13.2023.01.09.02.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 02:15:24 -0800 (PST) From: Neil Armstrong Date: Mon, 09 Jan 2023 11:15:20 +0100 Subject: [PATCH v3 4/7] drm/msm/dpu: add support for SM8550 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230103-topic-sm8550-upstream-mdss-dsi-v3-4-660c3bcb127f@linaro.org> References: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add definitions for the display hardware used on Qualcomm SM8550 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 197 +++++++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 201 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 42e72ee7aa5e..4449e2f5739c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -472,6 +472,20 @@ static const struct dpu_caps sm8450_dpu_caps =3D { .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, }; =20 +static const struct dpu_caps sm8550_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .qseed_type =3D DPU_SSPP_SCALER_QSEED3LITE, + .smart_dma_rev =3D DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .ubwc_version =3D DPU_HW_UBWC_VER_40, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 5120, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + static const struct dpu_mdp_cfg msm8998_mdp[] =3D { { .name =3D "top_0", .id =3D MDP_TOP, @@ -699,6 +713,37 @@ static const struct dpu_mdp_cfg sm8450_mdp[] =3D { }, }; =20 +static const struct dpu_mdp_cfg sm8550_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0, .len =3D 0x494, + .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), + .highest_bank_bit =3D 0x3, /* TODO: 2 for LP_DDR4 */ + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { + .reg_off =3D 0x4330, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG1] =3D { + .reg_off =3D 0x6330, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG2] =3D { + .reg_off =3D 0x8330, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG3] =3D { + .reg_off =3D 0xa330, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { + .reg_off =3D 0x24330, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA1] =3D { + .reg_off =3D 0x26330, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA2] =3D { + .reg_off =3D 0x28330, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA3] =3D { + .reg_off =3D 0x2a330, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] =3D { + .reg_off =3D 0x2c330, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] =3D { + .reg_off =3D 0x2e330, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] =3D { + .reg_off =3D 0x2bc, .bit_off =3D 20}, + }, +}; + static const struct dpu_mdp_cfg qcm2290_mdp[] =3D { { .name =3D "top_0", .id =3D MDP_TOP, @@ -985,6 +1030,45 @@ static const struct dpu_ctl_cfg sm8450_ctl[] =3D { }, }; =20 +static const struct dpu_ctl_cfg sm8550_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x290, + .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x290, + .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x290, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x290, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x290, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x290, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + static const struct dpu_ctl_cfg qcm2290_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, @@ -1269,6 +1353,40 @@ static const struct dpu_sspp_cfg sm8450_sspp[] =3D { sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), }; =20 +static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =3D + _VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =3D + _VIG_SBLK("1", 8, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 =3D + _VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =3D + _VIG_SBLK("3", 10, DPU_SSPP_SCALER_QSEED3LITE); +static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 =3D _DMA_SBLK("12"= , 5); +static const struct dpu_sspp_sub_blks sd8550_dma_sblk_5 =3D _DMA_SBLK("13"= , 6); + +static const struct dpu_sspp_cfg sm8550_sspp[] =3D { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, + sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, + sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, + sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, + sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_SDM845_MASK, + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK, + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK, + sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK, + sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), +}; + static const struct dpu_sspp_cfg qcm2290_sspp[] =3D { SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK, qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), @@ -1480,6 +1598,16 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_= sblk =3D { .len =3D 0x20, .version =3D 0x20000}, }; =20 +#define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ + {\ + .name =3D _name, .id =3D _id, \ + .base =3D _base, .len =3D 0, \ + .features =3D BIT(DPU_PINGPONG_DITHER), \ + .merge_3d =3D _merge_3d, \ + .sblk =3D &_sblk, \ + .intr_done =3D _done, \ + .intr_rdptr =3D _rdptr, \ + } #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ {\ .name =3D _name, .id =3D _id, \ @@ -1613,6 +1741,33 @@ static const struct dpu_pingpong_cfg sm8450_pp[] =3D= { -1), }; =20 +static const struct dpu_pingpong_cfg sm8550_pp[] =3D { + PP_BLK_DIPHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sb= lk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), + PP_BLK_DIPHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sb= lk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + -1), + PP_BLK_DIPHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sb= lk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + -1), + PP_BLK_DIPHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sb= lk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + -1), + PP_BLK_DIPHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sb= lk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK_DIPHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sb= lk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), + PP_BLK_DIPHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sb= lk, + -1, + -1), + PP_BLK_DIPHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sb= lk, + -1, + -1), +}; + static struct dpu_pingpong_cfg qcm2290_pp[] =3D { PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), @@ -1649,6 +1804,13 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d= [] =3D { MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), }; =20 +static const struct dpu_merge_3d_cfg sm8550_merge_3d[] =3D { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), + MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700), +}; + /************************************************************* * DSC sub blocks config *************************************************************/ @@ -1755,6 +1917,14 @@ static const struct dpu_intf_cfg sm8450_intf[] =3D { INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INT= F_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), }; =20 +static const struct dpu_intf_cfg sm8550_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INT= F_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + /* TODO TE sub-blocks for intf1 & intf2 */ + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MD= P_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MD= P_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INT= F_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + static const struct dpu_intf_cfg qcm2290_intf[] =3D { INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0), INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MD= P_SSPP_TOP0_INTR, 26, 27), @@ -2614,6 +2784,32 @@ static const struct dpu_mdss_cfg sm8450_dpu_cfg =3D { .mdss_irqs =3D IRQ_SM8450_MASK, }; =20 +static const struct dpu_mdss_cfg sm8550_dpu_cfg =3D { + .caps =3D &sm8550_dpu_caps, + .mdp_count =3D ARRAY_SIZE(sm8550_mdp), + .mdp =3D sm8550_mdp, + .ctl_count =3D ARRAY_SIZE(sm8550_ctl), + .ctl =3D sm8550_ctl, + .sspp_count =3D ARRAY_SIZE(sm8550_sspp), + .sspp =3D sm8550_sspp, + .mixer_count =3D ARRAY_SIZE(sm8150_lm), + .mixer =3D sm8150_lm, + .dspp_count =3D ARRAY_SIZE(sm8150_dspp), + .dspp =3D sm8150_dspp, + .pingpong_count =3D ARRAY_SIZE(sm8550_pp), + .pingpong =3D sm8550_pp, + .merge_3d_count =3D ARRAY_SIZE(sm8550_merge_3d), + .merge_3d =3D sm8550_merge_3d, + .intf_count =3D ARRAY_SIZE(sm8550_intf), + .intf =3D sm8550_intf, + .vbif_count =3D ARRAY_SIZE(sdm845_vbif), + .vbif =3D sdm845_vbif, + .reg_dma_count =3D 1, + .dma_cfg =3D &sm8450_regdma, + .perf =3D &sm8450_perf_data, + .mdss_irqs =3D IRQ_SM8450_MASK, +}; + static const struct dpu_mdss_cfg qcm2290_dpu_cfg =3D { .caps =3D &qcm2290_dpu_caps, .mdp_count =3D ARRAY_SIZE(qcm2290_mdp), @@ -2654,6 +2850,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handl= er[] =3D { { .hw_rev =3D DPU_HW_VER_720, .dpu_cfg =3D &sc7280_dpu_cfg}, { .hw_rev =3D DPU_HW_VER_800, .dpu_cfg =3D &sc8280xp_dpu_cfg}, { .hw_rev =3D DPU_HW_VER_810, .dpu_cfg =3D &sm8450_dpu_cfg}, + { .hw_rev =3D DPU_HW_VER_900, .dpu_cfg =3D &sm8550_dpu_cfg}, }; =20 const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index ebcdd8405cab..e9a90c8763ff 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -50,6 +50,7 @@ #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ #define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */ #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ +#define DPU_HW_VER_900 DPU_HW_VER(9, 0, 0) /* sm8550 */ =20 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_1= 70) #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_3= 00) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 2b9e15f99c65..2d9192a6ce00 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -120,6 +120,8 @@ enum dpu_sspp { SSPP_DMA1, SSPP_DMA2, SSPP_DMA3, + SSPP_DMA4, + SSPP_DMA5, SSPP_CURSOR0, SSPP_CURSOR1, SSPP_MAX diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 84a46319421a..6759c6d88083 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1313,6 +1313,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sm8250-dpu", }, { .compatible =3D "qcom,sm8350-dpu", }, { .compatible =3D "qcom,sm8450-dpu", }, + { .compatible =3D "qcom,sm8550-dpu", }, {} }; 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Mon, 09 Jan 2023 02:15:25 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id h10-20020a05600c2caa00b003cfd58409desm15815376wmc.13.2023.01.09.02.15.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 02:15:25 -0800 (PST) From: Neil Armstrong Date: Mon, 09 Jan 2023 11:15:21 +0100 Subject: [PATCH v3 5/7] drm/msm: mdss: add support for SM8550 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230103-topic-sm8550-upstream-mdss-dsi-v3-5-660c3bcb127f@linaro.org> References: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for the MDSS block on SM8550 platform. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index f9ef5085041d..02646e4bb4cd 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -297,6 +297,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 2, 1); break; case DPU_HW_VER_810: + case DPU_HW_VER_900: /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); break; @@ -532,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sm8250-mdss" }, { .compatible =3D "qcom,sm8350-mdss" }, { .compatible =3D "qcom,sm8450-mdss" }, + { .compatible =3D "qcom,sm8550-mdss" }, {} }; MODULE_DEVICE_TABLE(of, mdss_dt_match); --=20 2.34.1 From nobody Mon Sep 15 23:32:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED2BBC71130 for ; Mon, 9 Jan 2023 10:17:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237013AbjAIKRK (ORCPT ); Mon, 9 Jan 2023 05:17:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236964AbjAIKQB (ORCPT ); Mon, 9 Jan 2023 05:16:01 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEE2A186AC for ; Mon, 9 Jan 2023 02:15:27 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id k26-20020a05600c1c9a00b003d972646a7dso8588749wms.5 for ; Mon, 09 Jan 2023 02:15:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=tCP4ISuO0zEM2yHBBm5hXilVTz/TavgIZx7ZveIzedY=; b=zznQeoEBTtxCM+hAUf0zVnfGxiIWGAUedRjLg2sJMU6DK3IirMVL5TfELJTGPRyA/O UIHzk3yD7Pmp33ZcPUfTbaUb7hVA4KCvlqC5uj8ipvFZd43lm0qwiQxe2wJg5AF30T0Z sGxkUwjekgGUd10d8k6SJK1cYVUmkZ0h2lfpfrJGMq5bo+L/qvmF3wtyU49yU942d9Iq XjEHXHsgWGXKJAoe/ze3KZm23hE/de9chqlm3obc3ETIHbn8YkIY455NvfROo4q2VHIn Irwgo9XeCzxyZAXXMpPr2L7wPKadJTSkAI2WakLpRwvC4LIkl7jIojYXZeqtPzLv4v7b 7eww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tCP4ISuO0zEM2yHBBm5hXilVTz/TavgIZx7ZveIzedY=; b=zJrJ1it3N6Qq+++yGTC/o0M82hr9QG1twYuGTEc/E7JDZVh3/d4LogIAu24DyY0nGd iUA8FgDBacXl1AUJdA6ABqtJqISW0s4tr423v3tZLc/E0scue+VZyjs3fkGeJ/YQTG4R k7TkNSdCBjM1h3NJtWek8UMVjFfPk4BoU06SCupNJkMqeM1akzKWmjyNErEggW6uCm2B /VKBY6jjQ/gCoYBV43bZ+XH7vZDlZVMHI7D2GEknqM46kflJzt/Q03W8jOz8hFu1Ndgg UKD01VFHUbNVTptgV6SykRzrn+43n7zwb+NFEv26aNNUIKlAZi3oLEEGSoxumtoKZcpc wnRQ== X-Gm-Message-State: AFqh2kq8u0bjrpN4O9tiOzvQMSOUwOgNPfr67dfnzNM3O2XM45H32gqd IliovQHCCw/TQzCxudaKm/3w6Q== X-Google-Smtp-Source: AMrXdXtxcpmUd3dIa8ba0S7FfJWqftJ1MD86sHHfeBcvxJTaL4I/XE4TUcc75/v/jIBVGik9YCZaOw== X-Received: by 2002:a05:600c:601e:b0:3c6:e61e:ae71 with SMTP id az30-20020a05600c601e00b003c6e61eae71mr55408537wmb.1.1673259326402; Mon, 09 Jan 2023 02:15:26 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id h10-20020a05600c2caa00b003cfd58409desm15815376wmc.13.2023.01.09.02.15.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 02:15:26 -0800 (PST) From: Neil Armstrong Date: Mon, 09 Jan 2023 11:15:22 +0100 Subject: [PATCH v3 6/7] drm/msm/dsi: add support for DSI-PHY on SM8550 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230103-topic-sm8550-upstream-mdss-dsi-v3-6-660c3bcb127f@linaro.org> References: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SM8550 use a 4nm DSI PHYs, which share register definitions with 7nm DSI PHYs. Rather than duplicating the driver, handle 4nm variant inside the common 5+7nm driver. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/Kconfig | 4 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 88 ++++++++++++++++++++++++++-= ---- 4 files changed, 79 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index e7b100d97f88..949b18a29a55 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY Choose this option if DSI PHY on SDM845 is used on the platform. =20 config DRM_MSM_DSI_7NM_PHY - bool "Enable DSI 7nm/5nm PHY driver in MSM DRM" + bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM" depends on DRM_MSM_DSI default y help - Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280 + Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SM8550/SC7= 280 is used on the platform. =20 config DRM_MSM_HDMI diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index 04126af74bb5..cbe669fca26d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_5nm_8350_cfgs }, { .compatible =3D "qcom,sm8450-dsi-phy-5nm", .data =3D &dsi_phy_5nm_8450_cfgs }, + { .compatible =3D "qcom,sm8550-dsi-phy-4nm", + .data =3D &dsi_phy_4nm_8550_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index f7a907ed2b4b..58f9e09f5224 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; =20 struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index 7b2c16b3a36c..af5c952c6ad0 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -47,6 +47,8 @@ #define DSI_PHY_7NM_QUIRK_V4_2 BIT(2) /* Hardware is V4.3 */ #define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) +/* Hardware is V5.2 */ +#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4) =20 struct dsi_pll_config { bool enable_ssc; @@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm = *pll, struct dsi_pll_config =20 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) config->pll_clock_inverters =3D 0x28; - else if (pll_freq <=3D 1000000000ULL) - config->pll_clock_inverters =3D 0xa0; - else if (pll_freq <=3D 2500000000ULL) - config->pll_clock_inverters =3D 0x20; - else if (pll_freq <=3D 3020000000ULL) - config->pll_clock_inverters =3D 0x00; - else - config->pll_clock_inverters =3D 0x40; + else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if (pll_freq <=3D 1300000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq <=3D 2500000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq <=3D 4000000000ULL) + config->pll_clock_inverters =3D 0x00; + else + config->pll_clock_inverters =3D 0x40; + } else { + if (pll_freq <=3D 1000000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq <=3D 2500000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq <=3D 3020000000ULL) + config->pll_clock_inverters =3D 0x00; + else + config->pll_clock_inverters =3D 0x40; + } =20 config->decimal_div_start =3D dec; config->frac_div_start =3D frac; @@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_= 7nm *pll) vco_config_1 =3D 0x01; } =20 + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if (pll->vco_current_rate < 1557000000ULL) + vco_config_1 =3D 0x08; + else + vco_config_1 =3D 0x01; + } + dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1, analog_controls_five_1); dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1); @@ -860,7 +880,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, pr_warn("PLL turned on before configuring PHY\n"); =20 /* Request for REFGEN READY */ - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1); udelay(500); } @@ -894,7 +915,19 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, lane_ctrl0 =3D 0x1f; } =20 - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if (phy->cphy_mode) { + vreg_ctrl_0 =3D 0x45; + vreg_ctrl_1 =3D 0x45; + glbl_rescode_top_ctrl =3D 0x00; + glbl_rescode_bot_ctrl =3D 0x00; + } else { + vreg_ctrl_0 =3D 0x44; + vreg_ctrl_1 =3D 0x19; + glbl_rescode_top_ctrl =3D less_than_1500_mhz ? 0x3c : 0x03; + glbl_rescode_bot_ctrl =3D less_than_1500_mhz ? 0x38 : 0x3c; + } + } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) { if (phy->cphy_mode) { glbl_rescode_top_ctrl =3D less_than_1500_mhz ? 0x3d : 0x01; glbl_rescode_bot_ctrl =3D less_than_1500_mhz ? 0x38 : 0x3b; @@ -943,9 +976,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00); =20 /* program CMN_CTRL_4 for minor_ver 2 chipsets*/ - data =3D dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0); - data =3D data & (0xf0); - if (data =3D=3D 0x20) + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) =3D= =3D 0x20) dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04); =20 /* Configure PHY lane swap (TODO: we need to calculate this) */ @@ -1058,7 +1090,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *p= hy) dsi_phy_hw_v4_0_config_lpcdrx(phy, false); =20 /* Turn off REFGEN Vote */ - if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) { + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0); wmb(); /* Delay to ensure HW removes vote before PHY shut down */ @@ -1092,6 +1125,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_= 97800uA_regulators[] =3D { { .supply =3D "vdds", .init_load_uA =3D 97800 }, }; =20 +static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = =3D { + { .supply =3D "vdds", .init_load_uA =3D 98400 }, +}; + const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs =3D { .has_phy_lane =3D true, .regulator_data =3D dsi_phy_7nm_36mA_regulators, @@ -1201,3 +1238,26 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = =3D { .num_dsi_phy =3D 2, .quirks =3D DSI_PHY_7NM_QUIRK_V4_3, }; + +const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_98400uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_98400uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0xae95000, 0xae97000 }, + .num_dsi_phy =3D 2, + .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, +}; --=20 2.34.1 From nobody Mon Sep 15 23:32:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18AEEC71132 for ; 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Mon, 09 Jan 2023 02:15:27 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id h10-20020a05600c2caa00b003cfd58409desm15815376wmc.13.2023.01.09.02.15.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 02:15:27 -0800 (PST) From: Neil Armstrong Date: Mon, 09 Jan 2023 11:15:23 +0100 Subject: [PATCH v3 7/7] drm/msm/dsi: add support for DSI 2.7.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230103-topic-sm8550-upstream-mdss-dsi-v3-7-660c3bcb127f@linaro.org> References: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-mdss-dsi-v3-0-660c3bcb127f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for DSI 2.7.0 (block used on sm8550). Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 16 ++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/ds= i_cfg.c index 59a4cc95a251..33884ebd2f86 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -181,6 +181,20 @@ static const struct msm_dsi_config sdm845_dsi_cfg =3D { .num_dsi =3D 2, }; =20 +static const struct regulator_bulk_data sm8550_dsi_regulators[] =3D { + { .supply =3D "vdda", .init_load_uA =3D 16800 }, /* 1.2 V */ +}; + +static const struct msm_dsi_config sm8550_dsi_cfg =3D { + .io_offset =3D DSI_6G_REG_SHIFT, + .regulator_data =3D sm8550_dsi_regulators, + .num_regulators =3D ARRAY_SIZE(sm8550_dsi_regulators), + .bus_clk_names =3D dsi_sdm845_bus_clk_names, + .num_bus_clks =3D ARRAY_SIZE(dsi_sdm845_bus_clk_names), + .io_start =3D { 0xae94000, 0xae96000 }, + .num_dsi =3D 2, +}; + static const struct regulator_bulk_data sc7180_dsi_regulators[] =3D { { .supply =3D "vdda", .init_load_uA =3D 21800 }, /* 1.2 V */ }; @@ -302,6 +316,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handler= s[] =3D { &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0, + &sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops}, }; =20 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/ds= i_cfg.h index 95957fab499d..44be4a88aa83 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -26,6 +26,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 #define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 +#define MSM_DSI_6G_VER_MINOR_V2_7_0 0x20070000 =20 #define MSM_DSI_V2_VER_MINOR_8064 0x0 =20 --=20 2.34.1