From nobody Tue Sep 16 01:13:29 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D20AC54EBE for ; Mon, 9 Jan 2023 09:27:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236747AbjAIJ07 (ORCPT ); Mon, 9 Jan 2023 04:26:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234111AbjAIJ0q (ORCPT ); Mon, 9 Jan 2023 04:26:46 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08EBBBE for ; Mon, 9 Jan 2023 01:26:45 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id c4-20020a1c3504000000b003d9e2f72093so3684152wma.1 for ; Mon, 09 Jan 2023 01:26:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1sF7loVbGhMpSd7HZ7uMqlzG5ac86N1+T0FbK9g68oI=; b=BBlAL8lqhWJiC001uN8OnzNb0VWZsddCnLsL4J8Ajk1I7/UhaxxcRROx24l6xEuK2x ifN7CQcEu6kIrN+ZF7iW3N/h9185hmjsm7i4VJc7ZRBtCt46Ze9bPzFX9R+zE5dMHYfY O/syhGqIROofujaPvqRzXZvUD/ZXPnh5JnOtRRLYFz6Ppfu93gOzt042KbXA72AoIOIe swU0uWUSIVp3BUtGuziZiySPedJjNjhRxEQyhUYspt3qWzTVC9wm/2puIZRseBJAlBTS ak+Itx9RsBZZq1egSOCyDQz8hmekb28r4o/dWMVaJCKL2QQLcxVeIS/FUcYZDvsa2hEr ZAdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1sF7loVbGhMpSd7HZ7uMqlzG5ac86N1+T0FbK9g68oI=; b=tkoxRAicBr8n3HoV3mZBvWasoFu2DFRxH1wPGZ3EHpRf9GL8tKLqUob95d7J8JeNkZ WMlpoWswRSzpMyGcewSxQfXXmCWrmhSJIYlp55uTZecIz82uNFv9TZ5JMx+GOkGUmVJW 7G1zjTrMgFwe/kH2TbOtm8qhBBSFKrg9chF6DKUEChmr1g8gWoRYxyjLU90ckRBs9LG2 qYOC2PBqwhIRahXU0ndVV/7h2WXCgC6Pn4P2vl/3wE8ekU8Jycm0YCHBbojrgb13rX+t u3U0WkPrJUSRX5QccjR2rzvCI9QSOn0RNWT7DslO4EiXm0b75LsBBmo/76Rs5hvh+7Tp WucQ== X-Gm-Message-State: AFqh2koHCHjBpxsbK1MeP8nTuurPYoUidoBGqxHF8TDTgc81jMQv/CPm 6g8+jkqviz3qrI+JlRpUf/ATXg== X-Google-Smtp-Source: AMrXdXuROAHHoubEQkQx5UIs5jLhUzFXxmia1WEqCLdXiez5iDcdsGrMsaoBhn7JuhCfDByOhl0Knw== X-Received: by 2002:a05:600c:250:b0:3d2:2830:b8bb with SMTP id 16-20020a05600c025000b003d22830b8bbmr49398105wmj.34.1673256403505; Mon, 09 Jan 2023 01:26:43 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id s23-20020a1cf217000000b003d1e3b1624dsm15195758wmc.2.2023.01.09.01.26.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Jan 2023 01:26:43 -0800 (PST) From: Neil Armstrong Date: Mon, 09 Jan 2023 10:26:35 +0100 Subject: [PATCH v2 3/7] dt-bindings: display/msm: document MDSS on SM8550 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230103-topic-sm8550-upstream-mdss-dsi-v2-3-87f1c16d7635@linaro.org> References: <20230103-topic-sm8550-upstream-mdss-dsi-v2-0-87f1c16d7635@linaro.org> In-Reply-To: <20230103-topic-sm8550-upstream-mdss-dsi-v2-0-87f1c16d7635@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the MDSS hardware found on the Qualcomm SM8550 platform. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- .../bindings/display/msm/qcom,sm8550-mdss.yaml | 331 +++++++++++++++++= ++++ 1 file changed, 331 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml new file mode 100644 index 000000000000..6286e08bb941 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml @@ -0,0 +1,331 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Display MDSS + +maintainers: + - Neil Armstrong + +description: + SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks= like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8550-mdss + + clocks: + items: + - description: Display MDSS AHB + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8550-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8550-dsi-phy-4nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm8550-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0> + interconnect-names =3D "mdp0-mem", "mdp1-mem"; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc MDSS_GDSC>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "nrt_bus", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x1c00 0x2>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm8550-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM8550_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + dpu_intf2_out: endpoint { + remote-endpoint =3D <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz =3D /bits/ 64 <325000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz =3D /bits/ 64 <375000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz =3D /bits/ 64 <514000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM8550_MMCX>; + + phys =3D <&dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible =3D "qcom,dsi-phy-4nm-8550"; + reg =3D <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + }; + + dsi@ae96000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae96000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <5>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM8550_MMCX>; + + phys =3D <&dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible =3D "qcom,dsi-phy-4nm-8550"; + reg =3D <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + }; + }; +... --=20 2.34.1