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[80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:04 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 09/11] clk: imx: cpu: add device tree support Date: Sat, 31 Dec 2022 11:47:34 +0100 Message-Id: <20221231104736.12635-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-cpu.c | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c index cb6ca4cf0535..28fb75c6ecea 100644 --- a/drivers/clk/imx/clk-cpu.c +++ b/drivers/clk/imx/clk-cpu.c @@ -106,3 +106,57 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const = char *parent_name, return hw; } EXPORT_SYMBOL_GPL(imx_clk_hw_cpu); + +/** + * of_imx_cpu_clk_setup - Setup function for imx low power gate + * clock + * @node: device node for the clock + */ +static void __init of_imx_cpu_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct clk *parent_clk, *div, *mux, *pll, *step; + const char *name =3D node->name, *parent_name; + + parent_clk =3D of_clk_get_by_name(node, "fck"); + if (IS_ERR(parent_clk)) { + pr_err("failed to get parent clock for %pOFn\n", node); + return; + } + + div =3D of_clk_get_by_name(node, "div-clk"); + if (IS_ERR(div)) { + pr_err("failed to get div clock for %pOFn\n", node); + return; + } + + mux =3D of_clk_get_by_name(node, "mux-clk"); + if (IS_ERR(div)) { + pr_err("failed to get mux clock for %pOFn\n", node); + return; + } + + pll =3D of_clk_get_by_name(node, "pll-clk"); + if (IS_ERR(div)) { + pr_err("failed to get pll clock for %pOFn\n", node); + return; + } + + step =3D of_clk_get_by_name(node, "step-clk"); + if (IS_ERR(div)) { + pr_err("failed to get step clock for %pOFn\n", node); + return; + } + + parent_name =3D __clk_get_name(parent_clk); + of_property_read_string(node, "clock-output-names", &name); + + hw =3D imx_clk_hw_cpu(name, parent_name, div, mux, pll, step); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + pr_debug("name: %s, parent: %s, div: %s, mux: %s, pll: %s, step: %s\n", + name, parent_name, __clk_get_name(div), __clk_get_name(mux), + __clk_get_name(pll), __clk_get_name(step)); +} +CLK_OF_DECLARE(fsl_cpu_clk, "fsl,cpu-clock", of_imx_cpu_clk_setup); --=20 2.32.0