From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15633C4167B for ; Fri, 30 Dec 2022 15:36:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235136AbiL3PgQ (ORCPT ); Fri, 30 Dec 2022 10:36:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235176AbiL3PgK (ORCPT ); Fri, 30 Dec 2022 10:36:10 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE7141B9C5 for ; Fri, 30 Dec 2022 07:36:04 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id o15so15373682wmr.4 for ; Fri, 30 Dec 2022 07:36:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CO3cf7ELE8VZsDkOe+RWJcSBHW9hBBZN8aOD3+5Q1zI=; b=H3u0gwhz0dbghwgGKX4OEI6z3oljVv9R8wpCJb7hxZNYA/gzMJbcN6RA2IEZick4hM YuZMyeMzLAdvWcpfdXZiMxF/DCLw4DeIu/EWPIR2Lixm4su3oT31XBwYiAKZMsI6Opim N2Ip35qCu9cF3VtMcKKJ0NSSNn7CkDrHXMfawR0Ec+W9U6HDI9gCWkh+l766hDHTSlP8 I3BN2bPxmozrfiAj4SbWOJVZbzmO9ax+nbGGKkrDI2t/nUJ8sH1ns/ejH9nCtwBNrIu7 1XhOJ5mDHUFJtNjhbU1sLp/ud6BE+aP5SqtQtzmZXKIloMCNMLrVifRN7Sea/h40cJnR GBLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CO3cf7ELE8VZsDkOe+RWJcSBHW9hBBZN8aOD3+5Q1zI=; b=CAgCJVChv7yV8x/pPl/zZH1Ons9BA8Mo7Ii06H3LCMjCb8PVc+5ZDxGWJPpkMwlf8T O5mHDcTIShVGyCfJQJ9wUdtJiNiV3gTkwALbKc+Cdgfsivu+rRZtb4FvQFE3pBOuhd4f 9JVbQeVQLPfFWWr8A7z88K9/GIt9vRlgIbmlWLmR2B0Z9tmahaUCMe5SWdcN63VXL4F3 iNZ8RLAVHlI2O/AGdTTj/REjGq0ZL4IFJNFIubEqE/ydcUNsWkDrLq7KCMsOQ5qcn60k bwaWV5f3XNmVOoVr2G/zzmavoVaWHJj/t2HrlErPZPzh5lc98DTtd02nuAMgC2tX2V98 naIQ== X-Gm-Message-State: AFqh2kqTkzFl4uxcNBZ0ymReCX8Taud57INgmZwzY4m/Yx7JKcAWZxZq 1VM/ivEm2+Ns2VWYmPKv+o5DGA== X-Google-Smtp-Source: AMrXdXtIBngmZXHs7up+c2JZtzrks6dw6xuPMLbxcasUNENhHSVfJyMDXo8IX2XeEAYuE4wFfJepbA== X-Received: by 2002:a05:600c:358a:b0:3cf:8d51:1622 with SMTP id p10-20020a05600c358a00b003cf8d511622mr23314246wmq.1.1672414563515; Fri, 30 Dec 2022 07:36:03 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:03 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Cc: Rob Herring Subject: [PATCH v4 01/11] dt-bindings: display: msm: Add qcom,sm8350-dpu binding Date: Fri, 30 Dec 2022 16:35:44 +0100 Message-Id: <20221230153554.105856-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for DPU device tree bindings Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm83= 50-dpu.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml new file mode 100644 index 000000000000..120500395c9a --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Display DPU + +maintainers: + - Robert Foss + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8350-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible =3D "qcom,sm8350-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz =3D /bits/ 64 <345000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz =3D /bits/ 64 <460000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; +... --=20 2.34.1 From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C3A9C4708E for ; Fri, 30 Dec 2022 15:36:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235231AbiL3PgU (ORCPT ); Fri, 30 Dec 2022 10:36:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235192AbiL3PgL (ORCPT ); Fri, 30 Dec 2022 10:36:11 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5E0C1B9D4 for ; Fri, 30 Dec 2022 07:36:06 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id m8-20020a05600c3b0800b003d96f801c48so13185507wms.0 for ; Fri, 30 Dec 2022 07:36:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7vjCatnC6PRJ8n58iyF8sNVzrKF/5FkZi8R44hr7cpA=; b=kt8kd/PJQLF9kAoe+ZkAZjAGtt2a5+hZ47Q2/xsR3nV55OsIO3JGRxrs64QJxVy6By ed3R/R6eWNo0ysPCkzOSiqfazjhoIIKr3vemhuf53BoGJNbvr0OZ2iaP+/urI3cjvTGb YN38Z++OfYBzXdJ8ho+jzOk8FuN0MHVJwIoepwGwr9E9qo+CBGtYYTXV9krSTueo8yWj MwIe7bqrGdOJAXTe7zvJ2xCOyljecKo7rXPBe9bTwAUFDl9eAnOVexggufFhX8gHXj9+ 9be08Xz0e5ZFjf7Z36VTvEQA+dYvvs9zPUGBBSsZKeF3j2HExskx8mnYlurRfomGAKIc 1W8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7vjCatnC6PRJ8n58iyF8sNVzrKF/5FkZi8R44hr7cpA=; b=78OW6c8I35tOhE7q6BUcyLwUKOfwPchM9exR0w8WQ+QAWvrHHEgB8D0iucemgnW1Yn R3x+b1XTw7/ZEo77x84yR9FVFBSx7XDZ3I5DK64n3uvAchAd5aQaXkmkSyo0MW6JDDbF aiK8kLEQkFLPNrqWrZkPYzzwbY5LDN46xPhRv4HF17frWO5pe9raobkiMqeh1qCFX1eq ru6SScUNUa46APW1Ud3ncDvNtme8rJAHKZj8BsHkxe6kv4GGLbhGRCGFTl3AufCwB+i9 HIzcQGcVmcUz7kF2fyTsQEzk52Ex2LPQcsjOjABWbM4r8OkiUyWJ7wAAr9RHB8Z/JP7t gmhA== X-Gm-Message-State: AFqh2kr8KuwMCgzLHjb1UBcVHnFo1uohM7oiyXzbs5ZuV7fbnZvGhlWa wStjnCP4REN0ukWgrJJCutq7VQ== X-Google-Smtp-Source: AMrXdXsgIS36w2kdIOwh3VDgVSZQhdb25rZ+Fl+GX42ZYRr9Zl5+uT9QF2oTcoBNUgFU61KTTQFN5g== X-Received: by 2002:a05:600c:1d28:b0:3d2:1d51:246e with SMTP id l40-20020a05600c1d2800b003d21d51246emr24370672wms.9.1672414565339; Fri, 30 Dec 2022 07:36:05 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:04 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Cc: Rob Herring Subject: [PATCH v4 02/11] dt-bindings: display: msm: Add qcom,sm8350-mdss binding Date: Fri, 30 Dec 2022 16:35:45 +0100 Message-Id: <20221230153554.105856-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI etc. Add YAML schema for MDSS device tree bindings Signed-off-by: Robert Foss Reviewed-by: Rob Herring --- .../display/msm/qcom,sm8350-mdss.yaml | 221 ++++++++++++++++++ 1 file changed, 221 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm83= 50-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml new file mode 100644 index 000000000000..0d452f22f556 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 Display MDSS + +maintainers: + - Robert Foss + +description: + MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm8350-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: mdp0-mem + - const: mdp1-mem + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8350-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-5nm-8350 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm8350-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "mdp0-mem", "mdp1-mem"; + + power-domains =3D <&dispcc MDSS_GDSC>; + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "nrt_bus", "core"; + + iommus =3D <&apps_smmu 0x820 0x402>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm8350-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz =3D /bits/ 64 <345000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz =3D /bits/ 64 <460000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@ae94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + }; +... --=20 2.34.1 From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CA16C4167B for ; Fri, 30 Dec 2022 15:36:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235202AbiL3Pgb (ORCPT ); Fri, 30 Dec 2022 10:36:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235180AbiL3PgN (ORCPT ); Fri, 30 Dec 2022 10:36:13 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEA231BE8B for ; Fri, 30 Dec 2022 07:36:08 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id bn26so724842wrb.0 for ; Fri, 30 Dec 2022 07:36:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ptK4t7ReaSQqe0k1Ma+QWDe00m7vsAdNX1TXQgk/sCE=; b=JjfzbPugND4buJX/NIcyEEtMAVzx+60mnv8MjA3DBbgZ1EEGQ8H3VI6KvqNNrEMpjk 5clqJ1bTtnu7C/0CBUmAeD9qaC/elJBBIjt7/9QhmoRk3O4BSH4/GvrsmjET3h/94EXS 0qCMBmWg/ft7QpTzNHegBxru++NfpfzHRsLfGfjBuNPuABUqsv5LRT+XxEqhFz7kD8cI lnj3XtcUwCNJkPCiHB8Npl1JFKn6sYxS+nQkanQ/q4/LscLtzMQCQERm/TkMkzTk36ue jMgO6uMxG5bFhzyvxM4FyJ93TEvY6D4t6V4Q/03J7o7k3O3Gnizv99YeJ04YalMz/eou EW3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ptK4t7ReaSQqe0k1Ma+QWDe00m7vsAdNX1TXQgk/sCE=; b=c+7aq9BOA4+Q58/d5FHr11EDQRU1Eyec/h/gAjswRtw9IJbR6Oo2gIO5CiO3RY/1DR +iUiyMouR2fS/RzqVG0uf/SKRoFWtFCos1Kn/SWRv4q6yDTWgsH2ZToE73Oq4LK8SQFy twnll30dfVlf2cEc4vOS73FSkcYQQcrr7V91YHHrMg0lc7KgQYq1JLiFAR8lsbaBgu9M PqgJ0/oGyme4CpxQHuEjU8A2W87mrLpXjZULTeamCfbQdEydIT4PgDG+hcqLoc7T2svd 25rstV9fnmwQdR5wXegdbg9YarYwwdg3MoeSxnG67wYnMffIK6I1e5lyet3+40Ftjtqm tZ6A== X-Gm-Message-State: AFqh2koQQ4U+UD7ihIKNF+ovduYvfTmQh9F/fu6tcNST8oMn0jjt4C4c MhigdMjN5PAmE5FK6wcVemt+kQ== X-Google-Smtp-Source: AMrXdXsy9yZ5n6w+Xs6uHcvKrr5L4GO6MsQT7Uu8NzwNt2g3eB2OXI2883Vc4KDKX2vLGaJa3u7nBg== X-Received: by 2002:adf:ecc8:0:b0:26a:5040:78f6 with SMTP id s8-20020adfecc8000000b0026a504078f6mr21846927wro.46.1672414567205; Fri, 30 Dec 2022 07:36:07 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:06 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Subject: [PATCH v4 03/11] drm/msm/dpu: Add SM8350 to hw catalog Date: Fri, 30 Dec 2022 16:35:46 +0100 Message-Id: <20221230153554.105856-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatibility for SM8350 display subsystem, including required entries in DPU hw catalog. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 195 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + 2 files changed, 196 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 2196e205efa5..29181844aa43 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -112,6 +112,15 @@ BIT(MDP_INTF3_INTR) | \ BIT(MDP_INTF4_INTR)) =20 +#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_7xxx_INTR) | \ + BIT(MDP_INTF1_7xxx_INTR) | \ + BIT(MDP_INTF2_7xxx_INTR) | \ + BIT(MDP_INTF3_7xxx_INTR) | \ + 0) + #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ BIT(MDP_SSPP_TOP0_INTR2) | \ BIT(MDP_SSPP_TOP0_HIST_INTR) | \ @@ -379,6 +388,20 @@ static const struct dpu_caps sm8250_dpu_caps =3D { .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, }; =20 +static const struct dpu_caps sm8350_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .qseed_type =3D DPU_SSPP_SCALER_QSEED3LITE, + .smart_dma_rev =3D DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ + .ubwc_version =3D DPU_HW_UBWC_VER_40, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 4096, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + static const struct dpu_caps sc7280_dpu_caps =3D { .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages =3D 0x7, @@ -529,6 +552,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] =3D { }, }; =20 +static const struct dpu_mdp_cfg sm8350_mdp[] =3D { + { + .name =3D "top_0", .id =3D MDP_TOP, + .base =3D 0x0, .len =3D 0x494, + .features =3D 0, + .highest_bank_bit =3D 0x3, /* TODO: 2 for LP_DDR4 */ + .clk_ctrls[DPU_CLK_CTRL_VIG0] =3D { + .reg_off =3D 0x2ac, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG1] =3D { + .reg_off =3D 0x2b4, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG2] =3D { + .reg_off =3D 0x2bc, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_VIG3] =3D { + .reg_off =3D 0x2c4, .bit_off =3D 0}, + .clk_ctrls[DPU_CLK_CTRL_DMA0] =3D { + .reg_off =3D 0x2ac, .bit_off =3D 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA1] =3D { + .reg_off =3D 0x2b4, .bit_off =3D 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] =3D { + .reg_off =3D 0x2bc, .bit_off =3D 8}, + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] =3D { + .reg_off =3D 0x2c4, .bit_off =3D 8}, + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] =3D { + .reg_off =3D 0x2bc, .bit_off =3D 20}, + }, +}; + static const struct dpu_mdp_cfg sc7280_mdp[] =3D { { .name =3D "top_0", .id =3D MDP_TOP, @@ -687,6 +737,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] =3D { }, }; =20 +static const struct dpu_ctl_cfg sm8350_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x1e8, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, + { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x1e8, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, + { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x1e8, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, + { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x1e8, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, + { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x1e8, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, + { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x1e8, + .features =3D CTL_SC7280_MASK, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + static const struct dpu_ctl_cfg sc7280_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, @@ -1213,6 +1302,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] =3D= { -1), }; =20 +static const struct dpu_pingpong_cfg sm8350_pp[] =3D { + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_t= e, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_t= e, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + -1), + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + -1), +}; + static const struct dpu_pingpong_cfg sc7280_pp[] =3D { PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1), PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), @@ -1243,6 +1353,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d= [] =3D { MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), }; =20 +static const struct dpu_merge_3d_cfg sm8350_merge_3d[] =3D { + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), +}; + /************************************************************* * DSC sub blocks config *************************************************************/ @@ -1260,6 +1376,11 @@ static struct dpu_dsc_cfg sdm845_dsc[] =3D { DSC_BLK("dsc_3", DSC_3, 0x80c00), }; =20 +static struct dpu_dsc_cfg sm8350_dsc[] =3D { + DSC_BLK("dsc_0", DSC_0, 0x80000), + DSC_BLK("dsc_1", DSC_1, 0x81000), +}; + /************************************************************* * INTF sub blocks config *************************************************************/ @@ -1307,6 +1428,13 @@ static const struct dpu_intf_cfg sc7280_intf[] =3D { INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INT= F_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), }; =20 +static const struct dpu_intf_cfg sm8350_intf[] =3D { + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INT= F_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MD= P_SSPP_TOP0_INTR, 26, 27), + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MD= P_SSPP_TOP0_INTR, 28, 29), + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INT= F_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), +}; + static const struct dpu_intf_cfg sc8180x_intf[] =3D { INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INT= F_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MD= P_SSPP_TOP0_INTR, 26, 27), @@ -1435,6 +1563,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = =3D { .clk_ctrl =3D DPU_CLK_CTRL_REG_DMA, }; =20 +static const struct dpu_reg_dma_cfg sm8350_regdma =3D { + .base =3D 0x400, + .version =3D 0x00020000, + .trigger_sel_off =3D 0x119c, + .xin_id =3D 7, + .clk_ctrl =3D DPU_CLK_CTRL_REG_DMA, +}; + /************************************************************* * PERF data config *************************************************************/ @@ -1767,6 +1903,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = =3D { .bw_inefficiency_factor =3D 120, }; =20 +static const struct dpu_perf_cfg sm8350_perf_data =3D { + .max_bw_low =3D 11800000, + .max_bw_high =3D 15500000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 40, + /* FIXME: lut tables */ + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + static const struct dpu_perf_cfg qcm2290_perf_data =3D { .max_bw_low =3D 2700000, .max_bw_high =3D 2700000, @@ -1965,6 +2131,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg =3D { .mdss_irqs =3D IRQ_SM8250_MASK, }; =20 +static const struct dpu_mdss_cfg sm8350_dpu_cfg =3D { + .caps =3D &sm8350_dpu_caps, + .mdp_count =3D ARRAY_SIZE(sm8350_mdp), + .mdp =3D sm8350_mdp, + .ctl_count =3D ARRAY_SIZE(sm8350_ctl), + .ctl =3D sm8350_ctl, + .sspp_count =3D ARRAY_SIZE(sm8250_sspp), + .sspp =3D sm8250_sspp, + .mixer_count =3D ARRAY_SIZE(sm8150_lm), + .mixer =3D sm8150_lm, + .dspp_count =3D ARRAY_SIZE(sm8150_dspp), + .dspp =3D sm8150_dspp, + .pingpong_count =3D ARRAY_SIZE(sm8350_pp), + .pingpong =3D sm8350_pp, + .dsc_count =3D ARRAY_SIZE(sm8350_dsc), + .dsc =3D sm8350_dsc, + .merge_3d_count =3D ARRAY_SIZE(sm8350_merge_3d), + .merge_3d =3D sm8350_merge_3d, + .intf_count =3D ARRAY_SIZE(sm8350_intf), + .intf =3D sm8350_intf, + .vbif_count =3D ARRAY_SIZE(sdm845_vbif), + .vbif =3D sdm845_vbif, + .reg_dma_count =3D 1, + .dma_cfg =3D &sm8250_regdma, + .perf =3D &sm8350_perf_data, + .mdss_irqs =3D IRQ_SM8350_MASK, +}; + static const struct dpu_mdss_cfg sc7280_dpu_cfg =3D { .caps =3D &sc7280_dpu_caps, .mdp_count =3D ARRAY_SIZE(sc7280_mdp), @@ -2023,6 +2217,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handl= er[] =3D { { .hw_rev =3D DPU_HW_VER_620, .dpu_cfg =3D &sc7180_dpu_cfg}, { .hw_rev =3D DPU_HW_VER_630, .dpu_cfg =3D &sm6115_dpu_cfg}, { .hw_rev =3D DPU_HW_VER_650, .dpu_cfg =3D &qcm2290_dpu_cfg}, + { .hw_rev =3D DPU_HW_VER_700, .dpu_cfg =3D &sm8350_dpu_cfg}, { .hw_rev =3D DPU_HW_VER_720, .dpu_cfg =3D &sc7280_dpu_cfg}, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 29e7ea5840a2..10c0e525a44e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -46,6 +46,7 @@ #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ #define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */ #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ +#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */ #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ =20 --=20 2.34.1 From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A148C4708E for ; Fri, 30 Dec 2022 15:36:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230242AbiL3Pgi (ORCPT ); Fri, 30 Dec 2022 10:36:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235226AbiL3PgO (ORCPT ); Fri, 30 Dec 2022 10:36:14 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21C101BEA1 for ; Fri, 30 Dec 2022 07:36:10 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id ja17so15380491wmb.3 for ; Fri, 30 Dec 2022 07:36:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UpPq5JazF5WYQ6jpgXZutDJ6jwFO4iP9SJS7CYk0/y0=; b=IpFvRCH7jQ1qWrmgFoWu0b+b6MW5eXC/n7lDMp/rPVGRmWg3wAK2lnV3sL5GxEOPCb JmDCzs9hTA+VhH7QPw83kZltUJ3ltSFX0hHH0dPvSLA4M0RS74+M5e8Jt9meIOwwlnvL A18R45EQaEgYRyrMzV9cpu+Me2+SFgsV44YQ2OiezuBuyKvejcGg1+krBsJFYO6Y1qFS aqO5jfjWy62uWPRBTvoqRLmScF42JSVukLt9hEHb54Bak8o5knX4vxTlDNnUDGNB52nM Uuipi/07BFVK05Qv7GJAMgiOwevHD81cCb5QLmq1P0L+9mmQ1pKUu4iUMnGUku5iCYZw 4AhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UpPq5JazF5WYQ6jpgXZutDJ6jwFO4iP9SJS7CYk0/y0=; b=nLmDjPluoAGs5cbMkrnm70ZpjdAp9euc3Bu37zL1FZqAB2/fPiwEHyt+pNCV6BBH98 Yuk8pe64LqhEIZorFVP+M/wv14vP9bxrTPzC/p/lstCscdIVTtkowQ1yaH73PW8pFGuL PdjSV3PXEk/eNp4+OZtk5zJqF1iZjUoz171BYFoknnWC8X/Tzjl9k3wgYh48qieo1xCo dCou56y2y+pJtIBgh0gt6A1lOgFzqzs/V6nd4n/KvYfTZv9mmh06/zGgDUUbuzpWFuPG gKgYv12gF/VCwHq8S8AW74igOtM09KMvh/iE4I57T9tn1recIuGxZ9rwbkzXX1ezsJg1 /yog== X-Gm-Message-State: AFqh2koXBdEuETC7jvN9cpaSiRex8//GqJRhz7omQJla2mdOzuB1g6d4 USgCCKwUi5A/BiqezAIKrnI6gg== X-Google-Smtp-Source: AMrXdXtLrKFZgNnLmucO73CgP/R0EgJOux6fVGeOspso4zpdgP2Pp5PGqIWUTqEVkYr5vhE+FKsERQ== X-Received: by 2002:a05:600c:295:b0:3d2:259f:9061 with SMTP id 21-20020a05600c029500b003d2259f9061mr28475797wmk.34.1672414568688; Fri, 30 Dec 2022 07:36:08 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:08 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Subject: [PATCH v4 04/11] drm/msm/dpu: Add support for SM8350 Date: Fri, 30 Dec 2022 16:35:47 +0100 Message-Id: <20221230153554.105856-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatibles string, "qcom,sm8350-dpu", for the display processing unit used on Qualcomm SM8350 platform. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 987a74fb7fad..165958d47ec6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1302,6 +1302,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sm6115-dpu", }, { .compatible =3D "qcom,sm8150-dpu", }, { .compatible =3D "qcom,sm8250-dpu", }, + { .compatible =3D "qcom,sm8350-dpu", }, {} }; MODULE_DEVICE_TABLE(of, dpu_dt_match); --=20 2.34.1 From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0FBCC4167B for ; Fri, 30 Dec 2022 15:36:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235294AbiL3Pgl (ORCPT ); Fri, 30 Dec 2022 10:36:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235196AbiL3PgQ (ORCPT ); Fri, 30 Dec 2022 10:36:16 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1F2CDF07 for ; Fri, 30 Dec 2022 07:36:11 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id bi26-20020a05600c3d9a00b003d3404a89faso12735736wmb.1 for ; Fri, 30 Dec 2022 07:36:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kvoIQMnXY8yOCNSxPgg9R4wPyidXv2/4nGMjJvieCBs=; b=kQkZnSFJ15AgGEEKY55HiNDUlYDLyoEBh1YXgROxYK4o8lr2B2fxMNH46Azsx0n7Lg OKpSf7kaY0/HWiR5prROvKGmskVVDAU554WiUwHMf0GzEmRiMOynhNcrjTx4E9H/ZhZU afhLj5DI6lVhFS+MpbVvbL4+a4CQHCvPI6FvbBjc7NguYo+XYzG0EYzevrVjy5QYgUSg 2aWtVVyfG2NKSxJsX+mm4B9ZBVnK8x91vhlgRfZ8Cqwsonqt/9YXJxNjWuYzArkS9fzc UU2II2sT7ShRstyMMY7WpBDTpQa7oAtgMrtntxLtYPRB42zq/GQEIa/2f1x/tSq0LjW4 hkwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kvoIQMnXY8yOCNSxPgg9R4wPyidXv2/4nGMjJvieCBs=; b=ywXRVYpofP8bZ7BZRCBojUmCqFB3QsfLmdsNhOSm9mmYxxEHzS9eg7g0B7WwQ+gwqJ VBWe1606IILqdtbpQlDgCWpyDPvmBtZBg4llskKzjW1O1PYWS5F9A4fZpqmzvvTr6yic LGPRzzyM/uxSbH/DFlo1KtC2VcEFratLBlHzOAnN4XDmNJVZPLAMULUrLPvuiZ8jPXDa sbACGX5aqnUROX7FaPIFIck1wISuJKzJTBVBZSOHjRTt66w1Ex1+R0UrESRfWaVwjK1M hhLw55DzCnuS4bZG08PCrFdvtjUGziaFi5J4SsJg9pqqaJu7/ff2432DIB3nz8a+lWuV HChA== X-Gm-Message-State: AFqh2koKe+rCGcW1hAEPRZoTmVgzKO5lrnEf7N0ZsMfu1ZHQAVucx0kh j2QUzsAQSBwlNj+Lpg85PhzSfg== X-Google-Smtp-Source: AMrXdXtoJmQiYns1YtEHtp8+sf6gqykYvJor9xngXk7t1gmlGQpIcqatDuDWVMpzJn9N5SmzKrIdEQ== X-Received: by 2002:a05:600c:4fcf:b0:3cf:68f8:790b with SMTP id o15-20020a05600c4fcf00b003cf68f8790bmr23587091wmq.11.1672414570323; Fri, 30 Dec 2022 07:36:10 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:09 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Subject: [PATCH v4 05/11] drm/msm: Add support for SM8350 Date: Fri, 30 Dec 2022 16:35:48 +0100 Message-Id: <20221230153554.105856-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatibles string, "qcom,sm8350-mdss", for the multimedia display subsystem unit used on Qualcomm SM8350 platform. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/msm_mdss.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index ef31aad0c2de..34cd3df58aa1 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -297,6 +297,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) /* UBWC_2_0 */ msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x11f); break; + case DPU_HW_VER_700: + /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); + break; case DPU_HW_VER_720: msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); break; @@ -533,6 +537,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sm6115-mdss" }, { .compatible =3D "qcom,sm8150-mdss" }, { .compatible =3D "qcom,sm8250-mdss" }, + { .compatible =3D "qcom,sm8350-mdss" }, { .compatible =3D "qcom,sm8450-mdss" }, {} }; --=20 2.34.1 From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09C86C10F1B for ; Fri, 30 Dec 2022 15:36:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235307AbiL3Pgp (ORCPT ); Fri, 30 Dec 2022 10:36:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235237AbiL3PgY (ORCPT ); Fri, 30 Dec 2022 10:36:24 -0500 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4755B1B9EF for ; Fri, 30 Dec 2022 07:36:13 -0800 (PST) Received: by mail-wm1-x32c.google.com with SMTP id m26-20020a05600c3b1a00b003d9811fcaafso8865751wms.5 for ; Fri, 30 Dec 2022 07:36:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tH0W6Q+n5Go7kNaJjIz/J403hZWvc6cemePnkkWb/v0=; b=OxyOgbPnT7k1489t76J3DHMIpe9egWOSHmjxuepfcChM73OBdggsYx9ol8HmoJ5cdm 6aPkPqMpb5k0RoKhOJvT0pkzvBKsHaNCOiEyVOZJbNB/Xq+F6V2VIRXTGeOWGqxuq9hV cYhKbJqtgcfxVMk7dM2m2epQYDuASLRWRA9BT8fegSoatrzUmlpmzpfGDgtwKkCPcX/Q qPTn5E85AXvFRQVjFIgp0RAw3oYB9Uezg7x+Oz3qTTbzpB96v+4GFVg65Z+o4j2+1p2N o5I7/xvDgURSgAxhhqkuFqBvN/rEa1LBmkzF4oGSTzbkzs6snNPrqtI+3Cq2Z+dwGLUL qsJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tH0W6Q+n5Go7kNaJjIz/J403hZWvc6cemePnkkWb/v0=; b=UgQwjq/5T1TtllQLKoXatOLqr5ar7+CumfHS2zFl/PcDvcgylJ95CVdAvEzwArZJ25 SVkm+sIBSv/duWl2nFaOJvvBjD6UmS5Jrs/kXs3AeDxl3wOLExxBbJ366DbsrxJtybTn 6nD6IEnDVRXG/0NB+z8UUNymcRuQV+QauixjZVwsqdqAdoTAYwLrl0/SmQls/zOZ12E9 rgzUtbFauGmz2RHO0qzKcJ5YPBlSGXTsRl4j6j13vqBOlg39EQbvtGdNDIUHx5z5yXxY nYZMxsxAg5HOg/y8KzHDZ07fatddErLlukgssprahRfTkHcrauWrikYfTsvpdGBsK7xD u2AA== X-Gm-Message-State: AFqh2kph3hFI58Fy4Ys81pISfd43FHmtdB3eptkzWcAygPnBgm9/GM3G 08iMDaQCuHb7PrDuac8sHyEIKg== X-Google-Smtp-Source: AMrXdXssVL6+uV1UQm23RMdUf0R9v/skxVrm8rB/Jv/1iZxEWXeDZ4e84DjIYkDzjEmQgHIuDwSitw== X-Received: by 2002:a05:600c:3584:b0:3d9:719a:8f7d with SMTP id p4-20020a05600c358400b003d9719a8f7dmr15869596wmq.35.1672414571813; Fri, 30 Dec 2022 07:36:11 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:11 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Subject: [PATCH v4 06/11] arm64: dts: qcom: sm8350: Add &tlmm gpio-line-names Date: Fri, 30 Dec 2022 16:35:49 +0100 Message-Id: <20221230153554.105856-7-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add GPIO line names as described by the sm8350-hdk schematic. Signed-off-by: Robert Foss Reviewed-by: Jessica Zhang Tested-by: Jessica Zhang #SM8350 (HDK) --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205 ++++++++++++++++++++++++ 1 file changed, 205 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8350-hdk.dts index 0fcf5bd88fc7..e6deb08c6da0 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -233,6 +233,211 @@ &slpi { =20 &tlmm { gpio-reserved-ranges =3D <52 8>; + + gpio-line-names =3D + "APPS_I2C_SDA", /* GPIO_0 */ + "APPS_I2C_SCL", + "FSA_INT_N", + "USER_LED3_EN", + "SMBUS_SDA_1P8", + "SMBUS_SCL_1P8", + "2M2_3P3_EN", + "ALERT_DUAL_M2_N", + "EXP_UART_CTS", + "EXP_UART_RFR", + "EXP_UART_TX", /* GPIO_10 */ + "EXP_UART_RX", + "NC", + "NC", + "RCM_MARKER1", + "WSA0_EN", + "CAM1_RESET_N", + "CAM0_RESET_N", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "TS_I2C_SDA", /* GPIO_20 */ + "TS_I2C_SCL", + "TS_RESET_N", + "TS_INT_N", + "DISP0_RESET_N", + "DISP1_RESET_N", + "ETH_RESET", + "RCM_MARKER2", + "CAM_DC_MIPI_MUX_EN", + "CAM_DC_MIPI_MUX_SEL", + "AFC_PHY_TA_D_PLUS", /* GPIO_30 */ + "AFC_PHY_TA_D_MINUS", + "PM8008_1_IRQ", + "PM8008_1_RESET_N", + "PM8008_2_IRQ", + "PM8008_2_RESET_N", + "CAM_DC_I3C_SDA", + "CAM_DC_I3C_SCL", + "FP_INT_N", + "FP_WUHB_INT_N", + "SMB_SPMI_DATA", /* GPIO_40 */ + "SMB_SPMI_CLK", + "USB_HUB_RESET", + "FORCE_USB_BOOT", + "LRF_IRQ", + "NC", + "IMU2_INT", + "HDMI_3P3_EN", + "HDMI_RSTN", + "HDMI_1P2_EN", + "HDMI_INT", /* GPIO_50 */ + "USB1_ID", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS", + "NFC_I2C_SDA", /* GPIO_60 */ + "NFC_I2C_SCLC", + "NFC_EN", + "NFC_CLK_REQ", + "HST_WLAN_EN", + "HST_BT_EN", + "HST_SW_CTRL", + "NC", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", /* GPIO_70 */ + "HST_BT_UART_RX", + "CAM_DC_SPI0_MISO", + "CAM_DC_SPI0_MOSI", + "CAM_DC_SPI0_CLK", + "CAM_DC_SPI0_CS_N", + "CAM_DC_SPI1_MISO", + "CAM_DC_SPI1_MOSI", + "CAM_DC_SPI1_CLK", + "CAM_DC_SPI1_CS_N", + "HALL_INT_N", /* GPIO_80 */ + "USB_PHY_PS", + "MDP_VSYNC_P", + "MDP_VSYNC_S", + "ETH_3P3_EN", + "RADAR_INT", + "NFC_DWL_REQ", + "SM_GPIO_87", + "WCD_RESET_N", + "ALSP_INT_N", + "PRESS_INT", /* GPIO_90 */ + "SAR_INT_N", + "SD_CARD_DET_N", + "NC", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "PCIE1_RESET_N", + "PCIE1_CLK_REQ_N", + "PCIE1_WAKE_N", + "CAM_MCLK0", /* GPIO_100 */ + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "CAM_MCLK4", + "CAM_MCLK5", + "CAM2_RESET_N", + "CCI_I2C0_SDA", + "CCI_I2C0_SCL", + "CCI_I2C1_SDA", + "CCI_I2C1_SCL", /* GPIO_110 */ + "CCI_I2C2_SDA", + "CCI_I2C2_SCL", + "CCI_I2C3_SDA", + "CCI_I2C3_SCL", + "CAM5_RESET_N", + "CAM4_RESET_N", + "CAM3_RESET_N", + "IMU1_INT", + "MAG_INT_N", + "MI2S2_I2S_SCK", /* GPIO_120 */ + "MI2S2_I2S_DAT0", + "MI2S2_I2S_WS", + "HIFI_DAC_I2S_MCLK", + "MI2S2_I2S_DAT1", + "HIFI_DAC_I2S_SCK", + "HIFI_DAC_I2S_DAT0", + "NC", + "HIFI_DAC_I2S_WS", + "HST_BT_WLAN_SLIMBUS_CLK", + "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */ + "BT_LED_EN", + "WLAN_LED_EN", + "NC", + "NC", + "NC", + "UIM2_PRESENT", + "NC", + "NC", + "NC", + "UIM1_PRESENT", /* GPIO_140 */ + "NC", + "SM_RFFE0_DATA", + "NC", + "SM_RFFE1_DATA", + "SM_MSS_GRFC4", + "SM_MSS_GRFC5", + "SM_MSS_GRFC6", + "SM_MSS_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", /* GPIO_150 */ + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "HST_SW_CTRL", + "DSI0_STATUS", + "DSI1_STATUS", + "APPS_PBL_BOOT_SPEED_1", + "APPS_BOOT_FROM_ROM", + "APPS_PBL_BOOT_SPEED_0", + "QLINK0_REQ", + "QLINK0_EN", /* GPIO_160 */ + "QLINK0_WMSS_RESET_N", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", /* GPIO_170 */ + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + "DMIC01_CLK", + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "WSA_SWR_CLK", + "WSA_SWR_DATA", + "DMIC45_CLK", /* GPIO_180 */ + "DMIC45_DATA", + "WCD_SWR_TX_DATA2", + "SENSOR_I3C_SDA", + "SENSOR_I3C_SCL", + "CAM_OIS0_I3C_SDA", + "CAM_OIS0_I3C_SCL", + "IMU_SPI_MISO", + "IMU_SPI_MOSI", + "IMU_SPI_CLK", + "IMU_SPI_CS_N", /* GPIO_190 */ + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "SENSOR_I2C_SDA", + "SENSOR_I2C_SCL", + "RADAR_SPI_MISO", + "RADAR_SPI_MOSI", + "RADAR_SPI_CLK", + "RADAR_SPI_CS_N", + "HST_BLE_UART_TX", + "HST_BLE_UART_RX", /* GPIO_200 */ + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; }; =20 &uart2 { --=20 2.34.1 From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53480C4167B for ; Fri, 30 Dec 2022 15:36:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235317AbiL3Pgt (ORCPT ); Fri, 30 Dec 2022 10:36:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235250AbiL3PgZ (ORCPT ); Fri, 30 Dec 2022 10:36:25 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ED2F1B9FD for ; Fri, 30 Dec 2022 07:36:15 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id g10so1598422wmo.1 for ; Fri, 30 Dec 2022 07:36:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vx/P0H2CQ9hUs3jLsvEBWmhDm0mKZhjWQ35wZVj/yOk=; b=EJg7ptfVAcWiReZzZY2HrzrYvyZW/xIfKIya2JheodCF/td/BvBzOUjdNtHsg0bukM xD7u06m1cIY4r38vtETGrgIeiak/XVcChCxIiB+uCdjQRSvvr2w1b8xuS/Rb78jZVtsX gABkF1ZpBq8zopfWHXFlwtE/RDF7Od8C3tTsUNDP4bdkB2HJJ4g6bLLRnKHfM4ub6Q5t vV5VusxpYFvOMdoJ3+ZNMv6/CvmiaF0+2uEfA3f6MBlE3+ADBz1xpmEUTz623gf8cl5Y S6Ewey7AM+Xo8Xho29fsueiAeb5nwZ1ekxMh1dgibeoVSxi/a+/Yx4ulAKp2SUp/1K/6 xyUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vx/P0H2CQ9hUs3jLsvEBWmhDm0mKZhjWQ35wZVj/yOk=; b=QlLLY50N0BAl0vGfvWsDyr1Uaso6sT67A9an3knBcFUI9I8Jp7uShQBAPLUbfV2uT5 pltORy2K7t9rPRAkNFig+cMJrLMeV0IKPkPrHtnm5kK6zEYheIYdiFZxQlnDhuJnPE8H 4OUgWuaWVHrZuwkknjlyDh4iJnbKZ1kKpPEIsi1lXoXwimvKBz8RHPTsC134qNv3p84o JWobKVFEaaATdnMvFwdX5fviPoKE9CBdpWqQyKxCXEZ7eTxYOmgvkIBtPPhUxZJyj2/C THT2GFeILaLnr0cyGGx5371+b1Zt8p4txjc1ayUzlk9t+ONL+DOjHXn3ogUBCqwXwqDb LWdg== X-Gm-Message-State: AFqh2krTCgxL6eZJ2n4xFnAxlu1rrZLugXg5/CwiVuqS7m4ji/+6qrus 2X/VM5soimWC3eC5Se1caM7pYA== X-Google-Smtp-Source: AMrXdXt8BV4jDrWcE//4gLN7FNNLrLb0XuE3b7WF+M76Mf4gqsHlAgIxc0o4VWtGfYCQNpbgV72OnA== X-Received: by 2002:a1c:770b:0:b0:3cf:a18d:399c with SMTP id t11-20020a1c770b000000b003cfa18d399cmr23924928wmi.1.1672414573589; Fri, 30 Dec 2022 07:36:13 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:13 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Cc: Konrad Dybcio Subject: [PATCH v4 07/11] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name Date: Fri, 30 Dec 2022 16:35:50 +0100 Message-Id: <20221230153554.105856-8-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The mmxc power-domain-name is not required, and is not used by either earlier or later SoC versions (sm8250 / sm8450). Signed-off-by: Robert Foss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index a86d9ea93b9d..770ea105a565 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2557,7 +2557,6 @@ dispcc: clock-controller@af00000 { #power-domain-cells =3D <1>; =20 power-domains =3D <&rpmhpd SM8350_MMCX>; - power-domain-names =3D "mmcx"; }; =20 adsp: remoteproc@17300000 { --=20 2.34.1 From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64DB1C3DA7D for ; Fri, 30 Dec 2022 15:37:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235285AbiL3PhE (ORCPT ); Fri, 30 Dec 2022 10:37:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235266AbiL3Pg0 (ORCPT ); Fri, 30 Dec 2022 10:36:26 -0500 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B21691BEB3 for ; Fri, 30 Dec 2022 07:36:16 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id k22-20020a05600c1c9600b003d1ee3a6289so15399083wms.2 for ; Fri, 30 Dec 2022 07:36:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iL37qARH6P3MRzSOtk5quICTwOJji4rF0ACykgztECQ=; b=FOyP5pMDNuXZ6ELt3Q9R7WvQPtfeQcYvV2nKTw2TPRHBq+kFPQzHVTKU29SxlZniNP WybjW/1AttZDKLJ6lpGNNBRdN/8CGO/WTPAWHvUvQl25TelMgVZ1oLqihX7ATUOxDqM1 i6PyXNybeYBZzbCcRBBpXYkZm9enfUhoYDmC4bEWYZ1mw77d1CFJDFweHirRXLzrSCfs RTeCLCfpU2kUt00hvg+7lXxf3HvLC8BmP80D4G+jx5uwd7jYPYU+SiPPhhI9IELvdZjG DHwBGBBRDyfwKNqDibr4VDQEC251T4qKqwPAi3ufJhaQCZSNw085zlTznmvqOn2/hN4Y 2iBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iL37qARH6P3MRzSOtk5quICTwOJji4rF0ACykgztECQ=; b=wV9flFI59GCZV2GFUUXCWYHvi8johHEchkAB0YTvTRAcs7TzbD4pS9PRUGKmvtgiYB /T2P9rVfPqdVNqf/xGxIvfLgHFkcX3HRHbeV2kqLXEcu2wqfNaYYtvwnpl/WJvBeNXPT 034zXug5ppV+OJMGk4uinLIdiulUkvzwOH1psPrLqNP0DOFC6J0OYCrcovhzEJElPUQ0 Yu/CmUzN0y7kesvCcd2A0oT8ow2a2Vx+KzJVytez1apwYfQ9H0gWAQe6RdzKb1kIQBzc Z/61d8Y8uGDE6r/9LxfB1u0v4BbhJ0hrqQqsC+3tkzJzSlTXzZuuwMDxjvbSpk9eh378 IHlw== X-Gm-Message-State: AFqh2krsWKe50H/El91mn+6KPyO7XwRYKpntnc6z7P7AqQ1F6cq5z42C EFeQqZ/VCRrgvgWkX8sNHe/SPA== X-Google-Smtp-Source: AMrXdXvFZ1LAfH4+8KcjsP9ZLf8dXq2/NDo2oQAUwgfrrWEQE+9EQlZtPmNHkv4/WhQjyWm9jhFvIw== X-Received: by 2002:a05:600c:4d20:b0:3d3:5737:3afb with SMTP id u32-20020a05600c4d2000b003d357373afbmr23313629wmp.41.1672414575302; Fri, 30 Dec 2022 07:36:15 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:14 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Cc: Konrad Dybcio Subject: [PATCH v4 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells Date: Fri, 30 Dec 2022 16:35:51 +0100 Message-Id: <20221230153554.105856-9-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use two interconnect cells in order to optionally support a path tag. Signed-off-by: Robert Foss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 770ea105a565..bdefbbb2e38f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1543,56 +1543,56 @@ apps_smmu: iommu@15000000 { config_noc: interconnect@1500000 { compatible =3D "qcom,sm8350-config-noc"; reg =3D <0 0x01500000 0 0xa580>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 mc_virt: interconnect@1580000 { compatible =3D "qcom,sm8350-mc-virt"; reg =3D <0 0x01580000 0 0x1000>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 system_noc: interconnect@1680000 { compatible =3D "qcom,sm8350-system-noc"; reg =3D <0 0x01680000 0 0x1c200>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 aggre1_noc: interconnect@16e0000 { compatible =3D "qcom,sm8350-aggre1-noc"; reg =3D <0 0x016e0000 0 0x1f180>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 aggre2_noc: interconnect@1700000 { compatible =3D "qcom,sm8350-aggre2-noc"; reg =3D <0 0x01700000 0 0x33000>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 mmss_noc: interconnect@1740000 { compatible =3D "qcom,sm8350-mmss-noc"; reg =3D <0 0x01740000 0 0x1f080>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 lpass_ag_noc: interconnect@3c40000 { compatible =3D "qcom,sm8350-lpass-ag-noc"; reg =3D <0 0x03c40000 0 0xf080>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 compute_noc: interconnect@a0c0000{ compatible =3D "qcom,sm8350-compute-noc"; reg =3D <0 0x0a0c0000 0 0xa180>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 @@ -1620,8 +1620,8 @@ ipa: ipa@1e40000 { clocks =3D <&rpmhcc RPMH_IPA_CLK>; clock-names =3D "core"; =20 - interconnects =3D <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnects =3D <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; interconnect-names =3D "memory", "config"; =20 @@ -1661,7 +1661,7 @@ mpss: remoteproc@4080000 { <&rpmhpd SM8350_MSS>; power-domain-names =3D "cx", "mss"; =20 - interconnects =3D <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + interconnects =3D <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; =20 memory-region =3D <&pil_modem_mem>; =20 @@ -2238,7 +2238,7 @@ cdsp: remoteproc@98900000 { <&rpmhpd SM8350_MXC>; power-domain-names =3D "cx", "mxc"; =20 - interconnects =3D <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + interconnects =3D <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 = 0>; =20 memory-region =3D <&pil_cdsp_mem>; =20 @@ -2420,14 +2420,14 @@ usb_2_ssphy: phy@88ebe00 { dc_noc: interconnect@90c0000 { compatible =3D "qcom,sm8350-dc-noc"; reg =3D <0 0x090c0000 0 0x4200>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 gem_noc: interconnect@9100000 { compatible =3D "qcom,sm8350-gem-noc"; reg =3D <0 0x09100000 0 0xb4000>; - #interconnect-cells =3D <1>; + #interconnect-cells =3D <2>; qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 --=20 2.34.1 From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E528C4167B for ; Fri, 30 Dec 2022 15:37:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235218AbiL3PhK (ORCPT ); Fri, 30 Dec 2022 10:37:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235272AbiL3Pg0 (ORCPT ); Fri, 30 Dec 2022 10:36:26 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A9501C105 for ; Fri, 30 Dec 2022 07:36:18 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id k22-20020a05600c1c9600b003d1ee3a6289so15399127wms.2 for ; Fri, 30 Dec 2022 07:36:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qcKidAPkiHJovb9B7oYeIKp0R8mDUvOVBVJ1I025NEo=; b=OewdUX6KjHrsYhZ8u0FaGMUI6AFcn456DYI5nbUlJmpaynZldmOBCuQp1kDl9LwbEJ GoHLE8ZbvWfG0BuGm3wZXzucykQLOJEoFHsElos0LUmxHnzf+QX2e7SPry9g+7s8lPix CJobGiD5cPfylsfC5G/4FIvUnPuF9A65JCTDmYlPBmHoonlEMWhQwR6b/bKfzlKsZ9z+ 7xiJ44B8FbsusasDMgr2TMC+0oNHtDeyh12ZImKOmwVgXCFgT+qiNyo0IZzW8H1buIYu bT0hpmoafHARyK+4RlncXzUhopm4nfCi9yUTZfLtvIX5osP8YY17QOAQveGJ0jSUkiCD KrsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qcKidAPkiHJovb9B7oYeIKp0R8mDUvOVBVJ1I025NEo=; b=nbDmh1lFEK7qcXNeOB5JJ/Z0/7wOhURrexF/ya+2Pnv8NU03oVAAzqzD7imMU+qrur PpizIP2cZTXhNTvZ42Vr7Fc5WGLDjCt2Urpz7u+gOcEXrZpG9knCCN8xkvQw6OCKFL8k y2gn2WoVuLuw9TWh/2erU207CLEGQ94lZ9rT+F7BRFo+YX8L3yExate2MkPSZzR7E70B Fgo0MV5UVhwT0EipD9+E9b7i5JKrV3TCE0Q3o/Gms8mxl7C59qkf23aGrp/y56II1Ypa RQBNfu2vODq8eckdTPedCVDxjE7uKsgNZAPNR8/xsHeR3CE70GC6+RK+x9wfNntuBBDk cW0g== X-Gm-Message-State: AFqh2kqH3hBnZ9XoWSMy/oYNEsOZ8X91KxviT0bpBpbMjoC7BT07XteM gcWG1O92MnhYzny084pfM0ba0A== X-Google-Smtp-Source: AMrXdXuXvKB4YJu+4z8wbT117CWJFgbrKusx4Lw6Y0k/iI0QWhUHbeE5/95/r4lwz6CB4MmlENBPGQ== X-Received: by 2002:a1c:4b14:0:b0:3d3:5ade:4317 with SMTP id y20-20020a1c4b14000000b003d35ade4317mr22446377wma.8.1672414576864; Fri, 30 Dec 2022 07:36:16 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:16 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Subject: [PATCH v4 09/11] arm64: dts: qcom: sm8350: Add display system nodes Date: Fri, 30 Dec 2022 16:35:52 +0100 Message-Id: <20221230153554.105856-10-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these nodes the display subsystem is configured to support one DSI output. Signed-off-by: Robert Foss Reviewed-by: Jessica Zhang Tested-by: Jessica Zhang #SM8350 (HDK) --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 297 ++++++++++++++++++++++++++- 1 file changed, 293 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index bdefbbb2e38f..a80c0bf6d7fd 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2020, Linaro Limited */ =20 +#include #include #include #include @@ -2535,14 +2536,302 @@ usb_2_dwc3: usb@a800000 { }; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,sm8350-mdss"; + reg =3D <0 0x0ae00000 0 0x1000>; + reg-names =3D "mdss"; + + interconnects =3D <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "mdp0-mem", "mdp1-mem"; + + power-domains =3D <&dispcc MDSS_GDSC>; + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", "bus", "nrt_bus", "core"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu 0x820 0x402>; + + status =3D "disabled"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + dpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* TODO: opp-200000000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz =3D /bits/ 64 <345000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz =3D /bits/ 64 <460000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sm8350-dpu"; + reg =3D <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names =3D "mdp", "vbif"; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&dpu_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dpu_intf1_out: endpoint { + remote-endpoint =3D <&dsi0_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae94000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 =3D <&dsi0_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + + status =3D "disabled"; + + dsi0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,dsi-phy-5nm-8350"; + reg =3D <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible =3D "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae96000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 =3D <&dsi1_opp_table>; + power-domains =3D <&rpmhpd SM8350_MMCX>; + + phys =3D <&mdss_dsi1_phy>; + + status =3D "disabled"; + + dsi1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dsi1_in: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible =3D "qcom,dsi-phy-5nm-8350"; + reg =3D <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible =3D "qcom,sm8350-dispcc"; reg =3D <0 0x0af00000 0 0x10000>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <0>, - <0>, - <0>, - <0>, + <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, + <0>, <0>, <0>, <0>; clock-names =3D "bi_tcxo", --=20 2.34.1 From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C705C4167B for ; Fri, 30 Dec 2022 15:37:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235272AbiL3PhO (ORCPT ); Fri, 30 Dec 2022 10:37:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231474AbiL3Pg3 (ORCPT ); Fri, 30 Dec 2022 10:36:29 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3040E1C118 for ; Fri, 30 Dec 2022 07:36:20 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id p1-20020a05600c1d8100b003d8c9b191e0so15383400wms.4 for ; Fri, 30 Dec 2022 07:36:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yUZ4tH5NR3ShWZI1wP6dN+Rtb/3uNAvjYHh4qP5xPyE=; b=FuUdHcpUYQ9YPPxX4SKwXxQvofU88zGqyShLAyTMeaKmnILpPJQWKjaD9YxGKVrQcV W2hIH79me7FKOF8/Y1SB/koRnyad4gOnEl7UQkCVKXSw1RTi28RHLKhZ9jsnlh9QFU3y lK7oQ/5Ic27ki8095V8Cthvy3rc90ovibaN471dl1lcBjRDnU9rafr4zITjqECRkuXxG 6nJmbXYELd7+JuPC1G8TIx7GrtYlPLYEKVppT194T61kc35ThguwFQimR+PMNEsMpbkB ETj8IXSQCPjYdwH17YFaYu9c5k/I+qVRuYwEYFYq+9Wgw4lHHF+a4PXwaHkdRCzuLCjk Trcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yUZ4tH5NR3ShWZI1wP6dN+Rtb/3uNAvjYHh4qP5xPyE=; b=XPHk2/t5a9T3oO+x8FEo66sOVWPSKeyKoRTUbBt0hitBxMtjZb+TGQH44K9nY/Koek usRiY7ktmELsiWwK4KIZV9Dsq0C3pzawJkUeKq3WRTMI2U6Y99SpIsTWqD0QqnrRXafx jpqZM1MQ6yFRwg0bGhRQsnFACccLOcsVR7LYTSPSgG8rS2EHZdxNp4wFDorq7CyhtXTF ykKpbe5UQvLKHOaFrCgXxvYpoTUT7xuaXmvXwWX8LeakKakoI9vZ8mzRFDBUB44DF14i JVyiLKRF/q0vR1W/HerxBmUP4t9cRkuOuhz8TNX4/cB8DbynoXHDEnY/JuDIvk+2S5pX 53LQ== X-Gm-Message-State: AFqh2kq3ovj3L2nvA/Cl/UYzElZiFZCeRGG09sg2FAoksNdsv2piA9wk ZQ4MlUUicW1TzE0idIXzCQ7PRg== X-Google-Smtp-Source: AMrXdXusPgecTGP7fZw7vXdt4tF+S4NwgTctVJuFf4pxyAgs9zjLTxk3FWQlnp0PQZM4bfCkaapj4A== X-Received: by 2002:a05:600c:1e10:b0:3d1:f496:e25f with SMTP id ay16-20020a05600c1e1000b003d1f496e25fmr24402994wmb.16.1672414578700; Fri, 30 Dec 2022 07:36:18 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:18 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Subject: [PATCH v4 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes Date: Fri, 30 Dec 2022 16:35:53 +0100 Message-Id: <20221230153554.105856-11-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the display subsystem and the dsi0 output for the sm8350-hdk board. Signed-off-by: Robert Foss Reviewed-by: Jessica Zhang Tested-by: Jessica Zhang #SM8350 (HDK) --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8350-hdk.dts index e6deb08c6da0..1961f941ff83 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -213,10 +213,32 @@ &cdsp { firmware-name =3D "qcom/sm8350/cdsp.mbn"; }; =20 +&dispcc { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l6b_1p2>; + status =3D "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l5b_0p88>; + status =3D "okay"; +}; + &gpi_dma1 { status =3D "okay"; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_mdp { + status =3D "okay"; +}; + &mpss { status =3D "okay"; firmware-name =3D "qcom/sm8350/modem.mbn"; --=20 2.34.1 From nobody Tue Sep 16 18:12:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05F52C4167B for ; Fri, 30 Dec 2022 15:37:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235365AbiL3PhR (ORCPT ); Fri, 30 Dec 2022 10:37:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235216AbiL3Pgd (ORCPT ); Fri, 30 Dec 2022 10:36:33 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6D371C124 for ; Fri, 30 Dec 2022 07:36:20 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id m8-20020a05600c3b0800b003d96f801c48so13185841wms.0 for ; Fri, 30 Dec 2022 07:36:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ctxOvK28D28f3o6Pe3qUkH7ZxEJEHxVrpCcUg+NUh04=; b=g+KWhYGJxl7BWHkPVNQW1thWA8kAFGFXKPDHOZ373tFmfHrrrPrIE8mDNU+pEvbUcv sYbdVvT4u8d+m/kCUGSTSPZsQvC4+rrnz6+zgo+346ucE9ZCvb/Wx3BHgmR92wKGPbmi T9oHmoYYv3xuSLBhnj1fxSNfm4vVXAFA2EG6KHsA5TKAo5ifpHxLny4+OExRO6+uUwXJ g5T18A0HRPaIxiNXHMIaIrcovFujD0egizRlMXz6MTMPwMy9FQhJvlyxMmkiIxEx+sBS 2BnoQnguqkD7JYL3lq4S4xSpGPaW/fkXLLIbdC3L7QDhqaBbrEf8dYHKOhPgJUwEykwA Z0kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ctxOvK28D28f3o6Pe3qUkH7ZxEJEHxVrpCcUg+NUh04=; b=Co0NRveoJqu8OrehaHTIL54YDAvcEfECRud4f1RPSYKD5eCzK5Ijrcvn8H6t4Imuij NNuO+DsbVD41ChFe5i+t0MZd/ajUIUCEr1DqrTk9kp9Qpetn0wUNNHzLoMBX9tRzgs3j MgH4zJYOpe+j+GpSPavM+rRu26rykGiwkDVVtAcOjF/9GNaOqBR5n7RlmNKepAdemZ4L CArWhZRqkrMqlYy86Z8VSJsKTYsgZ6XjqIDhmAt4+QQCio80H7VTItOs4/BznZm/dtrS IjtHgSw+BMgxsKuEsMgXDgs8viE8vZiNGKfeXwIY/85+hgkqDwIdeUzeMLQxJQKHmk+B k0LA== X-Gm-Message-State: AFqh2kpbrpshw8wWFwqa75AtHALBNzfnk69EENv+OPhShZSYUKvxSmBu cjTR0E0/qHVn5OUlQCcv62IPhA== X-Google-Smtp-Source: AMrXdXupiR1KHz1rC6eEmvSjNUuoXVux4kIV6jTnI6HXoz6vZWYwnghGJbUlafDEiY/R85jV3v2VKw== X-Received: by 2002:a05:600c:4995:b0:3d3:4f43:fbc2 with SMTP id h21-20020a05600c499500b003d34f43fbc2mr23117665wmp.41.1672414580409; Fri, 30 Dec 2022 07:36:20 -0800 (PST) Received: from prec5560.. (freifunk-gw.bsa1-cpe1.syseleven.net. [176.74.57.43]) by smtp.gmail.com with ESMTPSA id l42-20020a05600c1d2a00b003cfbbd54178sm49857993wms.2.2022.12.30.07.36.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 07:36:20 -0800 (PST) From: Robert Foss To: robdclark@gmail.com, quic_abhinavk@quicinc.com, dmitry.baryshkov@linaro.org, sean@poorly.run, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, quic_jesszhan@quicinc.com, robert.foss@linaro.org, angelogioacchino.delregno@somainline.org, loic.poulain@linaro.org, vkoul@kernel.org, a39.skl@gmail.com, quic_khsieh@quicinc.com, quic_vpolimer@quicinc.com, swboyd@chromium.org, dianders@chromium.org, liushixin2@huawei.com, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Marek , vinod.koul@linaro.org Subject: [PATCH v4 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge Date: Fri, 30 Dec 2022 16:35:54 +0100 Message-Id: <20221230153554.105856-12-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221230153554.105856-1-robert.foss@linaro.org> References: <20221230153554.105856-1-robert.foss@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip. In order to toggle the board to enable the HDMI output, switch #7 & #8 on the rightmost multi-switch package have to be toggled to On. Signed-off-by: Robert Foss Reviewed-by: Jessica Zhang Tested-by: Jessica Zhang #SM8350 (HDK) --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 105 ++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8350-hdk.dts index 1961f941ff83..6b21897c92dc 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -20,6 +20,17 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + hdmi-connector { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con: endpoint { + remote-endpoint =3D <<9611_out>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vph_pwr"; @@ -29,6 +40,31 @@ vph_pwr: vph-pwr-regulator { regulator-always-on; regulator-boot-on; }; + + lt9611_1v2: lt9611-1v2-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "LT9611_1V2"; + + vin-supply =3D <&vph_pwr>; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + gpio =3D <&tlmm 49 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + lt9611_3v3: lt9611-3v3-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "LT9611_3V3"; + + vin-supply =3D <&vreg_bob>; + gpio =3D <&tlmm 47 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; }; =20 &adsp { @@ -220,6 +256,15 @@ &dispcc { &mdss_dsi0 { vdda-supply =3D <&vreg_l6b_1p2>; status =3D "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint =3D <<9611_a>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; }; =20 &mdss_dsi0_phy { @@ -231,6 +276,46 @@ &gpi_dma1 { status =3D "okay"; }; =20 +&i2c15 { + clock-frequency =3D <400000>; + status =3D "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible =3D "lontium,lt9611uxc"; + reg =3D <0x2b>; + + interrupts-extended =3D <&tlmm 50 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&tlmm 48 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <<9611_1v2>; + vcc-supply =3D <<9611_3v3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <<9611_state>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + lt9611_a: endpoint { + remote-endpoint =3D <&dsi0_out>; + }; + }; + + port@2 { + reg =3D <2>; + + lt9611_out: endpoint { + remote-endpoint =3D <&hdmi_con>; + }; + }; + }; + }; +}; + &mdss { status =3D "okay"; }; @@ -248,6 +333,10 @@ &qupv3_id_0 { status =3D "okay"; }; =20 +&qupv3_id_2 { + status =3D "okay"; +}; + &slpi { status =3D "okay"; firmware-name =3D "qcom/sm8350/slpi.mbn"; @@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state { drive-strength =3D <2>; output-low; }; + + lt9611_state: lt9611-state { + rst { + pins =3D "gpio48"; + function =3D "normal"; + + output-high; + input-disable; + }; + + irq { + pins =3D "gpio50"; + function =3D "gpio"; + bias-disable; + }; + }; }; --=20 2.34.1