From nobody Tue Sep 16 18:07:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69067C3DA7C for ; Fri, 30 Dec 2022 09:55:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234946AbiL3JzL (ORCPT ); Fri, 30 Dec 2022 04:55:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229505AbiL3JzF (ORCPT ); Fri, 30 Dec 2022 04:55:05 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 872231A807 for ; Fri, 30 Dec 2022 01:55:04 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id o2so16277621pjh.4 for ; Fri, 30 Dec 2022 01:55:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nQ3SWUnwOxxOnluQcCUMkWWYY8S0x44bkExbOVLaC48=; b=PIewojQzM9gdaK16yPowjVkvS9gJxGqd0smybnMugXbwyRtcY9H2OninVnk985ilXH TMWVfHPA6BRCAnxu5fpX77ZfejmB4fbFbMB4bZCf4KFAroubnEKJHZk11sW0q7kA5nIs 4AiXg5tEX7bf5/QTRMAMlAsnF/sR5DdLlV11Hz22LrvJp6XBYdpK0ojD6wIdst2/HdoE h5k+/ypI8nAiyoWOTPOamgGfAJG+2fJQjM6Y3EmvQOda/slt8HZszf64VtPkmYWabqpz QvMutBmXygyO0yarbfhdi5U9YqE/M2I+OzeWzKt1l/uzbgi6eArPebW5MjKoXgrdrxha Vtxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nQ3SWUnwOxxOnluQcCUMkWWYY8S0x44bkExbOVLaC48=; b=5OKnIVUeDf3eiZ2bzV8De1hQGHXJO8ESg/Ujh/LMwx3bAfks+xTtIo//DN59j5neiX +gr38xdySGqVj8Lf9ASFhWeRw0wEOdHICdyg4W7JgfR37INOGIt5SHBGszomq5klqrPD UI/5T/AfnsbxKW4025KpjNSP71WqnlEC2FXhMk4UB35s35lUyaCMs7OZfCaw5jz//APO tes7yaEK72Kjw3XSfQaPKMlzTx4clTEyrRqfFwUl+CZzRAqstqPmHrvxCNCv0dSh7TVU 6ckWDTYdTmf1JxRoLz50AdXv33olPUJaXw+4IdEoHzagqZvyUZzvrIQJxyj5YVNMfm/d 3Nog== X-Gm-Message-State: AFqh2kpHJFK+P/P8DrWHAAiAz1BUpLyx5bu6PRAILMvrqcMcEy4dsN0z fudUftwcqQq1fdoW8eFGsby7AQ== X-Google-Smtp-Source: AMrXdXuxZ5ubvMzAbz1wWO3szh7+ngbcZbwRzttK2BodjwDPRZsxol/hmIC/5rFy4F52A/m9VNKV9A== X-Received: by 2002:a17:902:f38c:b0:189:5f5c:da1f with SMTP id f12-20020a170902f38c00b001895f5cda1fmr25292169ple.5.1672394104051; Fri, 30 Dec 2022 01:55:04 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b7-20020a170902650700b00189c536c72asm14487719plk.148.2022.12.30.01.55.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 01:55:03 -0800 (PST) From: Akihiko Odaki Cc: Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v5 1/7] arm64: Allow the definition of UNKNOWN system register fields Date: Fri, 30 Dec 2022 18:54:46 +0900 Message-Id: <20221230095452.181764-2-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230095452.181764-1-akihiko.odaki@daynix.com> References: <20221230095452.181764-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Marc Zyngier The CCSIDR_EL1 register contains an UNKNOWN field (which replaces fields that were actually defined in previous revisions of the architecture). Define an 'Unkn' field type modeled after the Res0/Res1 types to allow such description. This allows the generation of #define CCSIDR_EL1_UNKN (UL(0) | GENMASK_ULL(31, 28)) which may have its use one day. Hopefully the architecture doesn't add too many of those in the future. Signed-off-by: Marc Zyngier Signed-off-by: Akihiko Odaki Reviewed-by: Mark Brown --- arch/arm64/tools/gen-sysreg.awk | 20 +++++++++++++++++++- arch/arm64/tools/sysreg | 2 ++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.= awk index db461921d256..f6909a6b8380 100755 --- a/arch/arm64/tools/gen-sysreg.awk +++ b/arch/arm64/tools/gen-sysreg.awk @@ -98,6 +98,7 @@ END { =20 res0 =3D "UL(0)" res1 =3D "UL(0)" + unkn =3D "UL(0)" =20 next_bit =3D 63 =20 @@ -112,11 +113,13 @@ END { =20 define(reg "_RES0", "(" res0 ")") define(reg "_RES1", "(" res1 ")") + define(reg "_UNKN", "(" unkn ")") print "" =20 reg =3D null res0 =3D null res1 =3D null + unkn =3D null =20 next } @@ -134,6 +137,7 @@ END { =20 res0 =3D "UL(0)" res1 =3D "UL(0)" + unkn =3D "UL(0)" =20 define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2) define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")") @@ -161,7 +165,9 @@ END { define(reg "_RES0", "(" res0 ")") if (res1 !=3D null) define(reg "_RES1", "(" res1 ")") - if (res0 !=3D null || res1 !=3D null) + if (unkn !=3D null) + define(reg "_UNKN", "(" unkn ")") + if (res0 !=3D null || res1 !=3D null || unkn !=3D null) print "" =20 reg =3D null @@ -172,6 +178,7 @@ END { op2 =3D null res0 =3D null res1 =3D null + unkn =3D null =20 next } @@ -190,6 +197,7 @@ END { next_bit =3D 0 res0 =3D null res1 =3D null + unkn =3D null =20 next } @@ -215,6 +223,16 @@ END { next } =20 +/^Unkn/ && (block =3D=3D "Sysreg" || block =3D=3D "SysregFields") { + expect_fields(2) + parse_bitdef(reg, "UNKN", $2) + field =3D "UNKN_" msb "_" lsb + + unkn =3D unkn " | GENMASK_ULL(" msb ", " lsb ")" + + next +} + /^Field/ && (block =3D=3D "Sysreg" || block =3D=3D "SysregFields") { expect_fields(3) field =3D $3 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 384757a7eda9..8f26fe1bedc6 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -15,6 +15,8 @@ =20 # Res1 [:] =20 +# Unkn [:] + # Field [:] =20 # Enum [:] --=20 2.38.1 From nobody Tue Sep 16 18:07:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B876C10F1B for ; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert CCSIDR_EL1 to automatic generation as per DDI0487I.a. Signed-off-by: Akihiko Odaki Reviewed-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 10 ++++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 7d301700d1a9..910e960661d3 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -425,7 +425,6 @@ =20 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) =20 -#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) =20 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8f26fe1bedc6..097d6faafc87 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -873,6 +873,16 @@ Sysreg SCXTNUM_EL1 3 0 13 0 7 Field 63:0 SoftwareContextNumber EndSysreg =20 +# The bit layout for CCSIDR_EL1 depends on whether FEAT_CCIDX is implement= ed. +# The following is for case when FEAT_CCIDX is not implemented. +Sysreg CCSIDR_EL1 3 1 0 0 0 +Res0 63:32 +Unkn 31:28 +Field 27:13 NumSets +Field 12:3 Associativity +Field 2:0 LineSize +EndSysreg + Sysreg CLIDR_EL1 3 1 0 0 1 Res0 63:47 Field 46:33 Ttypen --=20 2.38.1 From nobody Tue Sep 16 18:07:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA748C4167B for ; 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Fri, 30 Dec 2022 01:55:12 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b7-20020a170902650700b00189c536c72asm14487719plk.148.2022.12.30.01.55.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 01:55:11 -0800 (PST) From: Akihiko Odaki Cc: Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v5 3/7] arm64/sysreg: Add CCSIDR2_EL1 Date: Fri, 30 Dec 2022 18:54:48 +0900 Message-Id: <20221230095452.181764-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230095452.181764-1-akihiko.odaki@daynix.com> References: <20221230095452.181764-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CCSIDR2_EL1 is available if FEAT_CCIDX is implemented as per DDI0487I.a. Signed-off-by: Akihiko Odaki Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 097d6faafc87..01d592cbc0ba 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -899,6 +899,11 @@ Field 5:3 Ctype2 Field 2:0 Ctype1 EndSysreg =20 +Sysreg CCSIDR2_EL1 3 1 0 0 2 +Res0 63:24 +Field 23:0 NumSets +EndSysreg + Sysreg GMID_EL1 3 1 0 0 4 Res0 63:4 Field 3:0 BS --=20 2.38.1 From nobody Tue Sep 16 18:07:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94376C4167B for ; Fri, 30 Dec 2022 09:55:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234965AbiL3JzZ (ORCPT ); Fri, 30 Dec 2022 04:55:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234950AbiL3JzR (ORCPT ); Fri, 30 Dec 2022 04:55:17 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EEF01A809 for ; Fri, 30 Dec 2022 01:55:16 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id n12so8903778pjp.1 for ; Fri, 30 Dec 2022 01:55:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4WsGIW0prujF8xnGwWysGoOLhN4qrtpWJqnT9WJSTvs=; b=MZ6hFxp5qb6KiM3qQ8o8778D0L6Lw+2wriw4sEEuZvPRigiDoS8q20iBToS0o8mTbr 8UOGh6wBCkHuycrokxGKZ4NTVN5uQZSEuvHR7gzhS2+91NYif0CMakcWPjQvot4xaAnN kIOvYiyWnjVNbJtIDYqZDdSIA+SB8xBhoVH7WJEOnmynYxuSyJ5aBQIjTjrtf9hOSlBL AfIX9IV7sdlPCbp4GqUEztdfZ8RTVdjOpZXDELTHY3reO2aczIVPa6xmQIDNkHg9v6kV dmQLbjAt4B1fV50c8E0Mk4JkDGZFAas4wwraQ7HBhmWI2p0CDi2RMsjxTycA9zfR08JG bGEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4WsGIW0prujF8xnGwWysGoOLhN4qrtpWJqnT9WJSTvs=; b=VGrTLlX6ZnEJtODY53PJpZWBx/NWjDwJ5T209sA/e96uF/Z14AhMDw7piaFZQP+Lax nTd/5Fv8Hc36lYvB1uiiJ2aLxLe6KjDMQPGQsQoeZjoqgPN1KkJxgz9PQJAALZGN3GP6 gQtM9SUpkAeu0lETD8YFwonhrGczq23kxRxGsZZFQrl7WSPCDuArit0bbv7r8e3ci44G ooXD7wp1qHUVY3o6P3/5aSlaTkz+hW5E841CpKWVNxn9u/YzEl11sabJLC1XvJe6W+Go DpvzNu2kHOhiANqnivdAb5jdvCaQBUhotrQE0rLSqlbc1c11jCkoc9VZ1gkQvJe3KL/K bxew== X-Gm-Message-State: AFqh2kol23CCHFxgYc/x+5ivOnSuxxBcXmkg7CKS+U2TB1rwM8NEksP5 GwYLzt06hMlIobcHoEvbExSUWg== X-Google-Smtp-Source: AMrXdXss13QkrMhRA6dr0nvpfHQKU4tawzB8AD/+ZDrDtMGJ64TnpAhtOhFlWJsYFDiTDW6CVK9iCg== X-Received: by 2002:a17:902:d051:b0:192:581b:25d3 with SMTP id l17-20020a170902d05100b00192581b25d3mr26381526pll.17.1672394116193; Fri, 30 Dec 2022 01:55:16 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b7-20020a170902650700b00189c536c72asm14487719plk.148.2022.12.30.01.55.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 01:55:15 -0800 (PST) From: Akihiko Odaki Cc: Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v5 4/7] arm64/cache: Move CLIDR macro definitions Date: Fri, 30 Dec 2022 18:54:49 +0900 Message-Id: <20221230095452.181764-5-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230095452.181764-1-akihiko.odaki@daynix.com> References: <20221230095452.181764-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The macros are useful for KVM which needs to manage how CLIDR is exposed to vcpu so move them to include/asm/cache.h, which KVM can refer to. Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/cache.h | 6 ++++++ arch/arm64/kernel/cacheinfo.c | 5 ----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index c0b178d1bb4f..ab7133654a72 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -16,6 +16,12 @@ #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) =20 +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n =3D 1 to 7 */ +#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) +#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) +#define CLIDR_CTYPE(clidr, level) \ + (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) + /* * Memory returned by kmalloc() may be used for DMA, so we must make * sure that all such allocations are cache aligned. Otherwise, diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 97c42be71338..daa7b3f55997 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -11,11 +11,6 @@ #include =20 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ -/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n =3D 1 to 7 */ -#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) -#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) -#define CLIDR_CTYPE(clidr, level) \ - (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) =20 int cache_line_size(void) { --=20 2.38.1 From nobody Tue Sep 16 18:07:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 048CBC4167B for ; Fri, 30 Dec 2022 09:55:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234971AbiL3Jz2 (ORCPT ); Fri, 30 Dec 2022 04:55:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230056AbiL3JzV (ORCPT ); Fri, 30 Dec 2022 04:55:21 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD1871A818 for ; Fri, 30 Dec 2022 01:55:20 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id gv5-20020a17090b11c500b00223f01c73c3so20141258pjb.0 for ; Fri, 30 Dec 2022 01:55:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TArwYxCFrSBrMRpJqgmbgk8qp38LFtviL46odPa8HP0=; b=V2PPlMtIYzvmjTJcM3MvXUYStMJqQopldJARZAwRv+FVYRzKxm8EdA+RLIqYUME/Hm KaLh1Hru7NsccKthnioIq8xgC8HtSTaiYaLEchA1erIpB4E4X6kKPYwGeysBXNGNUgTJ PAsx5OLLBNNwZcX4sPd0A8ExO/quD4GN+oC9qkWRszdG7UjrUcyobgeQ81TgAwNonXEj HiOXauWJkUMAI9tqsTCCKyyr3L6nW3kE/ENC0TVF9GeqnrK6zhnpuAIJ7Ihg/3pH5tHU yFUicSZAxYWNp1OtEPhMsQG3yijRRKISF2DaK/k5PpB3Gi7kJu3OkTzVHggsE+cX/AVl Vyew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TArwYxCFrSBrMRpJqgmbgk8qp38LFtviL46odPa8HP0=; b=7bG16bjDBMhfUOyFhvjOph1slHwNhBXMiK7qfPt3Xib0LZUn82Tve6HnrDfAzd6Xa/ iaEmefO3gyXZ15B9fkw0wfNsY75wIh1e2oEGaYDK4hzO90/MdvpmbEkgxm6tH0IyArzA onscgQqDD15cenbPyzyvW6xesJgYC9Gi6O/KVS/6EeVR4CMJ2V4VKza+/iof6NKHehUK 6Z2dfGn7Fd4EvHTB9lYOgnDoExwmqhp9jSN3wQ3VR5eZJq5deG8boigN9uYGS58PEoQ8 4NqjKu+dmJESVudGCFDdrfGLnBEtyF8t0WQK3WLwgrVcZRk+ipczjyZNft5JUKG6MLwJ DTwg== X-Gm-Message-State: AFqh2kqsboPBHrLeeEF7j6YvjYkA2mz6vzSJWKejCPXw8n7Kmme5n9T/ R4srKXbJx722lGBccKDwcLI/Lw== X-Google-Smtp-Source: AMrXdXspaJ3vzRPB7+tbTBg5dQm4cj1J+UupdkoXbHJZ8PRRvxXXsuCCZcu+swH+OAPkleWIX3ymKQ== X-Received: by 2002:a17:902:b207:b0:189:e3d0:daf8 with SMTP id t7-20020a170902b20700b00189e3d0daf8mr30780379plr.55.1672394120198; Fri, 30 Dec 2022 01:55:20 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b7-20020a170902650700b00189c536c72asm14487719plk.148.2022.12.30.01.55.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 01:55:19 -0800 (PST) From: Akihiko Odaki Cc: Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v5 5/7] KVM: arm64: Always set HCR_TID2 Date: Fri, 30 Dec 2022 18:54:50 +0900 Message-Id: <20221230095452.181764-6-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230095452.181764-1-akihiko.odaki@daynix.com> References: <20221230095452.181764-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Always set HCR_TID2 to trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1. This saves a few lines of code and allows to employ their access trap handlers for more purposes anticipated by the old condition for setting HCR_TID2. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki Reviewed-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_arm.h | 3 ++- arch/arm64/include/asm/kvm_emulate.h | 4 ---- arch/arm64/include/asm/kvm_host.h | 2 -- arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 -- 4 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 8aa8492dafc0..44be46c280c1 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -81,11 +81,12 @@ * SWIO: Turn set/way invalidates into set/way clean+invalidate * PTW: Take a stage2 fault if a stage1 walk steps in device memory * TID3: Trap EL1 reads of group 3 ID registers + * TID2: Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1 */ #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ HCR_BSU_IS | HCR_FB | HCR_TACR | \ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ - HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 ) + HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 | HCR_TID2) #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 9bdba47f7e14..30c4598d643b 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -88,10 +88,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) if (vcpu_el1_is_32bit(vcpu)) vcpu->arch.hcr_el2 &=3D ~HCR_RW; =20 - if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) || - vcpu_el1_is_32bit(vcpu)) - vcpu->arch.hcr_el2 |=3D HCR_TID2; - if (kvm_has_mte(vcpu->kvm)) vcpu->arch.hcr_el2 |=3D HCR_ATA; } diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 45e2136322ba..cc2ede0eaed4 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -621,7 +621,6 @@ static inline bool __vcpu_read_sys_reg_from_cpu(int reg= , u64 *val) return false; =20 switch (reg) { - case CSSELR_EL1: *val =3D read_sysreg_s(SYS_CSSELR_EL1); break; case SCTLR_EL1: *val =3D read_sysreg_s(SYS_SCTLR_EL12); break; case CPACR_EL1: *val =3D read_sysreg_s(SYS_CPACR_EL12); break; case TTBR0_EL1: *val =3D read_sysreg_s(SYS_TTBR0_EL12); break; @@ -666,7 +665,6 @@ static inline bool __vcpu_write_sys_reg_to_cpu(u64 val,= int reg) return false; =20 switch (reg) { - case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index baa5b9b3dde5..147cb4c846c6 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -39,7 +39,6 @@ static inline bool ctxt_has_mte(struct kvm_cpu_context *c= txt) =20 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { - ctxt_sys_reg(ctxt, CSSELR_EL1) =3D read_sysreg(csselr_el1); ctxt_sys_reg(ctxt, SCTLR_EL1) =3D read_sysreg_el1(SYS_SCTLR); ctxt_sys_reg(ctxt, CPACR_EL1) =3D read_sysreg_el1(SYS_CPACR); ctxt_sys_reg(ctxt, TTBR0_EL1) =3D read_sysreg_el1(SYS_TTBR0); @@ -95,7 +94,6 @@ static inline void __sysreg_restore_user_state(struct kvm= _cpu_context *ctxt) static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2); - write_sysreg(ctxt_sys_reg(ctxt, CSSELR_EL1), csselr_el1); =20 if (has_vhe() || !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { --=20 2.38.1 From nobody Tue Sep 16 18:07:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AD2BC4167B for ; Fri, 30 Dec 2022 09:55:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234976AbiL3Jzu (ORCPT ); Fri, 30 Dec 2022 04:55:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234950AbiL3JzZ (ORCPT ); Fri, 30 Dec 2022 04:55:25 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B28A41A823 for ; Fri, 30 Dec 2022 01:55:24 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id g16so11703358plq.12 for ; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The CCSIDR access handler masks the associativity bits according to the bit layout for processors without FEAT_CCIDX. KVM also assumes CCSIDR is 32-bit where it will be 64-bit if FEAT_CCIDX is enabled. Mask FEAT_CCIDX so that these assumptions hold. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/sys_regs.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f4a7c5abcbca..aeabf1f3370b 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1124,6 +1124,12 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, = struct sys_reg_desc const *r ID_DFR0_PERFMON_SHIFT, kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); break; + case SYS_ID_AA64MMFR2_EL1: + val &=3D ~ID_AA64MMFR2_EL1_CCIDX_MASK; + break; + case SYS_ID_MMFR4_EL1: + val &=3D ~ARM64_FEATURE_MASK(ID_MMFR4_CCIDX); + break; } =20 return val; @@ -1605,6 +1611,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { =20 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, + { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, { SYS_DESC(SYS_CTR_EL0), access_ctr }, @@ -2106,6 +2113,10 @@ static const struct sys_reg_desc cp15_regs[] =3D { =20 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, + + /* CCSIDR2 */ + { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, + { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, }; =20 --=20 2.38.1 From nobody Tue Sep 16 18:07:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F29FAC4167B for ; Fri, 30 Dec 2022 09:55:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234970AbiL3Jzr (ORCPT ); Fri, 30 Dec 2022 04:55:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234875AbiL3Jzg (ORCPT ); Fri, 30 Dec 2022 04:55:36 -0500 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD4071A808 for ; Fri, 30 Dec 2022 01:55:28 -0800 (PST) Received: by mail-pl1-x630.google.com with SMTP id jn22so21334588plb.13 for ; Fri, 30 Dec 2022 01:55:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EZMHpVjirLyiPXdcj3AftH3acrrQIEI0GAhijs+zwd8=; b=1+JPGWftJlbkh3gilkmrCEShAyfFef5Qi3++XQaMyqoIIyDyEUBLdTx1RqW/m41YwV fxV/aXP2uX+ysBxo9/fXqWUgXnNMdRXP+wwRWTsT87X7P3BsvVpUhjdoqCODHaN0o/Hx mT0Fg5QPi361iSMpWgI/zNKWdkvOP7iY8So6TBB5IxBwm4M/8dBgexvRozboA3OOitsa EqAO9Zjh4U5n7DYnysfQ93vdSc4/iaRnFKyfMMxj7vzw+P9syRGTQzHodwnIUpFDfmN8 9viFl7efhAirp3UrHV5FTIF8xakCdGb6umQ6DxDBh9LGQju0AYB8/RbxTbapfXQbRvk4 vlFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EZMHpVjirLyiPXdcj3AftH3acrrQIEI0GAhijs+zwd8=; b=fpsTA5oxg0mkRfytDneKuxYAofDvdlsLm1md0gjiekcnL03/P7OxuOsRlukWYLPaY5 szdmW8WXGwS+S87Jgg2H1US3DKtKoYTF0WlE2huHSp8CDBbBxv58bu2Zrf0Q+txx/GAc uCby8gq8uOiVn6KBK4p7mSQwE7/xBMCMveP91rS8CIGqCCixrYvuQlqkb9Y4+IAKgfEo WNhFL3HO4JctpdhZlbOTCB1nZELkSNpFRjxRxHnWDmJU2Xgwr3/ehltmfO6GWvUTfGds R9qfI/Fzpef1khVVhXFtUQkODv5ItGUwQKFnL/1DnKbFLs94FMrlSIrkvRhG/CZArMtP AOCg== X-Gm-Message-State: AFqh2kqEj2j/Ks4/DkEPuxgGUDKXrniDg4pX80wZRRR/j9qKD1ZxSyAV 3Y5iDkW5zz37x+e5RdMPJC9kVQ== X-Google-Smtp-Source: AMrXdXtIgGPiJEotzBfNinM/x3ly5wXoQTeKKSK/kZPXWkunQENUHj2vS2ezmcCAwmq+TE8vOq09VA== X-Received: by 2002:a17:902:a717:b0:18d:d954:5f24 with SMTP id w23-20020a170902a71700b0018dd9545f24mr33794168plq.6.1672394128215; Fri, 30 Dec 2022 01:55:28 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b7-20020a170902650700b00189c536c72asm14487719plk.148.2022.12.30.01.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Dec 2022 01:55:27 -0800 (PST) From: Akihiko Odaki Cc: Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v5 7/7] KVM: arm64: Normalize cache configuration Date: Fri, 30 Dec 2022 18:54:52 +0900 Message-Id: <20221230095452.181764-8-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221230095452.181764-1-akihiko.odaki@daynix.com> References: <20221230095452.181764-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from the sanitized value, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. CLIDR_EL1 and CCSIDR_EL1 are now writable from the userspace so that the VMM can restore the values saved with the old kernel. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/cache.h | 3 + arch/arm64/include/asm/kvm_host.h | 4 + arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 245 ++++++++++++++++++------------ 4 files changed, 157 insertions(+), 96 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index ab7133654a72..a51e6e8f3171 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -22,6 +22,9 @@ #define CLIDR_CTYPE(clidr, level) \ (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) =20 +/* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n =3D 1 to 7 */ +#define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHI= FT) + /* * Memory returned by kmalloc() may be used for DMA, so we must make * sure that all such allocations are cache aligned. Otherwise, diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index cc2ede0eaed4..27abf81c6910 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -178,6 +178,7 @@ struct kvm_vcpu_fault_info { enum vcpu_sysreg { __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ MPIDR_EL1, /* MultiProcessor Affinity Register */ + CLIDR_EL1, /* Cache Level ID Register */ CSSELR_EL1, /* Cache Size Selection Register */ SCTLR_EL1, /* System Control Register */ ACTLR_EL1, /* Auxiliary Control Register */ @@ -417,6 +418,9 @@ struct kvm_vcpu_arch { u64 last_steal; gpa_t base; } steal; + + /* Per-vcpu CCSIDR override or NULL */ + u32 *ccsidr; }; =20 /* diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 5ae18472205a..7980983dbad7 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -157,6 +157,7 @@ void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) if (sve_state) kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu)); kfree(sve_state); + kfree(vcpu->arch.ccsidr); } =20 static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index aeabf1f3370b..47601806636a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -11,6 +11,7 @@ =20 #include #include +#include #include #include #include @@ -81,25 +82,78 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val,= int reg) __vcpu_sys_reg(vcpu, reg) =3D val; } =20 -/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 = */ -static u32 cache_levels; - /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ #define CSSELR_MAX 14 =20 +static u8 get_min_cache_line_size(u32 csselr) +{ + u64 ctr_el0; + int field; + + ctr_el0 =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + field =3D csselr & CSSELR_EL1_InD ? CTR_EL0_IminLine_SHIFT : CTR_EL0_Dmin= Line_SHIFT; + + return cpuid_feature_extract_unsigned_field(ctr_el0, field) - 2; +} + /* Which cache CCSIDR represents depends on CSSELR value. */ -static u32 get_ccsidr(u32 csselr) +static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) { - u32 ccsidr; + if (vcpu->arch.ccsidr) + return vcpu->arch.ccsidr[csselr]; =20 - /* Make sure noone else changes CSSELR during this! */ - local_irq_disable(); - write_sysreg(csselr, csselr_el1); - isb(); - ccsidr =3D read_sysreg(ccsidr_el1); - local_irq_enable(); + /* + * Fabricate a CCSIDR value as the overriding value does not exist. + * The real CCSIDR value will not be used as it can vary by the + * physical CPU which the vcpu currently resides in. + * + * The line size is determined with get_min_cache_line_size(), which + * should be valid for all CPUs even if they have different cache + * configuration. + * + * The associativity bits are cleared, meaning the geometry of all data + * and unified caches (which are guaranteed to be PIPT and thus + * non-aliasing) are 1 set and 1 way. + * Guests should not be doing cache operations by set/way at all, and + * for this reason, we trap them and attempt to infer the intent, so + * that we can flush the entire guest's address space at the appropriate + * time. The exposed geometry minimizes the number of the traps. + * [If guests should attempt to infer aliasing properties from the + * geometry (which is not permitted by the architecture), they would + * only do so for virtually indexed caches.] + * + * We don't check if the cache level exists as it is allowed to return + * an UNKNOWN value if not. + */ + return get_min_cache_line_size(csselr) << CCSIDR_EL1_LineSize_SHIFT; +} =20 - return ccsidr; +static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) +{ + u8 line_size =3D FIELD_GET(CCSIDR_EL1_LineSize, val); + u32 *ccsidr =3D vcpu->arch.ccsidr; + u32 i; + + if ((val & CCSIDR_EL1_RES0) || line_size < get_min_cache_line_size(csselr= )) + return -EINVAL; + + if (!ccsidr) { + if (val =3D=3D get_ccsidr(vcpu, csselr)) + return 0; + + ccsidr =3D kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL); + if (!ccsidr) + return -ENOMEM; + + for (i =3D 0; i < CSSELR_MAX; i++) + ccsidr[i] =3D get_ccsidr(vcpu, i); + + vcpu->arch.ccsidr =3D ccsidr; + } + + ccsidr[csselr] =3D val; + + return 0; } =20 /* @@ -1281,10 +1335,78 @@ static bool access_clidr(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, if (p->is_write) return write_to_read_only(vcpu, p, r); =20 - p->regval =3D read_sysreg(clidr_el1); + p->regval =3D __vcpu_sys_reg(vcpu, r->reg); return true; } =20 +/* + * Fabricate a CLIDR_EL1 value instead of using the real value, which can = vary + * by the physical CPU which the vcpu currently resides in. + */ +static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *= r) +{ + u64 ctr_el0 =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + u64 clidr; + u8 loc; + + if ((ctr_el0 & CTR_EL0_IDC)) { + /* + * Data cache clean to the PoU is not required so LoUU and LoUIS + * will not be set and a unified cache, which will be marked as + * LoC, will be added. + * + * If not DIC, let the unified cache L2 so that an instruction + * cache can be added as L1 later. + */ + loc =3D (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; + clidr =3D CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); + } else { + /* + * Data cache clean to the PoU is required so let L1 have a data + * cache and mark it as LoUU and LoUIS. As L1 has a data cache, + * it can be marked as LoC too. + */ + loc =3D 1; + clidr =3D 1 << CLIDR_LOUU_SHIFT; + clidr |=3D 1 << CLIDR_LOUIS_SHIFT; + clidr |=3D CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); + } + + /* + * Instruction cache invalidation to the PoU is required so let L1 have + * an instruction cache. If L1 already has a data cache, it will be + * CACHE_TYPE_SEPARATE. + */ + if (!(ctr_el0 & CTR_EL0_DIC)) + clidr |=3D CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); + + clidr |=3D loc << CLIDR_LOC_SHIFT; + + /* + * Add tag cache unified to data cache. Allocation tags and data are + * unified in a cache line so that it looks valid even if there is only + * one cache line. + */ + if (kvm_has_mte(vcpu->kvm)) + clidr |=3D 2 << CLIDR_TTYPE_SHIFT(loc); + + __vcpu_sys_reg(vcpu, r->reg) =3D clidr; +} + +static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + u64 val) +{ + u64 ctr_el0 =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + u64 idc =3D !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); + + if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) + return -EINVAL; + + __vcpu_sys_reg(vcpu, rd->reg) =3D val; + + return 0; +} + static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { @@ -1306,22 +1428,10 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, st= ruct sys_reg_params *p, return write_to_read_only(vcpu, p, r); =20 csselr =3D vcpu_read_sys_reg(vcpu, CSSELR_EL1); - p->regval =3D get_ccsidr(csselr); + csselr &=3D CSSELR_EL1_Level | CSSELR_EL1_InD; + if (csselr < CSSELR_MAX) + p->regval =3D get_ccsidr(vcpu, csselr); =20 - /* - * Guests should not be doing cache operations by set/way at all, and - * for this reason, we trap them and attempt to infer the intent, so - * that we can flush the entire guest's address space at the appropriate - * time. - * To prevent this trapping from causing performance problems, let's - * expose the geometry of all data and unified caches (which are - * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. - * [If guests should attempt to infer aliasing properties from the - * geometry (which is not permitted by the architecture), they would - * only do so for virtually indexed caches.] - */ - if (!(csselr & 1)) // data or unified cache - p->regval &=3D ~GENMASK(27, 3); return true; } =20 @@ -1610,7 +1720,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, =20 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, - { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, + { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, + .set_user =3D set_clidr }, { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, @@ -2622,7 +2733,6 @@ id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, =20 FUNCTION_INVARIANT(midr_el1) FUNCTION_INVARIANT(revidr_el1) -FUNCTION_INVARIANT(clidr_el1) FUNCTION_INVARIANT(aidr_el1) =20 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) @@ -2634,7 +2744,6 @@ static void get_ctr_el0(struct kvm_vcpu *v, const str= uct sys_reg_desc *r) static struct sys_reg_desc invariant_sys_regs[] =3D { { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, - { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, }; @@ -2671,33 +2780,7 @@ static int set_invariant_sys_reg(u64 id, u64 __user = *uaddr) return 0; } =20 -static bool is_valid_cache(u32 val) -{ - u32 level, ctype; - - if (val >=3D CSSELR_MAX) - return false; - - /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ - level =3D (val >> 1); - ctype =3D (cache_levels >> (level * 3)) & 7; - - switch (ctype) { - case 0: /* No cache */ - return false; - case 1: /* Instruction cache only */ - return (val & 1); - case 2: /* Data cache only */ - case 4: /* Unified cache */ - return !(val & 1); - case 3: /* Separate instruction and data caches */ - return true; - default: /* Reserved: we can't know instruction or data. */ - return false; - } -} - -static int demux_c15_get(u64 id, void __user *uaddr) +static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) { u32 val; u32 __user *uval =3D uaddr; @@ -2713,16 +2796,16 @@ static int demux_c15_get(u64 id, void __user *uaddr) return -ENOENT; val =3D (id & KVM_REG_ARM_DEMUX_VAL_MASK) >> KVM_REG_ARM_DEMUX_VAL_SHIFT; - if (!is_valid_cache(val)) + if (val >=3D CSSELR_MAX) return -ENOENT; =20 - return put_user(get_ccsidr(val), uval); + return put_user(get_ccsidr(vcpu, val), uval); default: return -ENOENT; } } =20 -static int demux_c15_set(u64 id, void __user *uaddr) +static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) { u32 val, newval; u32 __user *uval =3D uaddr; @@ -2738,16 +2821,13 @@ static int demux_c15_set(u64 id, void __user *uaddr) return -ENOENT; val =3D (id & KVM_REG_ARM_DEMUX_VAL_MASK) >> KVM_REG_ARM_DEMUX_VAL_SHIFT; - if (!is_valid_cache(val)) + if (val >=3D CSSELR_MAX) return -ENOENT; =20 if (get_user(newval, uval)) return -EFAULT; =20 - /* This is also invariant: you can't change it. */ - if (newval !=3D get_ccsidr(val)) - return -EINVAL; - return 0; + return set_ccsidr(vcpu, val, newval); default: return -ENOENT; } @@ -2784,7 +2864,7 @@ int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, co= nst struct kvm_one_reg *reg int err; =20 if ((reg->id & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_DEMUX) - return demux_c15_get(reg->id, uaddr); + return demux_c15_get(vcpu, reg->id, uaddr); =20 err =3D get_invariant_sys_reg(reg->id, uaddr); if (err !=3D -ENOENT) @@ -2828,7 +2908,7 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, co= nst struct kvm_one_reg *reg int err; =20 if ((reg->id & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_DEMUX) - return demux_c15_set(reg->id, uaddr); + return demux_c15_set(vcpu, reg->id, uaddr); =20 err =3D set_invariant_sys_reg(reg->id, uaddr); if (err !=3D -ENOENT) @@ -2840,13 +2920,7 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, c= onst struct kvm_one_reg *reg =20 static unsigned int num_demux_regs(void) { - unsigned int i, count =3D 0; - - for (i =3D 0; i < CSSELR_MAX; i++) - if (is_valid_cache(i)) - count++; - - return count; + return CSSELR_MAX; } =20 static int write_demux_regids(u64 __user *uindices) @@ -2856,8 +2930,6 @@ static int write_demux_regids(u64 __user *uindices) =20 val |=3D KVM_REG_ARM_DEMUX_ID_CCSIDR; for (i =3D 0; i < CSSELR_MAX; i++) { - if (!is_valid_cache(i)) - continue; if (put_user(val | i, uindices)) return -EFAULT; uindices++; @@ -2959,7 +3031,6 @@ int kvm_sys_reg_table_init(void) { bool valid =3D true; unsigned int i; - struct sys_reg_desc clidr; =20 /* Make sure tables are unique and in order. */ valid &=3D check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), f= alse); @@ -2976,23 +3047,5 @@ int kvm_sys_reg_table_init(void) for (i =3D 0; i < ARRAY_SIZE(invariant_sys_regs); i++) invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); =20 - /* - * CLIDR format is awkward, so clean it up. See ARM B4.1.20: - * - * If software reads the Cache Type fields from Ctype1 - * upwards, once it has seen a value of 0b000, no caches - * exist at further-out levels of the hierarchy. So, for - * example, if Ctype3 is the first Cache Type field with a - * value of 0b000, the values of Ctype4 to Ctype7 must be - * ignored. - */ - get_clidr_el1(NULL, &clidr); /* Ugly... */ - cache_levels =3D clidr.val; - for (i =3D 0; i < 7; i++) - if (((cache_levels >> (i*3)) & 7) =3D=3D 0) - break; - /* Clear all higher bits. */ - cache_levels &=3D (1 << (i*3))-1; - return 0; } --=20 2.38.1