From nobody Tue Sep 16 21:19:18 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97117C4167B for ; Thu, 29 Dec 2022 15:50:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233591AbiL2Pux (ORCPT ); Thu, 29 Dec 2022 10:50:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233386AbiL2Puj (ORCPT ); Thu, 29 Dec 2022 10:50:39 -0500 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C85C13F49 for ; Thu, 29 Dec 2022 07:50:38 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id m8-20020a05600c3b0800b003d96f801c48so11169845wms.0 for ; Thu, 29 Dec 2022 07:50:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pEdVYIDCyjQIozVI4BE2BvXtfHehdibvZ1uOyQg9tFw=; b=rBl5gV8tfSZs0wx8/3BCDl745B08pVzPfhtErDJtxzQwRSKqtP7V5t0N0QEJZas1HS SJLB2D7A4qv4+cpSR0A+XzRAzPlLULVRiH/XToUExR9lv0XtVzJhhvxxfyx24M7gHyFZ Y3O52tWSpFXdl/K1MgQBc4yq5+ruYA/DLvHJ9MuK4w7yAdq/j59H+1kcI2CBvPa5HQ9X YMVSJcJpcRn4LROWnLQzPqr/lWPZHVHoaBtf8vxA8jn/oI3ZMYxY0kkF2iP3H/y0Gnm+ LnL/X+JRgil9Ha/Wj8effJfxoeiLZ3M9MBY75EYNrsfwRs5BCRm++WbH/47aUN7pte05 EXVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pEdVYIDCyjQIozVI4BE2BvXtfHehdibvZ1uOyQg9tFw=; b=U7dlsI5inTWWgAO0CYamBRqv7GZ0qjveNGTmiZyV1pbaZUWD7ghxzCxso1wsyQ6mxl eKDvT+9MZQ9yxg29XVhSi7thkg3YIf9hkISBmYlBwWyDZ6ELtTMDtQG4/WqZzfLg4NAL HkzYCz8yJcN6ir13ifCicRXce97d1D6irCoKHmtIg+BQnJw2xvkj6kDYG9X3g+bz8DAO vo4SmVE4cGl+Xhj73a2y2SUhLW/zBqbyicI6oedSBZ0km28hV8IKPMLeRA61N4/DVIsA /RqaqhgvxqBKM7dUQgzFP/4RsHXFM4g0orNEc8C2llNidhkI4rx6w+AqF7FCGATM9NI0 PYDA== X-Gm-Message-State: AFqh2ko/EPuO2iUWEXw5qVWwC3OlizbOunFOIT3/2tWF0FoPE3F36AjF vANLd/6pme42AEqgEBQmnbM8Eg== X-Google-Smtp-Source: AMrXdXurWx7jopuz9KB4ZATRrdqs70MzxtWmuYNMxsjo46bv4aXdd8GMkbcoU6hNh+9QGB2Tu2KnsQ== X-Received: by 2002:a05:600c:b4d:b0:3d3:49db:d84 with SMTP id k13-20020a05600c0b4d00b003d349db0d84mr20148669wmr.20.1672329037892; Thu, 29 Dec 2022 07:50:37 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:8f7a:98d8:9d8d:ced8]) by smtp.gmail.com with ESMTPSA id bh12-20020a05600c3d0c00b003cfa81e2eb4sm25251647wmb.38.2022.12.29.07.50.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Dec 2022 07:50:37 -0800 (PST) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Srinivas Kandagatla , Vinod Koul , Alex Elder , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Krzysztof Kozlowski Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, Bartosz Golaszewski , Konrad Dybcio Subject: [PATCH v6 04/14] tty: serial: qcom-geni-serial: align #define values Date: Thu, 29 Dec 2022 16:50:20 +0100 Message-Id: <20221229155030.418800-5-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221229155030.418800-1-brgl@bgdev.pl> References: <20221229155030.418800-1-brgl@bgdev.pl> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Bartosz Golaszewski Keep the #define symbols aligned for better readability. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- drivers/tty/serial/qcom_geni_serial.c | 62 +++++++++++++-------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 359d9f0ba6ee..a4a50f2a6554 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -39,57 +39,57 @@ #define SE_UART_MANUAL_RFR 0x2ac =20 /* SE_UART_TRANS_CFG */ -#define UART_TX_PAR_EN BIT(0) -#define UART_CTS_MASK BIT(1) +#define UART_TX_PAR_EN BIT(0) +#define UART_CTS_MASK BIT(1) =20 /* SE_UART_TX_STOP_BIT_LEN */ -#define TX_STOP_BIT_LEN_1 0 -#define TX_STOP_BIT_LEN_2 2 +#define TX_STOP_BIT_LEN_1 0 +#define TX_STOP_BIT_LEN_2 2 =20 /* SE_UART_RX_TRANS_CFG */ -#define UART_RX_PAR_EN BIT(3) +#define UART_RX_PAR_EN BIT(3) =20 /* SE_UART_RX_WORD_LEN */ -#define RX_WORD_LEN_MASK GENMASK(9, 0) +#define RX_WORD_LEN_MASK GENMASK(9, 0) =20 /* SE_UART_RX_STALE_CNT */ -#define RX_STALE_CNT GENMASK(23, 0) +#define RX_STALE_CNT GENMASK(23, 0) =20 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ -#define PAR_CALC_EN BIT(0) -#define PAR_EVEN 0x00 -#define PAR_ODD 0x01 -#define PAR_SPACE 0x10 +#define PAR_CALC_EN BIT(0) +#define PAR_EVEN 0x00 +#define PAR_ODD 0x01 +#define PAR_SPACE 0x10 =20 /* SE_UART_MANUAL_RFR register fields */ -#define UART_MANUAL_RFR_EN BIT(31) -#define UART_RFR_NOT_READY BIT(1) -#define UART_RFR_READY BIT(0) +#define UART_MANUAL_RFR_EN BIT(31) +#define UART_RFR_NOT_READY BIT(1) +#define UART_RFR_READY BIT(0) =20 /* UART M_CMD OP codes */ -#define UART_START_TX 0x1 +#define UART_START_TX 0x1 /* UART S_CMD OP codes */ -#define UART_START_READ 0x1 - -#define UART_OVERSAMPLING 32 -#define STALE_TIMEOUT 16 -#define DEFAULT_BITS_PER_CHAR 10 -#define GENI_UART_CONS_PORTS 1 -#define GENI_UART_PORTS 3 -#define DEF_FIFO_DEPTH_WORDS 16 -#define DEF_TX_WM 2 -#define DEF_FIFO_WIDTH_BITS 32 -#define UART_RX_WM 2 +#define UART_START_READ 0x1 + +#define UART_OVERSAMPLING 32 +#define STALE_TIMEOUT 16 +#define DEFAULT_BITS_PER_CHAR 10 +#define GENI_UART_CONS_PORTS 1 +#define GENI_UART_PORTS 3 +#define DEF_FIFO_DEPTH_WORDS 16 +#define DEF_TX_WM 2 +#define DEF_FIFO_WIDTH_BITS 32 +#define UART_RX_WM 2 =20 /* SE_UART_LOOPBACK_CFG */ -#define RX_TX_SORTED BIT(0) -#define CTS_RTS_SORTED BIT(1) -#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) +#define RX_TX_SORTED BIT(0) +#define CTS_RTS_SORTED BIT(1) +#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) =20 /* UART pin swap value */ -#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) +#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) #define IO_MACRO_IO0_SEL 0x3 -#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) +#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) #define IO_MACRO_IO2_IO3_SWAP 0x4640 =20 /* We always configure 4 bytes per FIFO word */ --=20 2.37.2