From nobody Tue Sep 16 21:34:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D49C3C3DA7D for ; Thu, 29 Dec 2022 12:26:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233282AbiL2M0l (ORCPT ); Thu, 29 Dec 2022 07:26:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229535AbiL2M0j (ORCPT ); Thu, 29 Dec 2022 07:26:39 -0500 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6E7F263C; Thu, 29 Dec 2022 04:26:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672316798; x=1703852798; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=dn3epGzIAwWUMYhcvjgvIraCnxNDGBxxZThnjliU4Tw=; b=Z+3/Dx+hEFfWZ/sCBI1YvpUQ59mO+HGjoUbRf7n6iQ4+do1cOFk5K+p8 5Azf0GI9dNqszWyFX3nc0jDoXLIeUPxFyF5Ud1q8hM6inagu2ILLTKESv Q8mSZQ/5pFugLwP/I153CGTF1MHth9nHcluMcqtTGf/mqi/Fv03FS8DHf ANDoLtuS1KrFAHO2VQ+emWXJ5FauZLYz9YdY3/y/vvcX7wS6kzpnua9Ao N40jQpOcz9oSejYeS3pk51Ke1jFjWO6G9wCjEUf44T6wH1B6n+iLQnYYC JL8ZEm3pMwuhnXstN31Q+SEenPHonuSHa05q6jihbnRahJxdSNebhViht A==; X-IronPort-AV: E=McAfee;i="6500,9779,10574"; a="348243043" X-IronPort-AV: E=Sophos;i="5.96,284,1665471600"; d="scan'208";a="348243043" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Dec 2022 04:26:38 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10574"; a="795956079" X-IronPort-AV: E=Sophos;i="5.96,284,1665471600"; d="scan'208";a="795956079" Received: from unknown (HELO rajath-NUC10i7FNH..) ([10.223.165.88]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Dec 2022 04:26:34 -0800 From: Rajat Khandelwal To: jesse.brandeburg@intel.com, anthony.l.nguyen@intel.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, rajat.khandelwal@intel.com, Rajat Khandelwal Subject: [PATCH] igc: Mask replay rollover/timeout errors in I225_LMVP Date: Thu, 29 Dec 2022 17:56:40 +0530 Message-Id: <20221229122640.239859-1-rajat.khandelwal@linux.intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The CPU logs get flooded with replay rollover/timeout AER errors in the system with i225_lmvp connected, usually inside thunderbolt devices. One of the prominent TBT4 docks we use is HP G4 Hook2, which incorporates an Intel Foxville chipset, which uses the igc driver. On connecting ethernet, CPU logs get inundated with these errors. The point is we shouldn't be spamming the logs with such correctible errors as it confuses other kernel developers less familiar with PCI errors, support staff, and users who happen to look at the logs. Signed-off-by: Rajat Khandelwal --- drivers/net/ethernet/intel/igc/igc_main.c | 28 +++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethern= et/intel/igc/igc_main.c index ebff0e04045d..a3a6e8086c8d 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -6201,6 +6201,26 @@ u32 igc_rd32(struct igc_hw *hw, u32 reg) return value; } =20 +#ifdef CONFIG_PCIEAER +static void igc_mask_aer_replay_correctible(struct igc_adapter *adapter) +{ + struct pci_dev *pdev =3D adapter->pdev; + u32 aer_pos, corr_mask; + + if (pdev->device !=3D IGC_DEV_ID_I225_LMVP) + return; + + aer_pos =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); + if (!aer_pos) + return; + + pci_read_config_dword(pdev, aer_pos + PCI_ERR_COR_MASK, &corr_mask); + + corr_mask |=3D PCI_ERR_COR_REP_ROLL | PCI_ERR_COR_REP_TIMER; + pci_write_config_dword(pdev, aer_pos + PCI_ERR_COR_MASK, corr_mask); +} +#endif + /** * igc_probe - Device Initialization Routine * @pdev: PCI device information struct @@ -6236,8 +6256,6 @@ static int igc_probe(struct pci_dev *pdev, if (err) goto err_pci_reg; =20 - pci_enable_pcie_error_reporting(pdev); - err =3D pci_enable_ptm(pdev, NULL); if (err < 0) dev_info(&pdev->dev, "PCIe PTM not supported by PCIe bus/controller\n"); @@ -6272,6 +6290,12 @@ static int igc_probe(struct pci_dev *pdev, if (!adapter->io_addr) goto err_ioremap; =20 +#ifdef CONFIG_PCIEAER + igc_mask_aer_replay_correctible(adapter); +#endif + + pci_enable_pcie_error_reporting(pdev); + /* hw->hw_addr can be zeroed, so use adapter->io_addr for unmap */ hw->hw_addr =3D adapter->io_addr; =20 --=20 2.34.1