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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT076.mail.protection.outlook.com (10.13.174.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5944.16 via Frontend Transport; Wed, 28 Dec 2022 16:31:25 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 28 Dec 2022 10:31:23 -0600 From: Mario Limonciello To: Javier Martinez Canillas , Alex Deucher , CC: Carlos Soriano Sanchez , , , "David Airlie" , Daniel Vetter , , Mario Limonciello , "Pan, Xinhui" Subject: [PATCH v2 08/11] drm/amd: Request GFX9 microcode during IP discovery Date: Wed, 28 Dec 2022 10:30:55 -0600 Message-ID: <20221228163102.468-9-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221228163102.468-1-mario.limonciello@amd.com> References: <20221228163102.468-1-mario.limonciello@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT076:EE_|SJ2PR12MB8011:EE_ X-MS-Office365-Filtering-Correlation-Id: 5792695b-cfad-49cd-3fe9-08dae8f0f716 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Dec 2022 16:31:25.9853 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5792695b-cfad-49cd-3fe9-08dae8f0f716 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT076.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8011 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If GFX9 microcode is required but not available during early init, the microcode framebuffer will have already been released and the screen will freeze. Move the request for GFX9 microcode into the IP discovery phase so that if it's not available, IP discovery will fail. Signed-off-by: Mario Limonciello --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 144 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 143 +---------------- 2 files changed, 152 insertions(+), 135 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/dr= m/amd/amdgpu/amdgpu_discovery.c index 479266ed2b7f..0da16abd6b24 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -158,6 +158,68 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); =20 + +/* gfx9 */ +MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); +MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vega10_me.bin"); +MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); +MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); +MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vega12_me.bin"); +MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); +MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); +MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); +MODULE_FIRMWARE("amdgpu/vega20_me.bin"); +MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); +MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); +MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/raven_ce.bin"); +MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); +MODULE_FIRMWARE("amdgpu/raven_me.bin"); +MODULE_FIRMWARE("amdgpu/raven_mec.bin"); +MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); +MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); +MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); +MODULE_FIRMWARE("amdgpu/picasso_me.bin"); +MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); +MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); +MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); +MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); + +MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); +MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); +MODULE_FIRMWARE("amdgpu/raven2_me.bin"); +MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); +MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); +MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); +MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); +MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); +MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); +MODULE_FIRMWARE("amdgpu/renoir_me.bin"); +MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); +MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); + +MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); +MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); + static const char *hw_id_names[HW_ID_MAX] =3D { [MP1_HWID] =3D "MP1", [MP2_HWID] =3D "MP2", @@ -1845,8 +1907,87 @@ static int amdgpu_discovery_set_display_ip_blocks(st= ruct amdgpu_device *adev) return 0; } =20 +static int amdgpu_discovery_load_gfx9(struct amdgpu_device *adev, char *uc= ode_prefix) +{ + uint32_t smu_version; + char fw_name[40]; + int r; + + /* No CPG in Arcturus */ + if (adev->gfx.num_gfx_rings) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix); + r =3D request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); + if (r) + return r; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix); + r =3D request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); + if (r) + return r; + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", ucode_prefix); + r =3D request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); + if (r) + return r; + } + + if (amdgpu_sriov_vf(adev) && (adev->asic_type =3D=3D CHIP_ALDEBARAN)) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", ucode_prefix= ); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix); + r =3D request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); + if (r) + return r; + + /* + * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin + * instead of picasso_rlc.bin. + * Judgment method: + * PCO AM4: revision >=3D 0xC8 && revision <=3D 0xCF + * or revision >=3D 0xD8 && revision <=3D 0xDF + * otherwise is PCO FP5 + */ + if (!strcmp(ucode_prefix, "picasso") && + (((adev->pdev->revision >=3D 0xC8) && (adev->pdev->revision <=3D 0xCF)) = || + ((adev->pdev->revision >=3D 0xD8) && (adev->pdev->revision <=3D 0xDF)))) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", ucode_prefix= ); + else if (!strcmp(ucode_prefix, "raven") && (amdgpu_pm_load_smu_firmware(a= dev, &smu_version) =3D=3D 0) && + (smu_version >=3D 0x41e2b)) + /** + *SMC is loaded by SBIOS on APU and it's able to get the SMU version dire= ctly. + */ + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", ucode_pre= fix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); + r =3D request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); + if (r) + return r; + + /* mec2 fw bin support */ + if (adev->ip_versions[GC_HWIP][0] =3D=3D IP_VERSION(9, 4, 2) || + adev->ip_versions[GC_HWIP][0] =3D=3D IP_VERSION(9, 4, 1) || + adev->ip_versions[GC_HWIP][0] =3D=3D IP_VERSION(9, 3, 0)) { + + if (amdgpu_sriov_vf(adev) && (adev->asic_type =3D=3D CHIP_ALDEBARAN)) + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", ucode_pref= ix); + else + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", ucode_prefix); + + r =3D request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (r) + return r; + } + + return 0; +} + static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) { + char ucode_prefix[30]; + int r; + + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_= prefix)); + switch (adev->ip_versions[GC_HWIP][0]) { case IP_VERSION(9, 0, 1): case IP_VERSION(9, 1, 0): @@ -1856,6 +1997,9 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct a= mdgpu_device *adev) case IP_VERSION(9, 4, 0): case IP_VERSION(9, 4, 1): case IP_VERSION(9, 4, 2): + r =3D amdgpu_discovery_load_gfx9(adev, ucode_prefix); + if (r) + return r; amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); break; case IP_VERSION(10, 1, 10): diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/am= dgpu/gfx_v9_0.c index f202b45c413c..3d6e6b7d461d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -65,72 +65,6 @@ #define mmGCEA_PROBE_MAP 0x070c #define mmGCEA_PROBE_MAP_BASE_IDX 0 =20 -MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); -MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); -MODULE_FIRMWARE("amdgpu/vega10_me.bin"); -MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); -MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); -MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); -MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); -MODULE_FIRMWARE("amdgpu/vega12_me.bin"); -MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); -MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); -MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); -MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); -MODULE_FIRMWARE("amdgpu/vega20_me.bin"); -MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); -MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); -MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/raven_ce.bin"); -MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); -MODULE_FIRMWARE("amdgpu/raven_me.bin"); -MODULE_FIRMWARE("amdgpu/raven_mec.bin"); -MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); -MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); -MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); -MODULE_FIRMWARE("amdgpu/picasso_me.bin"); -MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); -MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); -MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); -MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); - -MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); -MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); -MODULE_FIRMWARE("amdgpu/raven2_me.bin"); -MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); -MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); -MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); -MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); -MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); -MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); -MODULE_FIRMWARE("amdgpu/renoir_me.bin"); -MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); -MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_me.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin"); -MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin"); - -MODULE_FIRMWARE("amdgpu/aldebaran_mec.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_mec2.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_rlc.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec.bin"); -MODULE_FIRMWARE("amdgpu/aldebaran_sjt_mec2.bin"); - #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 @@ -1253,31 +1187,18 @@ static void gfx_v9_0_check_if_need_gfxoff(struct am= dgpu_device *adev) static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, const char *chip_name) { - char fw_name[30]; int err; =20 - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); - err =3D request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; err =3D amdgpu_ucode_validate(adev->gfx.pfp_fw); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); =20 - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); - err =3D request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; err =3D amdgpu_ucode_validate(adev->gfx.me_fw); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); =20 - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); - err =3D request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err) - goto out; err =3D amdgpu_ucode_validate(adev->gfx.ce_fw); if (err) goto out; @@ -1286,8 +1207,7 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct amdg= pu_device *adev, out: if (err) { dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); + "gfx9: Failed to init firmware\n"); release_firmware(adev->gfx.pfp_fw); adev->gfx.pfp_fw =3D NULL; release_firmware(adev->gfx.me_fw); @@ -1301,36 +1221,11 @@ static int gfx_v9_0_init_cp_gfx_microcode(struct am= dgpu_device *adev, static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, const char *chip_name) { - char fw_name[30]; int err; const struct rlc_firmware_header_v2_0 *rlc_hdr; uint16_t version_major; uint16_t version_minor; - uint32_t smu_version; =20 - /* - * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin - * instead of picasso_rlc.bin. - * Judgment method: - * PCO AM4: revision >=3D 0xC8 && revision <=3D 0xCF - * or revision >=3D 0xD8 && revision <=3D 0xDF - * otherwise is PCO FP5 - */ - if (!strcmp(chip_name, "picasso") && - (((adev->pdev->revision >=3D 0xC8) && (adev->pdev->revision <=3D 0xCF)) = || - ((adev->pdev->revision >=3D 0xD8) && (adev->pdev->revision <=3D 0xDF)))) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); - else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev= , &smu_version) =3D=3D 0) && - (smu_version >=3D 0x41e2b)) - /** - *SMC is loaded by SBIOS on APU and it's able to get the SMU version dire= ctly. - */ - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name= ); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err =3D request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; err =3D amdgpu_ucode_validate(adev->gfx.rlc_fw); if (err) goto out; @@ -1342,8 +1237,7 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_= device *adev, out: if (err) { dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); + "gfx9: Failed to init firmware\n"); release_firmware(adev->gfx.rlc_fw); adev->gfx.rlc_fw =3D NULL; } @@ -1363,17 +1257,8 @@ static bool gfx_v9_0_load_mec2_fw_bin_support(struct= amdgpu_device *adev) static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, const char *chip_name) { - char fw_name[30]; int err; =20 - if (amdgpu_sriov_vf(adev) && (adev->asic_type =3D=3D CHIP_ALDEBARAN)) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); - - err =3D request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; err =3D amdgpu_ucode_validate(adev->gfx.mec_fw); if (err) goto out; @@ -1381,22 +1266,11 @@ static int gfx_v9_0_init_cp_compute_microcode(struc= t amdgpu_device *adev, amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); =20 if (gfx_v9_0_load_mec2_fw_bin_support(adev)) { - if (amdgpu_sriov_vf(adev) && (adev->asic_type =3D=3D CHIP_ALDEBARAN)) - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sjt_mec2.bin", chip_name); - else - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - - err =3D request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); - if (!err) { - err =3D amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; - amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); - amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); - } else { - err =3D 0; - adev->gfx.mec2_fw =3D NULL; - } + err =3D amdgpu_ucode_validate(adev->gfx.mec2_fw); + if (err) + goto out; + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); } else { adev->gfx.mec2_fw_version =3D adev->gfx.mec_fw_version; adev->gfx.mec2_feature_version =3D adev->gfx.mec_feature_version; @@ -1407,8 +1281,7 @@ static int gfx_v9_0_init_cp_compute_microcode(struct = amdgpu_device *adev, gfx_v9_0_check_fw_write_wait(adev); if (err) { dev_err(adev->dev, - "gfx9: Failed to init firmware \"%s\"\n", - fw_name); + "gfx9: Failed to init firmware\n"); release_firmware(adev->gfx.mec_fw); adev->gfx.mec_fw =3D NULL; release_firmware(adev->gfx.mec2_fw); --=20 2.34.1