From nobody Wed Sep 17 01:27:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EF74C4708D for ; Tue, 27 Dec 2022 00:31:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232632AbiL0Aa5 (ORCPT ); Mon, 26 Dec 2022 19:30:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232655AbiL0AaC (ORCPT ); Mon, 26 Dec 2022 19:30:02 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8C0A270A for ; Mon, 26 Dec 2022 16:29:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672100995; x=1703636995; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ba35wqiPwZ1LzOMWrGbZ6/UPey9BiC9eCP+Pk93x5S8=; b=ih8KNlukDsKHZMdppIzuaC83WyoKvunXiIbcFMcuTPnzgGnoJyzbbe7Y OD7+cQ44lb7/5di70irgVQ8cb1emHtV23AkhHVoU817Hfn5fVmRMSGaye p3va+83ltL1ol2yJjiaCKkbuzvq0RgOFrkFNb0p91swLvoKc+NDEXDPby W8kFmhpeE9WRWcblPbdOf/y8I11LYfHP0dYDRovSvhaBgpZhlzORQRnBV r//Uv/8YT43q4I4nC4Un+HE95T2BTmMo4CFze3J7ibQkGWOYnHIZ324d4 Uy/+JSJQhfGQuJDJUC8URAsnlqdnSDtq6TPq/sTnPaqhpX7ZjuRiWqcL+ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10572"; a="322597292" X-IronPort-AV: E=Sophos;i="5.96,277,1665471600"; d="scan'208";a="322597292" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Dec 2022 16:29:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10572"; a="760172251" X-IronPort-AV: E=Sophos;i="5.96,277,1665471600"; d="scan'208";a="760172251" Received: from yyang3-mobl1.ccr.corp.intel.com (HELO yhuang6-mobl2.ccr.corp.intel.com) ([10.254.212.104]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Dec 2022 16:29:51 -0800 From: Huang Ying To: Andrew Morton Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, Huang Ying , Zi Yan , Yang Shi , Baolin Wang , Oscar Salvador , Matthew Wilcox , Bharata B Rao , Alistair Popple , haoxin Subject: [PATCH 8/8] migrate_pages: batch flushing TLB Date: Tue, 27 Dec 2022 08:28:59 +0800 Message-Id: <20221227002859.27740-9-ying.huang@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221227002859.27740-1-ying.huang@intel.com> References: <20221227002859.27740-1-ying.huang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The TLB flushing will cost quite some CPU cycles during the folio migration in some situations. For example, when migrate a folio of a process with multiple active threads that run on multiple CPUs. After batching the _unmap and _move in migrate_pages(), the TLB flushing can be batched easily with the existing TLB flush batching mechanism. This patch implements that. We use the following test case to test the patch. On a 2-socket Intel server, - Run pmbench memory accessing benchmark - Run `migratepages` to migrate pages of pmbench between node 0 and node 1 back and forth. With the patch, the TLB flushing IPI reduces 99.1% during the test and the number of pages migrated successfully per second increases 291.7%. Signed-off-by: "Huang, Ying" Cc: Zi Yan Cc: Yang Shi Cc: Baolin Wang Cc: Oscar Salvador Cc: Matthew Wilcox Cc: Bharata B Rao Cc: Alistair Popple Cc: haoxin --- mm/migrate.c | 4 +++- mm/rmap.c | 20 +++++++++++++++++--- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/mm/migrate.c b/mm/migrate.c index 70a40b8fee1f..d7413164e748 100644 --- a/mm/migrate.c +++ b/mm/migrate.c @@ -1215,7 +1215,7 @@ static int migrate_folio_unmap(new_page_t get_new_pag= e, free_page_t put_new_page /* Establish migration ptes */ VM_BUG_ON_FOLIO(folio_test_anon(src) && !folio_test_ksm(src) && !anon_vma, src); - try_to_migrate(src, 0); + try_to_migrate(src, TTU_BATCH_FLUSH); page_was_mapped =3D 1; } =20 @@ -1732,6 +1732,8 @@ static int migrate_pages_batch(struct list_head *from= , new_page_t get_new_page, stats->nr_thp_failed +=3D thp_retry; stats->nr_failed_pages +=3D nr_retry_pages; move: + try_to_unmap_flush(); + retry =3D 1; for (pass =3D 0; pass < 10 && (retry || large_retry); pass++) { retry =3D 0; diff --git a/mm/rmap.c b/mm/rmap.c index b616870a09be..2e125f3e462e 100644 --- a/mm/rmap.c +++ b/mm/rmap.c @@ -1976,7 +1976,21 @@ static bool try_to_migrate_one(struct folio *folio, = struct vm_area_struct *vma, } else { flush_cache_page(vma, address, pte_pfn(*pvmw.pte)); /* Nuke the page table entry. */ - pteval =3D ptep_clear_flush(vma, address, pvmw.pte); + if (should_defer_flush(mm, flags)) { + /* + * We clear the PTE but do not flush so potentially + * a remote CPU could still be writing to the folio. + * If the entry was previously clean then the + * architecture must guarantee that a clear->dirty + * transition on a cached TLB entry is written through + * and traps if the PTE is unmapped. + */ + pteval =3D ptep_get_and_clear(mm, address, pvmw.pte); + + set_tlb_ubc_flush_pending(mm, pte_dirty(pteval)); + } else { + pteval =3D ptep_clear_flush(vma, address, pvmw.pte); + } } =20 /* Set the dirty flag on the folio now the pte is gone. */ @@ -2148,10 +2162,10 @@ void try_to_migrate(struct folio *folio, enum ttu_f= lags flags) =20 /* * Migration always ignores mlock and only supports TTU_RMAP_LOCKED and - * TTU_SPLIT_HUGE_PMD and TTU_SYNC flags. + * TTU_SPLIT_HUGE_PMD, TTU_SYNC, and TTU_BATCH_FLUSH flags. */ if (WARN_ON_ONCE(flags & ~(TTU_RMAP_LOCKED | TTU_SPLIT_HUGE_PMD | - TTU_SYNC))) + TTU_SYNC | TTU_BATCH_FLUSH))) return; =20 if (folio_is_zone_device(folio) && --=20 2.35.1