From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A42CDC5479D for ; Mon, 9 Jan 2023 15:32:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235292AbjAIPca (ORCPT ); Mon, 9 Jan 2023 10:32:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237232AbjAIPbp (ORCPT ); Mon, 9 Jan 2023 10:31:45 -0500 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F1C68FE7; Mon, 9 Jan 2023 07:30:55 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id E43AC12D9; Mon, 9 Jan 2023 16:30:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673278253; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Pi8DEqJ/gw2sKklo3+qvuIL9iaUr+yK9KADgetTEkBE=; b=s2WVn7RLyGMisKDHznY+P+Vd2K1UWspu+0J39aK/8LhwrLQu5WTkLyhq1bRwSpzO05L+aQ WBWR4gdFzTV581QYoNScl3prKZ6dt822050cEhJtFpL8PZXdrjwzGQdLjh/FLoGvH7smMA 5ZSUs62odnEOk5jvZFJIEsVR/zeVMp61ZnnhLQ0WVZNMwZ7klw5JJKWSGHYS+cpGK2/mRk /DYnxQruw9peBQLRoA6FYUC+QXU8Mi4cGEbuU+TETa7Y8P2E1ofSLFJ0H5uT+1hAIXiSa8 oNpsi6Ihdd7euWbGock/vpHnHLnK3ydrS12mlNEnDAbc+NJa8oqFRF4rUCYN3w== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:41 +0100 Subject: [PATCH net-next v3 01/11] net: mdio: Add dedicated C45 API to MDIO bus drivers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-1-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn Currently C22 and C45 transactions are mixed over a combined API calls which make use of a special bit in the reg address to indicate if a C45 transaction should be performed. This makes it impossible to know if the bus driver actually supports C45. Additionally, many C22 only drivers don't return -EOPNOTSUPP when asked to perform a C45 transaction, they mistaking perform a C22 transaction. This is the first step to cleanly separate C22 from C45. To maintain backwards compatibility until all drivers which are capable of performing C45 are converted to this new API, the helper functions will fall back to the older API if the new API is not supported. Eventually this fallback will be removed. Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle --- drivers/net/phy/mdio_bus.c | 189 +++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/mdio.h | 39 +++++----- include/linux/phy.h | 5 ++ 3 files changed, 214 insertions(+), 19 deletions(-) diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index 1cd604cd1fa1..bde195864c17 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -826,6 +826,100 @@ int __mdiobus_modify_changed(struct mii_bus *bus, int= addr, u32 regnum, } EXPORT_SYMBOL_GPL(__mdiobus_modify_changed); =20 +/** + * __mdiobus_c45_read - Unlocked version of the mdiobus_c45_read function + * @bus: the mii_bus struct + * @addr: the phy address + * @devad: device address to read + * @regnum: register number to read + * + * Read a MDIO bus register. Caller must hold the mdio bus lock. + * + * NOTE: MUST NOT be called from interrupt context. + */ +int __mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnu= m) +{ + int retval; + + lockdep_assert_held_once(&bus->mdio_lock); + + if (bus->read_c45) + retval =3D bus->read_c45(bus, addr, devad, regnum); + else + retval =3D bus->read(bus, addr, mdiobus_c45_addr(devad, regnum)); + + trace_mdio_access(bus, 1, addr, regnum, retval, retval); + mdiobus_stats_acct(&bus->stats[addr], true, retval); + + return retval; +} +EXPORT_SYMBOL(__mdiobus_c45_read); + +/** + * __mdiobus_c45_write - Unlocked version of the mdiobus_write function + * @bus: the mii_bus struct + * @addr: the phy address + * @devad: device address to read + * @regnum: register number to write + * @val: value to write to @regnum + * + * Write a MDIO bus register. Caller must hold the mdio bus lock. + * + * NOTE: MUST NOT be called from interrupt context. + */ +int __mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 regn= um, + u16 val) +{ + int err; + + lockdep_assert_held_once(&bus->mdio_lock); + + if (bus->write_c45) + err =3D bus->write_c45(bus, addr, devad, regnum, val); + else + err =3D bus->write(bus, addr, mdiobus_c45_addr(devad, regnum), + val); + + trace_mdio_access(bus, 0, addr, regnum, val, err); + mdiobus_stats_acct(&bus->stats[addr], false, err); + + return err; +} +EXPORT_SYMBOL(__mdiobus_c45_write); + +/** + * __mdiobus_c45_modify_changed - Unlocked version of the mdiobus_modify f= unction + * @bus: the mii_bus struct + * @addr: the phy address + * @devad: device address to read + * @regnum: register number to modify + * @mask: bit mask of bits to clear + * @set: bit mask of bits to set + * + * Read, modify, and if any change, write the register value back to the + * device. Any error returns a negative number. + * + * NOTE: MUST NOT be called from interrupt context. + */ +static int __mdiobus_c45_modify_changed(struct mii_bus *bus, int addr, + int devad, u32 regnum, u16 mask, + u16 set) +{ + int new, ret; + + ret =3D __mdiobus_c45_read(bus, addr, devad, regnum); + if (ret < 0) + return ret; + + new =3D (ret & ~mask) | set; + if (new =3D=3D ret) + return 0; + + ret =3D __mdiobus_c45_write(bus, addr, devad, regnum, new); + + return ret < 0 ? ret : 1; +} + /** * mdiobus_read_nested - Nested version of the mdiobus_read function * @bus: the mii_bus struct @@ -873,6 +967,29 @@ int mdiobus_read(struct mii_bus *bus, int addr, u32 re= gnum) } EXPORT_SYMBOL(mdiobus_read); =20 +/** + * mdiobus_c45_read - Convenience function for reading a given MII mgmt re= gister + * @bus: the mii_bus struct + * @addr: the phy address + * @devad: device address to read + * @regnum: register number to read + * + * NOTE: MUST NOT be called from interrupt context, + * because the bus read/write functions may wait for an interrupt + * to conclude the operation. + */ +int mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnum) +{ + int retval; + + mutex_lock(&bus->mdio_lock); + retval =3D __mdiobus_c45_read(bus, addr, devad, regnum); + mutex_unlock(&bus->mdio_lock); + + return retval; +} +EXPORT_SYMBOL(mdiobus_c45_read); + /** * mdiobus_write_nested - Nested version of the mdiobus_write function * @bus: the mii_bus struct @@ -922,6 +1039,31 @@ int mdiobus_write(struct mii_bus *bus, int addr, u32 = regnum, u16 val) } EXPORT_SYMBOL(mdiobus_write); =20 +/** + * mdiobus_c45_write - Convenience function for writing a given MII mgmt r= egister + * @bus: the mii_bus struct + * @addr: the phy address + * @devad: device address to read + * @regnum: register number to write + * @val: value to write to @regnum + * + * NOTE: MUST NOT be called from interrupt context, + * because the bus read/write functions may wait for an interrupt + * to conclude the operation. + */ +int mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 regnum, + u16 val) +{ + int err; + + mutex_lock(&bus->mdio_lock); + err =3D __mdiobus_c45_write(bus, addr, devad, regnum, val); + mutex_unlock(&bus->mdio_lock); + + return err; +} +EXPORT_SYMBOL(mdiobus_c45_write); + /** * mdiobus_modify - Convenience function for modifying a given mdio device * register @@ -943,6 +1085,30 @@ int mdiobus_modify(struct mii_bus *bus, int addr, u32= regnum, u16 mask, u16 set) } EXPORT_SYMBOL_GPL(mdiobus_modify); =20 +/** + * mdiobus_c45_modify - Convenience function for modifying a given mdio de= vice + * register + * @bus: the mii_bus struct + * @addr: the phy address + * @devad: device address to read + * @regnum: register number to write + * @mask: bit mask of bits to clear + * @set: bit mask of bits to set + */ +int mdiobus_c45_modify(struct mii_bus *bus, int addr, int devad, u32 regnu= m, + u16 mask, u16 set) +{ + int err; + + mutex_lock(&bus->mdio_lock); + err =3D __mdiobus_c45_modify_changed(bus, addr, devad, regnum, + mask, set); + mutex_unlock(&bus->mdio_lock); + + return err < 0 ? err : 0; +} +EXPORT_SYMBOL_GPL(mdiobus_c45_modify); + /** * mdiobus_modify_changed - Convenience function for modifying a given mdio * device register and returning if it changed @@ -965,6 +1131,29 @@ int mdiobus_modify_changed(struct mii_bus *bus, int a= ddr, u32 regnum, } EXPORT_SYMBOL_GPL(mdiobus_modify_changed); =20 +/** + * mdiobus_c45_modify_changed - Convenience function for modifying a given= mdio + * device register and returning if it changed + * @bus: the mii_bus struct + * @addr: the phy address + * @devad: device address to read + * @regnum: register number to write + * @mask: bit mask of bits to clear + * @set: bit mask of bits to set + */ +int mdiobus_c45_modify_changed(struct mii_bus *bus, int devad, int addr, + u32 regnum, u16 mask, u16 set) +{ + int err; + + mutex_lock(&bus->mdio_lock); + err =3D __mdiobus_c45_modify_changed(bus, addr, devad, regnum, mask, set); + mutex_unlock(&bus->mdio_lock); + + return err; +} +EXPORT_SYMBOL_GPL(mdiobus_c45_modify_changed); + /** * mdio_bus_match - determine if given MDIO driver supports the given * MDIO device diff --git a/include/linux/mdio.h b/include/linux/mdio.h index f7fbbf3069e7..1e78c8410b21 100644 --- a/include/linux/mdio.h +++ b/include/linux/mdio.h @@ -423,6 +423,17 @@ int mdiobus_modify(struct mii_bus *bus, int addr, u32 = regnum, u16 mask, u16 set); int mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum, u16 mask, u16 set); +int __mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnu= m); +int mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnum); +int __mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 reg= num, + u16 val); +int mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 regnu= m, + u16 val); +int mdiobus_c45_modify(struct mii_bus *bus, int addr, int devad, u32 regnu= m, + u16 mask, u16 set); + +int mdiobus_c45_modify_changed(struct mii_bus *bus, int addr, int devad, + u32 regnum, u16 mask, u16 set); =20 static inline int mdiodev_read(struct mdio_device *mdiodev, u32 regnum) { @@ -463,29 +474,19 @@ static inline u16 mdiobus_c45_devad(u32 regnum) return FIELD_GET(MII_DEVADDR_C45_MASK, regnum); } =20 -static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int d= evad, - u16 regnum) +static inline int mdiodev_c45_modify(struct mdio_device *mdiodev, int deva= d, + u32 regnum, u16 mask, u16 set) { - return __mdiobus_read(bus, prtad, mdiobus_c45_addr(devad, regnum)); + return mdiobus_c45_modify(mdiodev->bus, mdiodev->addr, devad, regnum, + mask, set); } =20 -static inline int __mdiobus_c45_write(struct mii_bus *bus, int prtad, int = devad, - u16 regnum, u16 val) +static inline int mdiodev_c45_modify_changed(struct mdio_device *mdiodev, + int devad, u32 regnum, u16 mask, + u16 set) { - return __mdiobus_write(bus, prtad, mdiobus_c45_addr(devad, regnum), - val); -} - -static inline int mdiobus_c45_read(struct mii_bus *bus, int prtad, int dev= ad, - u16 regnum) -{ - return mdiobus_read(bus, prtad, mdiobus_c45_addr(devad, regnum)); -} - -static inline int mdiobus_c45_write(struct mii_bus *bus, int prtad, int de= vad, - u16 regnum, u16 val) -{ - return mdiobus_write(bus, prtad, mdiobus_c45_addr(devad, regnum), val); + return mdiobus_c45_modify_changed(mdiodev->bus, mdiodev->addr, devad, + regnum, mask, set); } =20 static inline int mdiodev_c45_read(struct mdio_device *mdiodev, int devad, diff --git a/include/linux/phy.h b/include/linux/phy.h index 6378c997ded5..65844f0a7fb3 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -364,6 +364,11 @@ struct mii_bus { int (*read)(struct mii_bus *bus, int addr, int regnum); /** @write: Perform a write transfer on the bus */ int (*write)(struct mii_bus *bus, int addr, int regnum, u16 val); + /** @read: Perform a C45 read transfer on the bus */ + int (*read_c45)(struct mii_bus *bus, int addr, int devnum, int regnum); + /** @write: Perform a C45 write transfer on the bus */ + int (*write_c45)(struct mii_bus *bus, int addr, int devnum, + int regnum, u16 val); /** @reset: Perform a reset of the bus */ int (*reset)(struct mii_bus *bus); =20 --=20 2.30.2 From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BAC6C54EBD for ; Mon, 9 Jan 2023 15:32:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229684AbjAIPcP (ORCPT ); Mon, 9 Jan 2023 10:32:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237187AbjAIPbo (ORCPT ); Mon, 9 Jan 2023 10:31:44 -0500 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AB5065E2; Mon, 9 Jan 2023 07:30:56 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id C9F2F15CC; Mon, 9 Jan 2023 16:30:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673278254; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+RDMkazwnleO/fGtNxWpy8pqhwNMPSCM9ZW84mCDuiE=; b=qsEmH9XrJ/gPd9gPF8FJEUHIsI9UnJrp3l36osJeyr5oepbAa3ovWzx7gV/qU4HMWRci8U G1I9V6M8urFgukeuwTORqczyc6U9Ic/PTud2II3GFgmc5ThFpqtcKcCTRcb8dErgLn59tg WTXjhEWPmGx9QPab7pkiuizzC+FjF5ZuWh0E0RB4EObTB5cRsKzho6b2rUzrKXqPxOxVxI SdJrapc0y/QC5wAozScgIg7p46KjnnVdFjh0lm3vlM26VHD7Q8c8T4OSBk2dHzrTHo8aTF Xh6xjXJ0MtBzryAvymHpaw/ZHJwCrgAtzXhNeSxOXFcTQ2taolyLB7+mYZkwWA== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:42 +0100 Subject: [PATCH net-next v3 02/11] net: pcs: pcs-xpcs: Use C45 MDIO API MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-2-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn Convert the PCS-XPCS driver to make use of the C45 MDIO bus API for modify_change(). Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli --- v2: - [al] new patch --- drivers/net/pcs/pcs-xpcs.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index f6a038a1d51e..bc428a816719 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -199,9 +199,7 @@ int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, = u16 val) static int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set) { - u32 reg_addr =3D mdiobus_c45_addr(dev, reg); - - return mdiodev_modify_changed(xpcs->mdiodev, reg_addr, mask, set); + return mdiodev_c45_modify_changed(xpcs->mdiodev, dev, reg, mask, set); } =20 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg) --=20 2.30.2 From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2136C5479D for ; Mon, 9 Jan 2023 15:32:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237184AbjAIPcU (ORCPT ); Mon, 9 Jan 2023 10:32:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237198AbjAIPbo (ORCPT ); Mon, 9 Jan 2023 10:31:44 -0500 Received: from mail.3ffe.de (0001.3ffe.de [159.69.201.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5A968FEA; Mon, 9 Jan 2023 07:30:56 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 956E51648; Mon, 9 Jan 2023 16:30:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673278254; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PGv46D7gQHbV4r2vFEsGvofuAnLH9RGfLHYlLw3z8As=; b=PEgilRI8e8JgdbuJQlHSPKC7r/+jM46S7CttuPFSSJawqdOtgJyWhQdqSpjc8umRy7gM20 kuLjsvumC9haW/kVQpCk5ytFhfPC5x3fT6OmUlYEhyHapN/wtI4W3pJBwjCVfwQMg3S4az O/R18+9lE3qitUNvrdOuZLWpBllChpF7m2J3BeDiweuvsbmNAgmCTu9wbs8SVq2QNAYKVp nHf7K7xdPsWLQilsfn67AhFXl1KDYorglkatvcyicKqJ0Imn40zokcPU4IhK9PPrxVtJOh lF3zavJWb/CV29dp/1kCYdmI/CDhu/licg2Tuv3oo5uwjcTIekVmJHwYljnppQ== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:43 +0100 Subject: [PATCH net-next v3 03/11] net: mdio: mdiobus_register: update validation test MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-3-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn Now that C45 uses its own read/write methods, the validation performed when a bus is registers needs updating. All combinations of C22 and C45 are supported, but both read and write methods must be provided, read only busses are not supported etc. Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle --- v2: - [al] be consistent with other checks - [mw] make the test a bit easier to read v3: - [mw] use the original validation test style again but with double negation --- drivers/net/phy/mdio_bus.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index bde195864c17..c992a9fd8b01 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -526,8 +526,15 @@ int __mdiobus_register(struct mii_bus *bus, struct mod= ule *owner) int i, err; struct gpio_desc *gpiod; =20 - if (NULL =3D=3D bus || NULL =3D=3D bus->name || - NULL =3D=3D bus->read || NULL =3D=3D bus->write) + if (!bus || !bus->name) + return -EINVAL; + + /* An access method always needs both read and write operations */ + if (!!bus->read !=3D !!bus->write || !!bus->read_c45 !=3D !!bus->write_c4= 5) + return -EINVAL; + + /* At least one method is mandatory */ + if (!bus->read && !bus->read_c45) return -EINVAL; =20 if (bus->parent && bus->parent->of_node) --=20 2.30.2 From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFE1CC5479D for ; Mon, 9 Jan 2023 15:32:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237198AbjAIPc0 (ORCPT ); Mon, 9 Jan 2023 10:32:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237225AbjAIPbp (ORCPT ); Mon, 9 Jan 2023 10:31:45 -0500 Received: from mail.3ffe.de (0001.3ffe.de [159.69.201.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 594D79598; Mon, 9 Jan 2023 07:30:57 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 0282E1654; Mon, 9 Jan 2023 16:30:55 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673278255; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cwldWyFf7CaFTxQBOBymigKCBxPFmfPQFSYXECFA1MQ=; b=oBe/wDiEGzYu9Fc30RDGqfOtePnx+5N67Jc8XWAwViJATJbP5JciHihYt08LZ2CPnqoGXm uZArpFXb8LGFjfjAjXXX7S79M2PS+79KJbqSZO69qsWKd3bzRrrLYAYIXYg6ql+KNj6eYf QFLV/7qysP76I17N9ZXUkpM8Co/fADHz8zTv8pRK0+sadsWUa23hOO8F8/TFqbhkDxEDNV Kh4IJzK9xvXaw84ecISSaMUBh90vtEkIuwjqMygFfeNX7aQTRJKU3bGSi62Qh3a0YIRJXQ PD2iEEB36IH2lBcrduXuSgnBMlXDpiUEHLj2BemVjPRj+aiM8jY7HGIZ/J1pvg== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:44 +0100 Subject: [PATCH net-next v3 04/11] net: mdio: C22 is now optional, EOPNOTSUPP if not provided MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-4-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn When performing a C22 operation, check that the bus driver actually provides the methods, and return -EOPNOTSUPP if not. C45 only busses do exist, and in future their C22 methods will be NULL. Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle --- drivers/net/phy/mdio_bus.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index c992a9fd8b01..f71ba6ab85a7 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -766,7 +766,10 @@ int __mdiobus_read(struct mii_bus *bus, int addr, u32 = regnum) =20 lockdep_assert_held_once(&bus->mdio_lock); =20 - retval =3D bus->read(bus, addr, regnum); + if (bus->read) + retval =3D bus->read(bus, addr, regnum); + else + retval =3D -EOPNOTSUPP; =20 trace_mdio_access(bus, 1, addr, regnum, retval, retval); mdiobus_stats_acct(&bus->stats[addr], true, retval); @@ -792,7 +795,10 @@ int __mdiobus_write(struct mii_bus *bus, int addr, u32= regnum, u16 val) =20 lockdep_assert_held_once(&bus->mdio_lock); =20 - err =3D bus->write(bus, addr, regnum, val); + if (bus->write) + err =3D bus->write(bus, addr, regnum, val); + else + err =3D -EOPNOTSUPP; =20 trace_mdio_access(bus, 0, addr, regnum, val, err); mdiobus_stats_acct(&bus->stats[addr], false, err); --=20 2.30.2 From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B267AC54EBD for ; Mon, 9 Jan 2023 15:32:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230117AbjAIPcq (ORCPT ); Mon, 9 Jan 2023 10:32:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237165AbjAIPbu (ORCPT ); Mon, 9 Jan 2023 10:31:50 -0500 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 867151C12F; Mon, 9 Jan 2023 07:31:07 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 9C6CD16AB; Mon, 9 Jan 2023 16:30:55 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673278255; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EEZ/v6UcgF8jAd9Bq5O3tQtWCx116rW0omeP9KEiKw0=; b=Bs1T9rGnPcNDWGuFneTdy9igWqlryNH1KCei2Uj5Hkn+hyn/4RcpTKfU5FxN+9mkG0cItk oDcds7yka4Lo+6kYx8uuPk4A0MDiBqmXlj/ZUA3vClyZzU5J3kR71Ok9e9N03qilXOsPSP ARccQ562l4Dldsb2GNPyUmNozYRDv86gZoQLd0nDdlQTarGJfWAz3OSk2BxATqry9WUcA8 Byq3GMfp/V4KZ2J5A1+8REH//6yOfOgOlitmD775vxeXssp3hnJjUhwBEUxXKu5Ch6GHeu /63A9MmC2yeADSKKXUhbO+Fj8KVunDK4Gil1rRpugZ1ahPqyNpa1kshAACvF9Q== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:45 +0100 Subject: [PATCH net-next v3 05/11] net: mdio: Move mdiobus_c45_addr() next to users MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-5-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn Now that mdiobus_c45_addr() is only used within the MDIO code during fallback, move the function next to its only users. This function should not be used any more in drivers, the c45 helpers should be used in its place, so hiding it away will prevent any new users from being added. Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle --- drivers/net/phy/mdio_bus.c | 5 +++++ include/linux/mdio.h | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index f71ba6ab85a7..522cbe6a0b23 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -839,6 +839,11 @@ int __mdiobus_modify_changed(struct mii_bus *bus, int = addr, u32 regnum, } EXPORT_SYMBOL_GPL(__mdiobus_modify_changed); =20 +static u32 mdiobus_c45_addr(int devad, u16 regnum) +{ + return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; +} + /** * __mdiobus_c45_read - Unlocked version of the mdiobus_c45_read function * @bus: the mii_bus struct diff --git a/include/linux/mdio.h b/include/linux/mdio.h index 1e78c8410b21..97b49765e8b5 100644 --- a/include/linux/mdio.h +++ b/include/linux/mdio.h @@ -459,11 +459,6 @@ static inline int mdiodev_modify_changed(struct mdio_d= evice *mdiodev, mask, set); } =20 -static inline u32 mdiobus_c45_addr(int devad, u16 regnum) -{ - return MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum; -} - static inline u16 mdiobus_c45_regad(u32 regnum) { return FIELD_GET(MII_REGADDR_C45_MASK, regnum); --=20 2.30.2 From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D301C678D6 for ; Mon, 9 Jan 2023 15:32:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230351AbjAIPcv (ORCPT ); Mon, 9 Jan 2023 10:32:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237248AbjAIPbu (ORCPT ); Mon, 9 Jan 2023 10:31:50 -0500 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 894111C928; Mon, 9 Jan 2023 07:31:07 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 3D4E916CB; Mon, 9 Jan 2023 16:30:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673278256; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=30U39rkn3NsllRMFJKBG4fYOK4HMY172wdjUq7ytbv8=; b=pT22KBCTLM3XX5LScUwcLYLOcXFhYcaua9OjUFM9KTzG5b9oF2XaE/bNaMN0WTjQQWPb3R 66VicPplaGBDXl8Hd8H6FdPdUjvcyAf8ICcPKtRtxj3aWvxOyydb6aFbNo/kMNlDKXp4v4 Oc9+R649kS9zGiA3DJ0NDS9kkwLYhSB44vaiYa/PNHB495kFNJakiPR6SDyQVqBsjRvgP3 1He/ngtweTOLe7TXNdxqT03SwGAAqQEUo7zBaHZvCeMh6eQxk9I595ZXIWY4GsMoMrf5Bb J8cHZ8ZugHZoUCSHUchuJvRrQB28lVVImGgQz7HQYEN7SvBLMoWLlUDPaM9dCA== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:46 +0100 Subject: [PATCH net-next v3 06/11] net: mdio: mdio-bitbang: Separate C22 and C45 transactions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-6-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn The bitbbanging bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new driver API calls. The SH Ethernet driver places wrappers around these functions. In order to not break boards which might be using C45, add similar wrappers for C45 operations. Reviewed-by: Geert Uytterhoeven Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle --- v3: - [mw] Also apply the changes to davinci-mdio. This was missing in v2. --- drivers/net/ethernet/renesas/sh_eth.c | 37 +++++++++++++--- drivers/net/ethernet/ti/davinci_mdio.c | 50 ++++++++++++++++++---- drivers/net/mdio/mdio-bitbang.c | 77 +++++++++++++++++++++++-------= ---- include/linux/mdio-bitbang.h | 6 ++- 4 files changed, 130 insertions(+), 40 deletions(-) diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/r= enesas/sh_eth.c index 71a499113308..ed17163d7811 100644 --- a/drivers/net/ethernet/renesas/sh_eth.c +++ b/drivers/net/ethernet/renesas/sh_eth.c @@ -3044,23 +3044,46 @@ static int sh_mdio_release(struct sh_eth_private *m= dp) return 0; } =20 -static int sh_mdiobb_read(struct mii_bus *bus, int phy, int reg) +static int sh_mdiobb_read_c22(struct mii_bus *bus, int phy, int reg) { int res; =20 pm_runtime_get_sync(bus->parent); - res =3D mdiobb_read(bus, phy, reg); + res =3D mdiobb_read_c22(bus, phy, reg); pm_runtime_put(bus->parent); =20 return res; } =20 -static int sh_mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) +static int sh_mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, u16 = val) { int res; =20 pm_runtime_get_sync(bus->parent); - res =3D mdiobb_write(bus, phy, reg, val); + res =3D mdiobb_write_c22(bus, phy, reg, val); + pm_runtime_put(bus->parent); + + return res; +} + +static int sh_mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, int= reg) +{ + int res; + + pm_runtime_get_sync(bus->parent); + res =3D mdiobb_read_c45(bus, phy, devad, reg); + pm_runtime_put(bus->parent); + + return res; +} + +static int sh_mdiobb_write_c45(struct mii_bus *bus, int phy, int devad, + int reg, u16 val) +{ + int res; + + pm_runtime_get_sync(bus->parent); + res =3D mdiobb_write_c45(bus, phy, devad, reg, val); pm_runtime_put(bus->parent); =20 return res; @@ -3091,8 +3114,10 @@ static int sh_mdio_init(struct sh_eth_private *mdp, return -ENOMEM; =20 /* Wrap accessors with Runtime PM-aware ops */ - mdp->mii_bus->read =3D sh_mdiobb_read; - mdp->mii_bus->write =3D sh_mdiobb_write; + mdp->mii_bus->read =3D sh_mdiobb_read_c22; + mdp->mii_bus->write =3D sh_mdiobb_write_c22; + mdp->mii_bus->read_c45 =3D sh_mdiobb_read_c45; + mdp->mii_bus->write_c45 =3D sh_mdiobb_write_c45; =20 /* Hook up MII support for ethtool */ mdp->mii_bus->name =3D "sh_mii"; diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/= ti/davinci_mdio.c index 946b9753ccfb..23169e36a3d4 100644 --- a/drivers/net/ethernet/ti/davinci_mdio.c +++ b/drivers/net/ethernet/ti/davinci_mdio.c @@ -225,7 +225,7 @@ static int davinci_get_mdio_data(struct mdiobb_ctrl *ct= rl) return test_bit(MDIO_PIN, ®); } =20 -static int davinci_mdiobb_read(struct mii_bus *bus, int phy, int reg) +static int davinci_mdiobb_read_c22(struct mii_bus *bus, int phy, int reg) { int ret; =20 @@ -233,7 +233,7 @@ static int davinci_mdiobb_read(struct mii_bus *bus, int= phy, int reg) if (ret < 0) return ret; =20 - ret =3D mdiobb_read(bus, phy, reg); + ret =3D mdiobb_read_c22(bus, phy, reg); =20 pm_runtime_mark_last_busy(bus->parent); pm_runtime_put_autosuspend(bus->parent); @@ -241,8 +241,8 @@ static int davinci_mdiobb_read(struct mii_bus *bus, int= phy, int reg) return ret; } =20 -static int davinci_mdiobb_write(struct mii_bus *bus, int phy, int reg, - u16 val) +static int davinci_mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, + u16 val) { int ret; =20 @@ -250,7 +250,41 @@ static int davinci_mdiobb_write(struct mii_bus *bus, i= nt phy, int reg, if (ret < 0) return ret; =20 - ret =3D mdiobb_write(bus, phy, reg, val); + ret =3D mdiobb_write_c22(bus, phy, reg, val); + + pm_runtime_mark_last_busy(bus->parent); + pm_runtime_put_autosuspend(bus->parent); + + return ret; +} + +static int davinci_mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, + int reg) +{ + int ret; + + ret =3D pm_runtime_resume_and_get(bus->parent); + if (ret < 0) + return ret; + + ret =3D mdiobb_read_c45(bus, phy, devad, reg); + + pm_runtime_mark_last_busy(bus->parent); + pm_runtime_put_autosuspend(bus->parent); + + return ret; +} + +static int davinci_mdiobb_write_c45(struct mii_bus *bus, int phy, int deva= d, + int reg, u16 val) +{ + int ret; + + ret =3D pm_runtime_resume_and_get(bus->parent); + if (ret < 0) + return ret; + + ret =3D mdiobb_write_c45(bus, phy, devad, reg, val); =20 pm_runtime_mark_last_busy(bus->parent); pm_runtime_put_autosuspend(bus->parent); @@ -573,8 +607,10 @@ static int davinci_mdio_probe(struct platform_device *= pdev) data->bus->name =3D dev_name(dev); =20 if (data->manual_mode) { - data->bus->read =3D davinci_mdiobb_read; - data->bus->write =3D davinci_mdiobb_write; + data->bus->read =3D davinci_mdiobb_read_c22; + data->bus->write =3D davinci_mdiobb_write_c22; + data->bus->read_c45 =3D davinci_mdiobb_read_c45; + data->bus->write_c45 =3D davinci_mdiobb_write_c45; data->bus->reset =3D davinci_mdiobb_reset; =20 dev_info(dev, "Configuring MDIO in manual mode\n"); diff --git a/drivers/net/mdio/mdio-bitbang.c b/drivers/net/mdio/mdio-bitban= g.c index 07609114a26b..b83932562be2 100644 --- a/drivers/net/mdio/mdio-bitbang.c +++ b/drivers/net/mdio/mdio-bitbang.c @@ -127,14 +127,12 @@ static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int = op, u8 phy, u8 reg) =20 /* In clause 45 mode all commands are prefixed by MDIO_ADDR to specify the lower 16 bits of the 21 bit address. This transfer is done identically = to a - MDIO_WRITE except for a different code. To enable clause 45 mode or - MII_ADDR_C45 into the address. Theoretically clause 45 and normal devic= es - can exist on the same bus. Normal devices should ignore the MDIO_ADDR + MDIO_WRITE except for a different code. Theoretically clause 45 and nor= mal + devices can exist on the same bus. Normal devices should ignore the MDI= O_ADDR phase. */ -static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr) +static void mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, int dev_add= r, + int reg) { - unsigned int dev_addr =3D (addr >> 16) & 0x1F; - unsigned int reg =3D addr & 0xFFFF; mdiobb_cmd(ctrl, MDIO_C45_ADDR, phy, dev_addr); =20 /* send the turnaround (10) */ @@ -145,21 +143,13 @@ static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, = int phy, u32 addr) =20 ctrl->ops->set_mdio_dir(ctrl, 0); mdiobb_get_bit(ctrl); - - return dev_addr; } =20 -int mdiobb_read(struct mii_bus *bus, int phy, int reg) +static int mdiobb_read_common(struct mii_bus *bus, int phy) { struct mdiobb_ctrl *ctrl =3D bus->priv; int ret, i; =20 - if (reg & MII_ADDR_C45) { - reg =3D mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); - } else - mdiobb_cmd(ctrl, ctrl->op_c22_read, phy, reg); - ctrl->ops->set_mdio_dir(ctrl, 0); =20 /* check the turnaround bit: the PHY should be driving it to zero, if this @@ -180,17 +170,31 @@ int mdiobb_read(struct mii_bus *bus, int phy, int reg) mdiobb_get_bit(ctrl); return ret; } -EXPORT_SYMBOL(mdiobb_read); =20 -int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val) +int mdiobb_read_c22(struct mii_bus *bus, int phy, int reg) { struct mdiobb_ctrl *ctrl =3D bus->priv; =20 - if (reg & MII_ADDR_C45) { - reg =3D mdiobb_cmd_addr(ctrl, phy, reg); - mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); - } else - mdiobb_cmd(ctrl, ctrl->op_c22_write, phy, reg); + mdiobb_cmd(ctrl, ctrl->op_c22_read, phy, reg); + + return mdiobb_read_common(bus, phy); +} +EXPORT_SYMBOL(mdiobb_read_c22); + +int mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, int reg) +{ + struct mdiobb_ctrl *ctrl =3D bus->priv; + + mdiobb_cmd_addr(ctrl, phy, devad, reg); + mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); + + return mdiobb_read_common(bus, phy); +} +EXPORT_SYMBOL(mdiobb_read_c45); + +static int mdiobb_write_common(struct mii_bus *bus, u16 val) +{ + struct mdiobb_ctrl *ctrl =3D bus->priv; =20 /* send the turnaround (10) */ mdiobb_send_bit(ctrl, 1); @@ -202,7 +206,27 @@ int mdiobb_write(struct mii_bus *bus, int phy, int reg= , u16 val) mdiobb_get_bit(ctrl); return 0; } -EXPORT_SYMBOL(mdiobb_write); + +int mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, u16 val) +{ + struct mdiobb_ctrl *ctrl =3D bus->priv; + + mdiobb_cmd(ctrl, ctrl->op_c22_write, phy, reg); + + return mdiobb_write_common(bus, val); +} +EXPORT_SYMBOL(mdiobb_write_c22); + +int mdiobb_write_c45(struct mii_bus *bus, int phy, int devad, int reg, u16= val) +{ + struct mdiobb_ctrl *ctrl =3D bus->priv; + + mdiobb_cmd_addr(ctrl, phy, devad, reg); + mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); + + return mdiobb_write_common(bus, val); +} +EXPORT_SYMBOL(mdiobb_write_c45); =20 struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl) { @@ -214,8 +238,11 @@ struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl = *ctrl) =20 __module_get(ctrl->ops->owner); =20 - bus->read =3D mdiobb_read; - bus->write =3D mdiobb_write; + bus->read =3D mdiobb_read_c22; + bus->write =3D mdiobb_write_c22; + bus->read_c45 =3D mdiobb_read_c45; + bus->write_c45 =3D mdiobb_write_c45; + bus->priv =3D ctrl; if (!ctrl->override_op_c22) { ctrl->op_c22_read =3D MDIO_READ; diff --git a/include/linux/mdio-bitbang.h b/include/linux/mdio-bitbang.h index 373630fe5c28..cffabdbce075 100644 --- a/include/linux/mdio-bitbang.h +++ b/include/linux/mdio-bitbang.h @@ -38,8 +38,10 @@ struct mdiobb_ctrl { u8 op_c22_write; }; =20 -int mdiobb_read(struct mii_bus *bus, int phy, int reg); -int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val); +int mdiobb_read_c22(struct mii_bus *bus, int phy, int reg); +int mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, u16 val); +int mdiobb_read_c45(struct mii_bus *bus, int devad, int phy, int reg); +int mdiobb_write_c45(struct mii_bus *bus, int devad, int phy, int reg, u16= val); =20 /* The returned bus is not yet registered with the phy layer. */ struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl); --=20 2.30.2 From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29D09C61DB3 for ; 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bh=Lgn0fUyj9IFSMk8AaMRWHgs4+wjSuyxk0Wk78bhVnA0=; b=paHoMYp5QyTdFJmmJGlkyXxyx1kT7mnZo4KsGjYw673zA4PozBqwyJfHLfMUDMeyv98ELr xmptzo+6SEGjSibLaBQj4m+FO+HdVMUhJiS19ZDemTrPStFuuEo3TKrf9iCCypPs+zIn6x aPA3K6eGXZajQEi1AZWWZM7oj4qeoc786ugIgP2xji+EKZ2w7DVNirDKl0NJ+npLxKv6qR 3byRLnvcqXoxg2/tawbXmbt+oBwczg81pRjk4sz/5jOe/16WZv4Qfl4oljyNCHhFlCxme1 +YXfZQYmFv9eoVubcaixqiWW1+X2D9Y+83Dtp7qmXhatDjOfdIRIukTHqw6n+g== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:47 +0100 Subject: [PATCH net-next v3 07/11] net: mdio: mvmdio: Convert XSMI bus to new API MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-7-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn The marvell MDIO driver supports two different hardware blocks. The XSMI block is C45 only. Convert this block to the new API, and only populate the c45 calls in the bus structure. Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle --- drivers/net/ethernet/marvell/mvmdio.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvmdio.c b/drivers/net/ethernet/m= arvell/mvmdio.c index ef878973b859..2d654a40af13 100644 --- a/drivers/net/ethernet/marvell/mvmdio.c +++ b/drivers/net/ethernet/marvell/mvmdio.c @@ -204,21 +204,17 @@ static const struct orion_mdio_ops orion_mdio_xsmi_op= s =3D { .poll_interval_max =3D MVMDIO_XSMI_POLL_INTERVAL_MAX, }; =20 -static int orion_mdio_xsmi_read(struct mii_bus *bus, int mii_id, - int regnum) +static int orion_mdio_xsmi_read_c45(struct mii_bus *bus, int mii_id, + int dev_addr, int regnum) { struct orion_mdio_dev *dev =3D bus->priv; - u16 dev_addr =3D (regnum >> 16) & GENMASK(4, 0); int ret; =20 - if (!(regnum & MII_ADDR_C45)) - return -EOPNOTSUPP; - ret =3D orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus); if (ret < 0) return ret; =20 - writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG); + writel(regnum, dev->regs + MVMDIO_XSMI_ADDR_REG); writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) | (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) | MVMDIO_XSMI_READ_OPERATION, @@ -237,21 +233,17 @@ static int orion_mdio_xsmi_read(struct mii_bus *bus, = int mii_id, return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0); } =20 -static int orion_mdio_xsmi_write(struct mii_bus *bus, int mii_id, - int regnum, u16 value) +static int orion_mdio_xsmi_write_c45(struct mii_bus *bus, int mii_id, + int dev_addr, int regnum, u16 value) { struct orion_mdio_dev *dev =3D bus->priv; - u16 dev_addr =3D (regnum >> 16) & GENMASK(4, 0); int ret; =20 - if (!(regnum & MII_ADDR_C45)) - return -EOPNOTSUPP; - ret =3D orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus); if (ret < 0) return ret; =20 - writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG); + writel(regnum, dev->regs + MVMDIO_XSMI_ADDR_REG); writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) | (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) | MVMDIO_XSMI_WRITE_OPERATION | value, @@ -302,8 +294,8 @@ static int orion_mdio_probe(struct platform_device *pde= v) bus->write =3D orion_mdio_smi_write; break; case BUS_TYPE_XSMI: - bus->read =3D orion_mdio_xsmi_read; - bus->write =3D orion_mdio_xsmi_write; + bus->read_c45 =3D orion_mdio_xsmi_read_c45; + bus->write_c45 =3D orion_mdio_xsmi_write_c45; break; } =20 --=20 2.30.2 From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CD26C54EBD for ; Mon, 9 Jan 2023 15:33:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229649AbjAIPdI (ORCPT ); Mon, 9 Jan 2023 10:33:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237251AbjAIPbu (ORCPT ); Mon, 9 Jan 2023 10:31:50 -0500 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C4141EC75; Mon, 9 Jan 2023 07:31:07 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id EB74118D8; Mon, 9 Jan 2023 16:30:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673278257; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hiQtbjr1MuOIadudcSBQhGvcT/hBXRIhqkSXGDXJPIo=; b=x23FRf2u9HfAfVFtarmaIOkyQ4mbzjmqiVXL6KW6UrcYg5mixeDYZAJ+R4KLfpQk5m44c4 +j3KIuImPXWUdFvV0eDTZt2/M9difs2f19yL1+SOSj00FQJUgZdSb80Mz6C5TgdaboLdzC 8Mpj1ZHw2ALLfqq2NtWW+QjmWZlr66n75loFWcrfi8ceddmWqxTR/M/aM6DUlBEwZAdn/Z xEMLUp9P+KSknWY+pZCSS8PX0WTL4VM8/UETnELEx0VQccEybpIGBiaWCxhc2g5Y9+JmNV 4AFosfhti3qPd6Os1gaVHlC6EJwAqkAaWHenofimLIXwsEPPDlBY/ruwIKfDKQ== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:48 +0100 Subject: [PATCH net-next v3 08/11] net: mdio: xgmac_mdio: Separate C22 and C45 transactions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-8-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn The xgmac MDIO bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. While at it, remove the misleading comment. According to Vladimir Oltean: - miimcom is a register accessed by fsl_pq_mdio.c, not by xgmac_mdio.c - "device dev" doesn't really refer to anything (maybe "dev_addr"). - I don't understand what is meant by the comment "All PHY configuration has to be done through the TSEC1 MIIM regs". Or rather said, I think I understand, but it is irrelevant to the driver for 2 reasons: * TSEC devices use the fsl_pq_mdio.c driver, not this one * It doesn't matter to this driver whose TSEC registers are used for MDIO access. The driver just works with the registers it's given, which is a concern for the device tree. - barring the above, the rest just describes the MDIO bus API, which is superfluous Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle Tested-by: Vladimir Oltean --- v2: - [al] Move the masking of regnum into the variable declarations - [al] Remove a couple of blank lines v3: - [mw] Remove comment --- drivers/net/ethernet/freescale/xgmac_mdio.c | 148 ++++++++++++++++++++----= ---- 1 file changed, 108 insertions(+), 40 deletions(-) diff --git a/drivers/net/ethernet/freescale/xgmac_mdio.c b/drivers/net/ethe= rnet/freescale/xgmac_mdio.c index d7d39a58cd80..8b5a4cd8ff08 100644 --- a/drivers/net/ethernet/freescale/xgmac_mdio.c +++ b/drivers/net/ethernet/freescale/xgmac_mdio.c @@ -128,30 +128,49 @@ static int xgmac_wait_until_done(struct device *dev, return 0; } =20 -/* - * Write value to the PHY for this device to the register at regnum,waiting - * until the write is done before it returns. All PHY configuration has t= o be - * done through the TSEC1 MIIM regs. - */ -static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u= 16 value) +static int xgmac_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnu= m, + u16 value) { struct mdio_fsl_priv *priv =3D (struct mdio_fsl_priv *)bus->priv; struct tgec_mdio_controller __iomem *regs =3D priv->mdio_base; - uint16_t dev_addr; + bool endian =3D priv->is_little_endian; + u16 dev_addr =3D regnum & 0x1f; u32 mdio_ctl, mdio_stat; int ret; + + mdio_stat =3D xgmac_read32(®s->mdio_stat, endian); + mdio_stat &=3D ~MDIO_STAT_ENC; + xgmac_write32(mdio_stat, ®s->mdio_stat, endian); + + ret =3D xgmac_wait_until_free(&bus->dev, regs, endian); + if (ret) + return ret; + + /* Set the port and dev addr */ + mdio_ctl =3D MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); + xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian); + + /* Write the value to the register */ + xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian); + + ret =3D xgmac_wait_until_done(&bus->dev, regs, endian); + if (ret) + return ret; + + return 0; +} + +static int xgmac_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_a= ddr, + int regnum, u16 value) +{ + struct mdio_fsl_priv *priv =3D (struct mdio_fsl_priv *)bus->priv; + struct tgec_mdio_controller __iomem *regs =3D priv->mdio_base; bool endian =3D priv->is_little_endian; + u32 mdio_ctl, mdio_stat; + int ret; =20 mdio_stat =3D xgmac_read32(®s->mdio_stat, endian); - if (regnum & MII_ADDR_C45) { - /* Clause 45 (ie 10G) */ - dev_addr =3D (regnum >> 16) & 0x1f; - mdio_stat |=3D MDIO_STAT_ENC; - } else { - /* Clause 22 (ie 1G) */ - dev_addr =3D regnum & 0x1f; - mdio_stat &=3D ~MDIO_STAT_ENC; - } + mdio_stat |=3D MDIO_STAT_ENC; =20 xgmac_write32(mdio_stat, ®s->mdio_stat, endian); =20 @@ -164,13 +183,11 @@ static int xgmac_mdio_write(struct mii_bus *bus, int = phy_id, int regnum, u16 val xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian); =20 /* Set the register address */ - if (regnum & MII_ADDR_C45) { - xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian); + xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian); =20 - ret =3D xgmac_wait_until_free(&bus->dev, regs, endian); - if (ret) - return ret; - } + ret =3D xgmac_wait_until_free(&bus->dev, regs, endian); + if (ret) + return ret; =20 /* Write the value to the register */ xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian); @@ -182,31 +199,82 @@ static int xgmac_mdio_write(struct mii_bus *bus, int = phy_id, int regnum, u16 val return 0; } =20 -/* - * Reads from register regnum in the PHY for device dev, returning the val= ue. +/* Reads from register regnum in the PHY for device dev, returning the val= ue. * Clears miimcom first. All PHY configuration has to be done through the * TSEC1 MIIM regs. */ -static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum) +static int xgmac_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum) { struct mdio_fsl_priv *priv =3D (struct mdio_fsl_priv *)bus->priv; struct tgec_mdio_controller __iomem *regs =3D priv->mdio_base; + bool endian =3D priv->is_little_endian; + u16 dev_addr =3D regnum & 0x1f; unsigned long flags; - uint16_t dev_addr; uint32_t mdio_stat; uint32_t mdio_ctl; int ret; - bool endian =3D priv->is_little_endian; =20 mdio_stat =3D xgmac_read32(®s->mdio_stat, endian); - if (regnum & MII_ADDR_C45) { - dev_addr =3D (regnum >> 16) & 0x1f; - mdio_stat |=3D MDIO_STAT_ENC; + mdio_stat &=3D ~MDIO_STAT_ENC; + xgmac_write32(mdio_stat, ®s->mdio_stat, endian); + + ret =3D xgmac_wait_until_free(&bus->dev, regs, endian); + if (ret) + return ret; + + /* Set the Port and Device Addrs */ + mdio_ctl =3D MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); + xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian); + + if (priv->has_a009885) + /* Once the operation completes, i.e. MDIO_STAT_BSY clears, we + * must read back the data register within 16 MDC cycles. + */ + local_irq_save(flags); + + /* Initiate the read */ + xgmac_write32(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl, endian); + + ret =3D xgmac_wait_until_done(&bus->dev, regs, endian); + if (ret) + goto irq_restore; + + /* Return all Fs if nothing was there */ + if ((xgmac_read32(®s->mdio_stat, endian) & MDIO_STAT_RD_ER) && + !priv->has_a011043) { + dev_dbg(&bus->dev, + "Error while reading PHY%d reg at %d.%d\n", + phy_id, dev_addr, regnum); + ret =3D 0xffff; } else { - dev_addr =3D regnum & 0x1f; - mdio_stat &=3D ~MDIO_STAT_ENC; + ret =3D xgmac_read32(®s->mdio_data, endian) & 0xffff; + dev_dbg(&bus->dev, "read %04x\n", ret); } =20 +irq_restore: + if (priv->has_a009885) + local_irq_restore(flags); + + return ret; +} + +/* Reads from register regnum in the PHY for device dev, returning the val= ue. + * Clears miimcom first. All PHY configuration has to be done through the + * TSEC1 MIIM regs. + */ +static int xgmac_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_ad= dr, + int regnum) +{ + struct mdio_fsl_priv *priv =3D (struct mdio_fsl_priv *)bus->priv; + struct tgec_mdio_controller __iomem *regs =3D priv->mdio_base; + bool endian =3D priv->is_little_endian; + u32 mdio_stat, mdio_ctl; + unsigned long flags; + int ret; + + mdio_stat =3D xgmac_read32(®s->mdio_stat, endian); + mdio_stat |=3D MDIO_STAT_ENC; + xgmac_write32(mdio_stat, ®s->mdio_stat, endian); =20 ret =3D xgmac_wait_until_free(&bus->dev, regs, endian); @@ -218,13 +286,11 @@ static int xgmac_mdio_read(struct mii_bus *bus, int p= hy_id, int regnum) xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian); =20 /* Set the register address */ - if (regnum & MII_ADDR_C45) { - xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian); + xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian); =20 - ret =3D xgmac_wait_until_free(&bus->dev, regs, endian); - if (ret) - return ret; - } + ret =3D xgmac_wait_until_free(&bus->dev, regs, endian); + if (ret) + return ret; =20 if (priv->has_a009885) /* Once the operation completes, i.e. MDIO_STAT_BSY clears, we @@ -326,8 +392,10 @@ static int xgmac_mdio_probe(struct platform_device *pd= ev) return -ENOMEM; =20 bus->name =3D "Freescale XGMAC MDIO Bus"; - bus->read =3D xgmac_mdio_read; - bus->write =3D xgmac_mdio_write; + bus->read =3D xgmac_mdio_read_c22; + bus->write =3D xgmac_mdio_write_c22; + bus->read_c45 =3D xgmac_mdio_read_c45; + bus->write_c45 =3D xgmac_mdio_write_c45; bus->parent =3D &pdev->dev; bus->probe_capabilities =3D MDIOBUS_C22_C45; snprintf(bus->id, MII_BUS_ID_SIZE, "%pa", &res->start); --=20 2.30.2 From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0253C5479D for ; Mon, 9 Jan 2023 15:33:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237066AbjAIPdE (ORCPT ); Mon, 9 Jan 2023 10:33:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237161AbjAIPbu (ORCPT ); Mon, 9 Jan 2023 10:31:50 -0500 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C3AF1EC69; Mon, 9 Jan 2023 07:31:08 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 9A08118F4; Mon, 9 Jan 2023 16:30:57 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673278257; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6a41x9xkDddn0pKN675NFehAFfkJd5FOLk73tfVYXAs=; b=Z1otKrDv2SQDrlxMVXMdZ+1hmiRsJovlAtyCffdDyrk6DoX/tSjVMtAFL8MymE2O8CdF8C 9Bq51R898qZ8Xo5H0OB2147Oiy6w50KIRVkhRayrgNUfNV6OA3cYkc/FyCsZUr0s516Nch JvupojR10HYlL0Mr4GuXArtVFYmouFz6P3fX2BhC0rxum6JjoE+CQbbVnT5lVLiOP0z8u2 CmBNE5roIjSoVyAj0/jLwktY4p0PFruSq6zRF6BH+lM38TlxhwkyyhZFW37bRmFvm9F3QU 5Tj/ncMnsM5tuAOwRRwry/mrAZozMWSdj4QwjDprvLjFVqpmQCyCKCmPs9ZyEw== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:49 +0100 Subject: [PATCH net-next v3 09/11] net: fec: Separate C22 and C45 transactions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-9-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn The fec MDIO bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle Reviewed-by: Wei Fang --- v2: - [al] Fixup some indentation v3: - [mw] More concise subject --- drivers/net/ethernet/freescale/fec_main.c | 153 ++++++++++++++++++++------= ---- 1 file changed, 103 insertions(+), 50 deletions(-) diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethern= et/freescale/fec_main.c index 644f3c963730..e6238e53940d 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -1987,47 +1987,74 @@ static int fec_enet_mdio_wait(struct fec_enet_priva= te *fep) return ret; } =20 -static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) +static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int reg= num) { struct fec_enet_private *fep =3D bus->priv; struct device *dev =3D &fep->pdev->dev; int ret =3D 0, frame_start, frame_addr, frame_op; - bool is_c45 =3D !!(regnum & MII_ADDR_C45); =20 ret =3D pm_runtime_resume_and_get(dev); if (ret < 0) return ret; =20 - if (is_c45) { - frame_start =3D FEC_MMFR_ST_C45; + /* C22 read */ + frame_op =3D FEC_MMFR_OP_READ; + frame_start =3D FEC_MMFR_ST; + frame_addr =3D regnum; =20 - /* write address */ - frame_addr =3D (regnum >> 16); - writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | - FEC_MMFR_TA | (regnum & 0xFFFF), - fep->hwp + FEC_MII_DATA); + /* start a read op */ + writel(frame_start | frame_op | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | + FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); =20 - /* wait for end of transfer */ - ret =3D fec_enet_mdio_wait(fep); - if (ret) { - netdev_err(fep->netdev, "MDIO address write timeout\n"); - goto out; - } + /* wait for end of transfer */ + ret =3D fec_enet_mdio_wait(fep); + if (ret) { + netdev_err(fep->netdev, "MDIO read timeout\n"); + goto out; + } =20 - frame_op =3D FEC_MMFR_OP_READ_C45; + ret =3D FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); =20 - } else { - /* C22 read */ - frame_op =3D FEC_MMFR_OP_READ; - frame_start =3D FEC_MMFR_ST; - frame_addr =3D regnum; +out: + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return ret; +} + +static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id, + int devad, int regnum) +{ + struct fec_enet_private *fep =3D bus->priv; + struct device *dev =3D &fep->pdev->dev; + int ret =3D 0, frame_start, frame_op; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + frame_start =3D FEC_MMFR_ST_C45; + + /* write address */ + writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | + FEC_MMFR_TA | (regnum & 0xFFFF), + fep->hwp + FEC_MII_DATA); + + /* wait for end of transfer */ + ret =3D fec_enet_mdio_wait(fep); + if (ret) { + netdev_err(fep->netdev, "MDIO address write timeout\n"); + goto out; } =20 + frame_op =3D FEC_MMFR_OP_READ_C45; + /* start a read op */ writel(frame_start | frame_op | - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | - FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | + FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); =20 /* wait for end of transfer */ ret =3D fec_enet_mdio_wait(fep); @@ -2045,45 +2072,69 @@ static int fec_enet_mdio_read(struct mii_bus *bus, = int mii_id, int regnum) return ret; } =20 -static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, - u16 value) +static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int re= gnum, + u16 value) { struct fec_enet_private *fep =3D bus->priv; struct device *dev =3D &fep->pdev->dev; int ret, frame_start, frame_addr; - bool is_c45 =3D !!(regnum & MII_ADDR_C45); =20 ret =3D pm_runtime_resume_and_get(dev); if (ret < 0) return ret; =20 - if (is_c45) { - frame_start =3D FEC_MMFR_ST_C45; + /* C22 write */ + frame_start =3D FEC_MMFR_ST; + frame_addr =3D regnum; =20 - /* write address */ - frame_addr =3D (regnum >> 16); - writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | - FEC_MMFR_TA | (regnum & 0xFFFF), - fep->hwp + FEC_MII_DATA); + /* start a write op */ + writel(frame_start | FEC_MMFR_OP_WRITE | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | + FEC_MMFR_TA | FEC_MMFR_DATA(value), + fep->hwp + FEC_MII_DATA); =20 - /* wait for end of transfer */ - ret =3D fec_enet_mdio_wait(fep); - if (ret) { - netdev_err(fep->netdev, "MDIO address write timeout\n"); - goto out; - } - } else { - /* C22 write */ - frame_start =3D FEC_MMFR_ST; - frame_addr =3D regnum; + /* wait for end of transfer */ + ret =3D fec_enet_mdio_wait(fep); + if (ret) + netdev_err(fep->netdev, "MDIO write timeout\n"); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return ret; +} + +static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id, + int devad, int regnum, u16 value) +{ + struct fec_enet_private *fep =3D bus->priv; + struct device *dev =3D &fep->pdev->dev; + int ret, frame_start; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + frame_start =3D FEC_MMFR_ST_C45; + + /* write address */ + writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | + FEC_MMFR_TA | (regnum & 0xFFFF), + fep->hwp + FEC_MII_DATA); + + /* wait for end of transfer */ + ret =3D fec_enet_mdio_wait(fep); + if (ret) { + netdev_err(fep->netdev, "MDIO address write timeout\n"); + goto out; } =20 /* start a write op */ writel(frame_start | FEC_MMFR_OP_WRITE | - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | - FEC_MMFR_TA | FEC_MMFR_DATA(value), - fep->hwp + FEC_MII_DATA); + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | + FEC_MMFR_TA | FEC_MMFR_DATA(value), + fep->hwp + FEC_MII_DATA); =20 /* wait for end of transfer */ ret =3D fec_enet_mdio_wait(fep); @@ -2381,8 +2432,10 @@ static int fec_enet_mii_init(struct platform_device = *pdev) } =20 fep->mii_bus->name =3D "fec_enet_mii_bus"; - fep->mii_bus->read =3D fec_enet_mdio_read; - fep->mii_bus->write =3D fec_enet_mdio_write; + fep->mii_bus->read =3D fec_enet_mdio_read_c22; + fep->mii_bus->write =3D fec_enet_mdio_write_c22; + fep->mii_bus->read_c45 =3D fec_enet_mdio_read_c45; + fep->mii_bus->write_c45 =3D fec_enet_mdio_write_c45; snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", pdev->name, fep->dev_id + 1); fep->mii_bus->priv =3D fep; --=20 2.30.2 From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2208C5479D for ; Mon, 9 Jan 2023 15:33:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233309AbjAIPc6 (ORCPT ); Mon, 9 Jan 2023 10:32:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237250AbjAIPbu (ORCPT ); Mon, 9 Jan 2023 10:31:50 -0500 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C2E61EC60; Mon, 9 Jan 2023 07:31:07 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 4327319AC; Mon, 9 Jan 2023 16:30:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673278258; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZKZX4lcj+SRBIVWCBH17m7wfPVkw0M5gZtlyN0DyHu8=; b=fCSsUcMXDlZzixTku/Y+ymZofQlKNafLyq8JmlrNVkLWLAFDn3XTwVw51vWElJJug1k+ZF ogtfq1axpzXT0hqcrnwCHvgMMPNP6WaRhHDKAifUTLBQ9/xzr0f3e9ZG7OIot1HTsrmSgF E5JPalqR23Z7h5hF6Y8X91w8h5uzm0ilszAFTB8nCKi7399/rjeup3ijl+Ln9olwa8mlLz G8eav1lUQCAxySB/z8ynkAfTL1UOMuJwT0g37B+DPElKUBlcNAwinuITOjgZ5iTqKJBH5O yYTauzwB5otYjzxH9nQbr9EYkoIuNFAC7oQyhruz9v/Fha75yrSS1p/xWID3jA== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:50 +0100 Subject: [PATCH net-next v3 10/11] net: mdio: add mdiobus_c45_read/write_nested helpers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-10-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn Some DSA devices pass through PHY access to the MDIO bus the switch is on. Add C45 versions of the current C22 helpers for nested accesses to MDIO busses, so that C22 and C45 can be separated in these DSA drivers. Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle --- v2: - [al] new patch --- drivers/net/phy/mdio_bus.c | 55 ++++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/mdio.h | 4 ++++ 2 files changed, 59 insertions(+) diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index 522cbe6a0b23..902e1c88ef58 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -1008,6 +1008,33 @@ int mdiobus_c45_read(struct mii_bus *bus, int addr, = int devad, u32 regnum) } EXPORT_SYMBOL(mdiobus_c45_read); =20 +/** + * mdiobus_c45_read_nested - Nested version of the mdiobus_c45_read functi= on + * @bus: the mii_bus struct + * @addr: the phy address + * @devad: device address to read + * @regnum: register number to read + * + * In case of nested MDIO bus access avoid lockdep false positives by + * using mutex_lock_nested(). + * + * NOTE: MUST NOT be called from interrupt context, + * because the bus read/write functions may wait for an interrupt + * to conclude the operation. + */ +int mdiobus_c45_read_nested(struct mii_bus *bus, int addr, int devad, + u32 regnum) +{ + int retval; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + retval =3D __mdiobus_c45_read(bus, addr, devad, regnum); + mutex_unlock(&bus->mdio_lock); + + return retval; +} +EXPORT_SYMBOL(mdiobus_c45_read_nested); + /** * mdiobus_write_nested - Nested version of the mdiobus_write function * @bus: the mii_bus struct @@ -1082,6 +1109,34 @@ int mdiobus_c45_write(struct mii_bus *bus, int addr,= int devad, u32 regnum, } EXPORT_SYMBOL(mdiobus_c45_write); =20 +/** + * mdiobus_c45_write_nested - Nested version of the mdiobus_c45_write func= tion + * @bus: the mii_bus struct + * @addr: the phy address + * @devad: device address to read + * @regnum: register number to write + * @val: value to write to @regnum + * + * In case of nested MDIO bus access avoid lockdep false positives by + * using mutex_lock_nested(). + * + * NOTE: MUST NOT be called from interrupt context, + * because the bus read/write functions may wait for an interrupt + * to conclude the operation. + */ +int mdiobus_c45_write_nested(struct mii_bus *bus, int addr, int devad, + u32 regnum, u16 val) +{ + int err; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + err =3D __mdiobus_c45_write(bus, addr, devad, regnum, val); + mutex_unlock(&bus->mdio_lock); + + return err; +} +EXPORT_SYMBOL(mdiobus_c45_write_nested); + /** * mdiobus_modify - Convenience function for modifying a given mdio device * register diff --git a/include/linux/mdio.h b/include/linux/mdio.h index 97b49765e8b5..220f3ca8702d 100644 --- a/include/linux/mdio.h +++ b/include/linux/mdio.h @@ -425,10 +425,14 @@ int mdiobus_modify_changed(struct mii_bus *bus, int a= ddr, u32 regnum, u16 mask, u16 set); int __mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnu= m); int mdiobus_c45_read(struct mii_bus *bus, int addr, int devad, u32 regnum); +int mdiobus_c45_read_nested(struct mii_bus *bus, int addr, int devad, + u32 regnum); int __mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 reg= num, u16 val); int mdiobus_c45_write(struct mii_bus *bus, int addr, int devad, u32 regnu= m, u16 val); +int mdiobus_c45_write_nested(struct mii_bus *bus, int addr, int devad, + u32 regnum, u16 val); int mdiobus_c45_modify(struct mii_bus *bus, int addr, int devad, u32 regnu= m, u16 mask, u16 set); =20 --=20 2.30.2 From nobody Thu Nov 14 07:21:24 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19AE9C61DB3 for ; Mon, 9 Jan 2023 15:33:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234962AbjAIPdM (ORCPT ); Mon, 9 Jan 2023 10:33:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237219AbjAIPbv (ORCPT ); Mon, 9 Jan 2023 10:31:51 -0500 Received: from mail.3ffe.de (0001.3ffe.de [IPv6:2a01:4f8:c0c:9d57::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C4F51EC7B; Mon, 9 Jan 2023 07:31:07 -0800 (PST) Received: from mwalle01.sab.local (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.3ffe.de (Postfix) with ESMTPSA id 92F811A11; Mon, 9 Jan 2023 16:30:58 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2022082101; t=1673278258; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HNr/3z9uIVXHH/dsxG51QQYxf6cRktTO5iC8JOqbAFY=; b=kxst7edEMF+wOKsTqNfUehJsnE6pLdTtIL47AAXJVwXj9qedSFIe6zTWJetypt/jNnC55v rCutxCa487leU3NVLm5aPkrACPBbVTVU6jbxFnd13u3mnnRj6J2o64INxBKZ8U3AjRAmn3 e+g7gMRq7fkGpuaAhfpAF47a/1l1ggmzjy24LGq9NawRole2WaD8rSsXScvmom8y4Y6GTF Et8W8EvgUchdQlsUYda3eEzHM9ubtkxd9MVGGsdH6dWq1zlWi1cdT3+E8QHv5ozhRPSSC8 p7FRXd2Qycr7K40IsdclJDuwAHpZo/Pk+aaY3hyETm4k70FWjD3WTif7w9tBbQ== From: Michael Walle Date: Mon, 09 Jan 2023 16:30:51 +0100 Subject: [PATCH net-next v3 11/11] net: dsa: mv88e6xxx: Separate C22 and C45 transactions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221227-v6-2-rc1-c45-seperation-v3-11-ade1deb438da@walle.cc> References: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> In-Reply-To: <20221227-v6-2-rc1-c45-seperation-v3-0-ade1deb438da@walle.cc> To: Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jose Abreu , Sergey Shtylyov , Wei Fang , Shenwei Wang , Clark Wang , NXP Linux Team , Sean Wang , Landen Chao , DENG Qingfang , Florian Fainelli , Vladimir Oltean , Matthias Brugger Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Andrew Lunn , Geert Uytterhoeven , Michael Walle , Vladimir Oltean X-Mailer: b4 0.11.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Lunn The global2 SMI MDIO bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. Update the SERDES code to make use of these new accessors. Signed-off-by: Andrew Lunn Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mv88e6xxx/chip.c | 175 ++++++++++++++++++++++++++------= ---- drivers/net/dsa/mv88e6xxx/chip.h | 7 ++ drivers/net/dsa/mv88e6xxx/global2.c | 66 ++++++++------ drivers/net/dsa/mv88e6xxx/global2.h | 18 ++-- drivers/net/dsa/mv88e6xxx/phy.c | 32 +++++++ drivers/net/dsa/mv88e6xxx/phy.h | 4 + drivers/net/dsa/mv88e6xxx/serdes.c | 8 +- 7 files changed, 225 insertions(+), 85 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/c= hip.c index 242b8b325504..0ff9cd0be217 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -3884,6 +3884,24 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, = int phy, int reg) return err ? err : val; } =20 +static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, + int reg) +{ + struct mv88e6xxx_mdio_bus *mdio_bus =3D bus->priv; + struct mv88e6xxx_chip *chip =3D mdio_bus->chip; + u16 val; + int err; + + if (!chip->info->ops->phy_read_c45) + return -EOPNOTSUPP; + + mv88e6xxx_reg_lock(chip); + err =3D chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); + mv88e6xxx_reg_unlock(chip); + + return err ? err : val; +} + static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16= val) { struct mv88e6xxx_mdio_bus *mdio_bus =3D bus->priv; @@ -3900,6 +3918,23 @@ static int mv88e6xxx_mdio_write(struct mii_bus *bus,= int phy, int reg, u16 val) return err; } =20 +static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int deva= d, + int reg, u16 val) +{ + struct mv88e6xxx_mdio_bus *mdio_bus =3D bus->priv; + struct mv88e6xxx_chip *chip =3D mdio_bus->chip; + int err; + + if (!chip->info->ops->phy_write_c45) + return -EOPNOTSUPP; + + mv88e6xxx_reg_lock(chip); + err =3D chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); + mv88e6xxx_reg_unlock(chip); + + return err; +} + static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, struct device_node *np, bool external) @@ -3938,6 +3973,8 @@ static int mv88e6xxx_mdio_register(struct mv88e6xxx_c= hip *chip, =20 bus->read =3D mv88e6xxx_mdio_read; bus->write =3D mv88e6xxx_mdio_write; + bus->read_c45 =3D mv88e6xxx_mdio_read_c45; + bus->write_c45 =3D mv88e6xxx_mdio_write_c45; bus->parent =3D chip->dev; =20 if (!external) { @@ -4149,8 +4186,10 @@ static const struct mv88e6xxx_ops mv88e6097_ops =3D { .ip_pri_map =3D mv88e6085_g1_ip_pri_map, .irl_init_all =3D mv88e6352_g2_irl_init_all, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6185_port_sync_link, .port_set_speed_duplex =3D mv88e6185_port_set_speed_duplex, @@ -4198,8 +4237,10 @@ static const struct mv88e6xxx_ops mv88e6123_ops =3D { .ip_pri_map =3D mv88e6085_g1_ip_pri_map, .irl_init_all =3D mv88e6352_g2_irl_init_all, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_speed_duplex =3D mv88e6185_port_set_speed_duplex, @@ -4279,8 +4320,10 @@ static const struct mv88e6xxx_ops mv88e6141_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom8, .set_eeprom =3D mv88e6xxx_g2_set_eeprom8, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6390_port_set_rgmii_delay, @@ -4343,8 +4386,10 @@ static const struct mv88e6xxx_ops mv88e6161_ops =3D { .ip_pri_map =3D mv88e6085_g1_ip_pri_map, .irl_init_all =3D mv88e6352_g2_irl_init_all, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_speed_duplex =3D mv88e6185_port_set_speed_duplex, @@ -4426,8 +4471,10 @@ static const struct mv88e6xxx_ops mv88e6171_ops =3D { .ip_pri_map =3D mv88e6085_g1_ip_pri_map, .irl_init_all =3D mv88e6352_g2_irl_init_all, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6352_port_set_rgmii_delay, @@ -4472,8 +4519,10 @@ static const struct mv88e6xxx_ops mv88e6172_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom16, .set_eeprom =3D mv88e6xxx_g2_set_eeprom16, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6352_port_set_rgmii_delay, @@ -4527,8 +4576,10 @@ static const struct mv88e6xxx_ops mv88e6175_ops =3D { .ip_pri_map =3D mv88e6085_g1_ip_pri_map, .irl_init_all =3D mv88e6352_g2_irl_init_all, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6352_port_set_rgmii_delay, @@ -4573,8 +4624,10 @@ static const struct mv88e6xxx_ops mv88e6176_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom16, .set_eeprom =3D mv88e6xxx_g2_set_eeprom16, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6352_port_set_rgmii_delay, @@ -4673,8 +4726,10 @@ static const struct mv88e6xxx_ops mv88e6190_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom8, .set_eeprom =3D mv88e6xxx_g2_set_eeprom8, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6390_port_set_rgmii_delay, @@ -4736,8 +4791,10 @@ static const struct mv88e6xxx_ops mv88e6190x_ops =3D= { .get_eeprom =3D mv88e6xxx_g2_get_eeprom8, .set_eeprom =3D mv88e6xxx_g2_set_eeprom8, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6390_port_set_rgmii_delay, @@ -4799,8 +4856,10 @@ static const struct mv88e6xxx_ops mv88e6191_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom8, .set_eeprom =3D mv88e6xxx_g2_set_eeprom8, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6390_port_set_rgmii_delay, @@ -4862,8 +4921,10 @@ static const struct mv88e6xxx_ops mv88e6240_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom16, .set_eeprom =3D mv88e6xxx_g2_set_eeprom16, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6352_port_set_rgmii_delay, @@ -4925,8 +4986,10 @@ static const struct mv88e6xxx_ops mv88e6250_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom16, .set_eeprom =3D mv88e6xxx_g2_set_eeprom16, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6352_port_set_rgmii_delay, @@ -4964,8 +5027,10 @@ static const struct mv88e6xxx_ops mv88e6290_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom8, .set_eeprom =3D mv88e6xxx_g2_set_eeprom8, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6390_port_set_rgmii_delay, @@ -5029,8 +5094,10 @@ static const struct mv88e6xxx_ops mv88e6320_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom16, .set_eeprom =3D mv88e6xxx_g2_set_eeprom16, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6320_port_set_rgmii_delay, @@ -5074,8 +5141,10 @@ static const struct mv88e6xxx_ops mv88e6321_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom16, .set_eeprom =3D mv88e6xxx_g2_set_eeprom16, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6320_port_set_rgmii_delay, @@ -5117,8 +5186,10 @@ static const struct mv88e6xxx_ops mv88e6341_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom8, .set_eeprom =3D mv88e6xxx_g2_set_eeprom8, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6390_port_set_rgmii_delay, @@ -5183,8 +5254,10 @@ static const struct mv88e6xxx_ops mv88e6350_ops =3D { .ip_pri_map =3D mv88e6085_g1_ip_pri_map, .irl_init_all =3D mv88e6352_g2_irl_init_all, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6352_port_set_rgmii_delay, @@ -5227,8 +5300,10 @@ static const struct mv88e6xxx_ops mv88e6351_ops =3D { .ip_pri_map =3D mv88e6085_g1_ip_pri_map, .irl_init_all =3D mv88e6352_g2_irl_init_all, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6352_port_set_rgmii_delay, @@ -5275,8 +5350,10 @@ static const struct mv88e6xxx_ops mv88e6352_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom16, .set_eeprom =3D mv88e6xxx_g2_set_eeprom16, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6352_port_set_rgmii_delay, @@ -5340,8 +5417,10 @@ static const struct mv88e6xxx_ops mv88e6390_ops =3D { .get_eeprom =3D mv88e6xxx_g2_get_eeprom8, .set_eeprom =3D mv88e6xxx_g2_set_eeprom8, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6390_port_set_rgmii_delay, @@ -5407,8 +5486,10 @@ static const struct mv88e6xxx_ops mv88e6390x_ops =3D= { .get_eeprom =3D mv88e6xxx_g2_get_eeprom8, .set_eeprom =3D mv88e6xxx_g2_set_eeprom8, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6390_port_set_rgmii_delay, @@ -5473,8 +5554,10 @@ static const struct mv88e6xxx_ops mv88e6393x_ops =3D= { .get_eeprom =3D mv88e6xxx_g2_get_eeprom8, .set_eeprom =3D mv88e6xxx_g2_set_eeprom8, .set_switch_mac =3D mv88e6xxx_g2_set_switch_mac, - .phy_read =3D mv88e6xxx_g2_smi_phy_read, - .phy_write =3D mv88e6xxx_g2_smi_phy_write, + .phy_read =3D mv88e6xxx_g2_smi_phy_read_c22, + .phy_write =3D mv88e6xxx_g2_smi_phy_write_c22, + .phy_read_c45 =3D mv88e6xxx_g2_smi_phy_read_c45, + .phy_write_c45 =3D mv88e6xxx_g2_smi_phy_write_c45, .port_set_link =3D mv88e6xxx_port_set_link, .port_sync_link =3D mv88e6xxx_port_sync_link, .port_set_rgmii_delay =3D mv88e6390_port_set_rgmii_delay, diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/c= hip.h index e693154cf803..751bede49942 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -451,6 +451,13 @@ struct mv88e6xxx_ops { struct mii_bus *bus, int addr, int reg, u16 val); =20 + int (*phy_read_c45)(struct mv88e6xxx_chip *chip, + struct mii_bus *bus, + int addr, int devad, int reg, u16 *val); + int (*phy_write_c45)(struct mv88e6xxx_chip *chip, + struct mii_bus *bus, + int addr, int devad, int reg, u16 val); + /* Priority Override Table operations */ int (*pot_clear)(struct mv88e6xxx_chip *chip); =20 diff --git a/drivers/net/dsa/mv88e6xxx/global2.c b/drivers/net/dsa/mv88e6xx= x/global2.c index fa65ecd9cb85..ed3b2f88e783 100644 --- a/drivers/net/dsa/mv88e6xxx/global2.c +++ b/drivers/net/dsa/mv88e6xxx/global2.c @@ -739,20 +739,18 @@ static int mv88e6xxx_g2_smi_phy_read_data_c45(struct = mv88e6xxx_chip *chip, return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data); } =20 -static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, - bool external, int port, int reg, - u16 *data) +static int _mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, + bool external, int port, int devad, + int reg, u16 *data) { - int dev =3D (reg >> 16) & 0x1f; - int addr =3D reg & 0xffff; int err; =20 - err =3D mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev, - addr); + err =3D mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, devad, + reg); if (err) return err; =20 - return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev, + return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, devad, data); } =20 @@ -771,51 +769,65 @@ static int mv88e6xxx_g2_smi_phy_write_data_c45(struct= mv88e6xxx_chip *chip, return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev); } =20 -static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, - bool external, int port, int reg, - u16 data) +static int _mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, + bool external, int port, int devad, + int reg, u16 data) { - int dev =3D (reg >> 16) & 0x1f; - int addr =3D reg & 0xffff; int err; =20 - err =3D mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev, - addr); + err =3D mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, devad, + reg); if (err) return err; =20 - return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev, + return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, devad, data); } =20 -int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus = *bus, - int addr, int reg, u16 *val) +int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip, + struct mii_bus *bus, + int addr, int reg, u16 *val) { struct mv88e6xxx_mdio_bus *mdio_bus =3D bus->priv; bool external =3D mdio_bus->external; =20 - if (reg & MII_ADDR_C45) - return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg, - val); - return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg, val); } =20 -int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus= *bus, - int addr, int reg, u16 val) +int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, + struct mii_bus *bus, int addr, int devad, + int reg, u16 *val) { struct mv88e6xxx_mdio_bus *mdio_bus =3D bus->priv; bool external =3D mdio_bus->external; =20 - if (reg & MII_ADDR_C45) - return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg, - val); + return _mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, devad, reg, + val); +} + +int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip, + struct mii_bus *bus, int addr, int reg, + u16 val) +{ + struct mv88e6xxx_mdio_bus *mdio_bus =3D bus->priv; + bool external =3D mdio_bus->external; =20 return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg, val); } =20 +int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, + struct mii_bus *bus, int addr, int devad, + int reg, u16 val) +{ + struct mv88e6xxx_mdio_bus *mdio_bus =3D bus->priv; + bool external =3D mdio_bus->external; + + return _mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, devad, reg, + val); +} + /* Offset 0x1B: Watchdog Control */ static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq) { diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xx= x/global2.h index 7536b8b0ad01..e973114d6890 100644 --- a/drivers/net/dsa/mv88e6xxx/global2.h +++ b/drivers/net/dsa/mv88e6xxx/global2.h @@ -314,12 +314,18 @@ int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip= , int reg, int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); =20 -int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, - struct mii_bus *bus, - int addr, int reg, u16 *val); -int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, - struct mii_bus *bus, - int addr, int reg, u16 val); +int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip, + struct mii_bus *bus, + int addr, int reg, u16 *val); +int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip, + struct mii_bus *bus, + int addr, int reg, u16 val); +int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, + struct mii_bus *bus, + int addr, int devad, int reg, u16 *val); +int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, + struct mii_bus *bus, + int addr, int devad, int reg, u16 val); int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); =20 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, diff --git a/drivers/net/dsa/mv88e6xxx/phy.c b/drivers/net/dsa/mv88e6xxx/ph= y.c index 252b5b3a3efe..8bb88b3d900d 100644 --- a/drivers/net/dsa/mv88e6xxx/phy.c +++ b/drivers/net/dsa/mv88e6xxx/phy.c @@ -55,6 +55,38 @@ int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int= phy, int reg, u16 val) return chip->info->ops->phy_write(chip, bus, addr, reg, val); } =20 +int mv88e6xxx_phy_read_c45(struct mv88e6xxx_chip *chip, int phy, int devad, + int reg, u16 *val) +{ + int addr =3D phy; /* PHY devices addresses start at 0x0 */ + struct mii_bus *bus; + + bus =3D mv88e6xxx_default_mdio_bus(chip); + if (!bus) + return -EOPNOTSUPP; + + if (!chip->info->ops->phy_read_c45) + return -EOPNOTSUPP; + + return chip->info->ops->phy_read_c45(chip, bus, addr, devad, reg, val); +} + +int mv88e6xxx_phy_write_c45(struct mv88e6xxx_chip *chip, int phy, int deva= d, + int reg, u16 val) +{ + int addr =3D phy; /* PHY devices addresses start at 0x0 */ + struct mii_bus *bus; + + bus =3D mv88e6xxx_default_mdio_bus(chip); + if (!bus) + return -EOPNOTSUPP; + + if (!chip->info->ops->phy_write_c45) + return -EOPNOTSUPP; + + return chip->info->ops->phy_write_c45(chip, bus, addr, devad, reg, val); +} + static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8= page) { return mv88e6xxx_phy_write(chip, phy, MV88E6XXX_PHY_PAGE, page); diff --git a/drivers/net/dsa/mv88e6xxx/phy.h b/drivers/net/dsa/mv88e6xxx/ph= y.h index 05ea0d546969..5f47722364cc 100644 --- a/drivers/net/dsa/mv88e6xxx/phy.h +++ b/drivers/net/dsa/mv88e6xxx/phy.h @@ -28,6 +28,10 @@ int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int = phy, int reg, u16 *val); int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, int reg, u16 val); +int mv88e6xxx_phy_read_c45(struct mv88e6xxx_chip *chip, int phy, int devad, + int reg, u16 *val); +int mv88e6xxx_phy_write_c45(struct mv88e6xxx_chip *chip, int phy, int deva= d, + int reg, u16 val); int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, u8 page, int reg, u16 *val); int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, diff --git a/drivers/net/dsa/mv88e6xxx/serdes.c b/drivers/net/dsa/mv88e6xxx= /serdes.c index d94150d8f3f4..72faec8f44dc 100644 --- a/drivers/net/dsa/mv88e6xxx/serdes.c +++ b/drivers/net/dsa/mv88e6xxx/serdes.c @@ -36,17 +36,13 @@ static int mv88e6352_serdes_write(struct mv88e6xxx_chip= *chip, int reg, static int mv88e6390_serdes_read(struct mv88e6xxx_chip *chip, int lane, int device, int reg, u16 *val) { - int reg_c45 =3D MII_ADDR_C45 | device << 16 | reg; - - return mv88e6xxx_phy_read(chip, lane, reg_c45, val); + return mv88e6xxx_phy_read_c45(chip, lane, device, reg, val); } =20 static int mv88e6390_serdes_write(struct mv88e6xxx_chip *chip, int lane, int device, int reg, u16 val) { - int reg_c45 =3D MII_ADDR_C45 | device << 16 | reg; - - return mv88e6xxx_phy_write(chip, lane, reg_c45, val); + return mv88e6xxx_phy_write_c45(chip, lane, device, reg, val); } =20 static int mv88e6xxx_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, --=20 2.30.2