From nobody Thu Nov 14 07:33:45 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99275C3DA79 for ; Mon, 26 Dec 2022 09:43:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231947AbiLZJnc (ORCPT ); Mon, 26 Dec 2022 04:43:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231585AbiLZJnC (ORCPT ); Mon, 26 Dec 2022 04:43:02 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98F202BC1; Mon, 26 Dec 2022 01:43:00 -0800 (PST) X-UUID: 48d1eb2f3db24682b423d8c0366d2002-20221226 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=q48BiG3GA6a/FVMi7I3tyjbzYJB8krFyaDYoiGSPB4U=; b=WUcS2FXt9PShfesWS9q1/xYqkgIFUZQxgTm43PZMPH6l7r0gLKG5ADhfvh5wojskWOp57KN79GSz1M+ADzsn7TnyKrCWeOd7q9wu9j82lRUdcGqJgoJdNosqbXeL2kfxbcNh4qpGRPviut/Ksz5Z6ObBLR1pm2AO/sZR0BSxJhc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:5a3ef7cf-5077-441e-afbd-e50b2fa230cb,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.14,REQID:5a3ef7cf-5077-441e-afbd-e50b2fa230cb,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:dcaaed0,CLOUDID:d1b7f8f3-ff42-4fb0-b929-626456a83c14,B ulkID:2212261742545BFO1ISZ,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 48d1eb2f3db24682b423d8c0366d2002-20221226 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1981579365; Mon, 26 Dec 2022 17:42:52 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 26 Dec 2022 17:42:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 26 Dec 2022 17:42:51 +0800 From: Roger Lu To: Matthias Brugger , Enric Balletbo Serra , Kevin Hilman , Nicolas Boichat CC: Fan Chen , Roger Lu , Jia-wei Chang , , , , , , Subject: [PATCH v1 11/13] soc: mediatek: mtk-svs: add thermal voltage compensation if needed Date: Mon, 26 Dec 2022 17:42:46 +0800 Message-ID: <20221226094248.4506-12-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221226094248.4506-1-roger.lu@mediatek.com> References: <20221226094248.4506-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some extreme test environment may keep IC temperature very low or very high during system boot stage. For stability concern, we add thermal voltage compenstation if needed no matter svs bank phase is in init02 or mon mode. Signed-off-by: Roger Lu Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 3a2be5ced8e6..dacfee4a0b32 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -557,7 +557,7 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svs= b) } =20 /* Get thermal effect */ - if (svsb->phase =3D=3D SVSB_PHASE_MON) { + if (!IS_ERR_OR_NULL(svsb->tzd)) { ret =3D thermal_zone_get_temp(svsb->tzd, &tzone_temp); if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && svsb->temp < SVSB_TEMP_LOWER_BOUND)) { @@ -572,7 +572,8 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svs= b) temp_voffset +=3D svsb->tzone_ltemp_voffset; =20 /* 2-line bank update all opp volts when running mon mode */ - if (svsb->type =3D=3D SVSB_HIGH || svsb->type =3D=3D SVSB_LOW) { + if (svsb->phase =3D=3D SVSB_PHASE_MON && (svsb->type =3D=3D SVSB_HIGH || + svsb->type =3D=3D SVSB_LOW)) { opp_start =3D 0; opp_stop =3D svsb->opp_count; } @@ -588,11 +589,6 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *sv= sb) /* do nothing */ goto unlock_mutex; case SVSB_PHASE_INIT02: - svsb_volt =3D max(svsb->volt[i], svsb->vmin); - opp_volt =3D svs_bank_volt_to_opp_volt(svsb_volt, - svsb->volt_step, - svsb->volt_base); - break; case SVSB_PHASE_MON: svsb_volt =3D max(svsb->volt[i] + temp_voffset, svsb->vmin); opp_volt =3D svs_bank_volt_to_opp_volt(svsb_volt, @@ -1680,7 +1676,7 @@ static int svs_bank_resource_setup(struct svs_platfor= m *svsp) } } =20 - if (svsb->mode_support & SVSB_MODE_MON) { + if (!IS_ERR_OR_NULL(svsb->tzone_name)) { svsb->tzd =3D thermal_zone_get_zone_by_name(svsb->tzone_name); if (IS_ERR(svsb->tzd)) { dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", @@ -2124,6 +2120,7 @@ static struct svs_bank svs_mt8192_banks[] =3D { .type =3D SVSB_LOW, .set_freq_pct =3D svs_set_bank_freq_pct_v3, .get_volts =3D svs_get_bank_volts_v3, + .tzone_name =3D "gpu1", .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT, .mode_support =3D SVSB_MODE_INIT02, .opp_count =3D MAX_OPP_ENTRIES, @@ -2141,6 +2138,10 @@ static struct svs_bank svs_mt8192_banks[] =3D { .core_sel =3D 0x0fff0100, .int_st =3D BIT(0), .ctl0 =3D 0x00540003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 0, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 7, }, { .sw_id =3D SVSB_GPU, --=20 2.18.0