From nobody Sun Apr 12 15:05:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1C18C41535 for ; Fri, 23 Dec 2022 11:57:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235990AbiLWL45 (ORCPT ); Fri, 23 Dec 2022 06:56:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229637AbiLWL4t (ORCPT ); Fri, 23 Dec 2022 06:56:49 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BAC02A270; Fri, 23 Dec 2022 03:56:48 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BNBufbQ095267; Fri, 23 Dec 2022 05:56:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1671796601; bh=9FLfUyBeHTKkjUtiRPpEx7qqv9j025D9xy4iL8U/B3w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ergnOXsZs1GaSQgM6Zy1xetNyApRf5YsQQdciPtgvO6Fuzrtu0aa054gM8E3tljDb vJ1NfB12Pm8Wnjh5ZQvD0ZFInd7xQ6vHvrHjY/btNTQ34uenc30DxcQIKqhW7N6tSp ehKkUcbDqGuWinoxVXIvuqle9IFClWeXrQTtZpf0= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BNBufHx008347 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Dec 2022 05:56:41 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 23 Dec 2022 05:56:41 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 23 Dec 2022 05:56:41 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BNBueAs092535; Fri, 23 Dec 2022 05:56:41 -0600 From: Devarsh Thakkar To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 1/2] dt-bindings: remoteproc: ti: Add new compatible for AM62 SoC family Date: Fri, 23 Dec 2022 17:26:37 +0530 Message-ID: <20221223115638.20192-2-devarsht@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221223115638.20192-1-devarsht@ti.com> References: <20221223115638.20192-1-devarsht@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AM62 family of devices don't have a R5F cluster, instead they have single core DM R5F. Add new compatible string ti,am62-r5fss to support this scenario. When this new compatible is used don't allow cluster-mode property usage in device-tree as this implies that there is no R5F cluster available and only single R5F core is present. Signed-off-by: Devarsh Thakkar --- V2: Avoid acronyms, use "Device Manager" instead of "DM" V3: - Use separate if block for each compatible for ti,cluster-mode property - Rearrange compatibles as per alphabatical order --- .../bindings/remoteproc/ti,k3-r5f-rproc.yaml | 68 +++++++++++++------ 1 file changed, 47 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.y= aml b/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml index fb9605f0655b..e8a861179bd9 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml @@ -21,6 +21,9 @@ description: | called "Single-CPU" mode, where only Core0 is used, but with ability to = use Core1's TCMs as well. =20 + AM62 SoC family support a single R5F core only which runs Device Manager + firmware and can also be used as a remote processor with IPC communicati= on. + Each Dual-Core R5F sub-system is represented as a single DTS node representing the cluster, with a pair of child DT nodes representing the individual R5F cores. Each node has a number of required or optional @@ -28,16 +31,20 @@ description: | the device management of the remote processor and to communicate with the remote processor. =20 + Since AM62 SoC family only support a single core, there is no cluster-mo= de + property setting required for it. + properties: $nodename: pattern: "^r5fss(@.*)?" =20 compatible: enum: + - ti,am62-r5fss + - ti,am64-r5fss - ti,am654-r5fss - - ti,j721e-r5fss - ti,j7200-r5fss - - ti,am64-r5fss + - ti,j721e-r5fss - ti,j721s2-r5fss =20 power-domains: @@ -80,7 +87,9 @@ patternProperties: node representing a TI instantiation of the Arm Cortex R5F core. The= re are some specific integration differences for the IP like the usage = of a Region Address Translator (RAT) for translating the larger SoC bus - addresses into a 32-bit address space for the processor. + addresses into a 32-bit address space for the processor. For AM62x, + the R5F Sub-System device node should only define one R5F child node + as it has only one core available. =20 Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM) internal memories split between two banks - TCMA and TCMB (further @@ -100,11 +109,12 @@ patternProperties: properties: compatible: enum: - - ti,am654-r5f - - ti,j721e-r5f - - ti,j7200-r5f - - ti,am64-r5f - - ti,j721s2-r5f + - ti,am62-r5fss + - ti,am64-r5fss + - ti,am654-r5fss + - ti,j7200-r5fss + - ti,j721e-r5fss + - ti,j721s2-r5fss =20 reg: items: @@ -208,19 +218,35 @@ patternProperties: =20 unevaluatedProperties: false =20 -if: - properties: - compatible: - enum: - - ti,am64-r5fss -then: - properties: - ti,cluster-mode: - enum: [0, 2] -else: - properties: - ti,cluster-mode: - enum: [0, 1] +allOf: + - if: + properties: + compatible: + enum: + - ti,am64-r5fss + then: + properties: + ti,cluster-mode: + enum: [0, 2] + + - if: + properties: + compatible: + enum: ["ti,am654-r5fss", "ti,j7200-r5fss", "ti,j721e-r5fss", "t= i,j721s2-r5fss"] + then: + properties: + ti,cluster-mode: + enum: [0, 1] + + - if: + properties: + compatible: + enum: + - ti,am62-r5fss + then: + properties: + ti,cluster-mode: false + =20 required: - compatible --=20 2.17.1 From nobody Sun Apr 12 15:05:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2DEEC4332F for ; Fri, 23 Dec 2022 11:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235294AbiLWL5G (ORCPT ); Fri, 23 Dec 2022 06:57:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230448AbiLWL4x (ORCPT ); Fri, 23 Dec 2022 06:56:53 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 913392A26F; Fri, 23 Dec 2022 03:56:50 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BNBuhR0126119; Fri, 23 Dec 2022 05:56:43 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1671796603; bh=Kqps/tfiJGXV621Iub//FTWNyVQs5QhSkQdxwUsfWrc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZPanXUOqf2ViF8sWqrlkqsEkuPnIBZqmwYBTMKgRyXn6hsJYgsgOaQd27n8UgK/uK mrjTaRczAOss6b6LyRUbusr0uVSaRdsFPX3aftikvkggt7GYTvGNWvyYPipvxCq5kS 1kleCJwACGy2ZnMfQsnC/HRbJgvbpt9pPpKl5Xbw= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BNBuhnx111615 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 23 Dec 2022 05:56:43 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 23 Dec 2022 05:56:43 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 23 Dec 2022 05:56:42 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BNBug8b008048; Fri, 23 Dec 2022 05:56:42 -0600 From: Devarsh Thakkar To: , , , , , , , CC: , , , , , , Subject: [PATCH v3 2/2] remoteproc: k3-r5: Use separate compatible string for TI AM62 SoC family Date: Fri, 23 Dec 2022 17:26:38 +0530 Message-ID: <20221223115638.20192-3-devarsht@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221223115638.20192-1-devarsht@ti.com> References: <20221223115638.20192-1-devarsht@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AM62 and AM62A SoCs use single core R5F which is a new scenario different than the one being used with CLUSTER_MODE_SINGLECPU which is for utilizing a single core from a set of cores available in R5F cluster present in the SoC. To support this single core scenario map it with newly defined CLUSTER_MODE_NONE and use it when compatible is set to ti,am62-r5fss. Signed-off-by: Devarsh Thakkar --- V2: Fix indentation and ordering issues as per review comments V3: Change CLUSTER_MODE_NONE value to -1 --- drivers/remoteproc/ti_k3_r5_remoteproc.c | 57 ++++++++++++++++++------ 1 file changed, 44 insertions(+), 13 deletions(-) diff --git a/drivers/remoteproc/ti_k3_r5_remoteproc.c b/drivers/remoteproc/= ti_k3_r5_remoteproc.c index 0481926c6975..127f1f68e592 100644 --- a/drivers/remoteproc/ti_k3_r5_remoteproc.c +++ b/drivers/remoteproc/ti_k3_r5_remoteproc.c @@ -74,9 +74,11 @@ struct k3_r5_mem { * Split mode : AM65x, J721E, J7200 and AM64x SoCs * LockStep mode : AM65x, J721E and J7200 SoCs * Single-CPU mode : AM64x SoCs only + * None : AM62x, AM62A SoCs */ enum cluster_mode { - CLUSTER_MODE_SPLIT =3D 0, + CLUSTER_MODE_NONE =3D -1, + CLUSTER_MODE_SPLIT, CLUSTER_MODE_LOCKSTEP, CLUSTER_MODE_SINGLECPU, }; @@ -86,11 +88,13 @@ enum cluster_mode { * @tcm_is_double: flag to denote the larger unified TCMs in certain modes * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for E= CC * @single_cpu_mode: flag to denote if SoC/IP supports Single-CPU mode + * @is_single_core: flag to denote if SoC/IP has only single core R5 */ struct k3_r5_soc_data { bool tcm_is_double; bool tcm_ecc_autoinit; bool single_cpu_mode; + bool is_single_core; }; =20 /** @@ -838,7 +842,8 @@ static int k3_r5_rproc_configure(struct k3_r5_rproc *kp= roc) =20 core0 =3D list_first_entry(&cluster->cores, struct k3_r5_core, elem); if (cluster->mode =3D=3D CLUSTER_MODE_LOCKSTEP || - cluster->mode =3D=3D CLUSTER_MODE_SINGLECPU) { + cluster->mode =3D=3D CLUSTER_MODE_SINGLECPU || + cluster->mode =3D=3D CLUSTER_MODE_NONE) { core =3D core0; } else { core =3D kproc->core; @@ -853,7 +858,7 @@ static int k3_r5_rproc_configure(struct k3_r5_rproc *kp= roc) boot_vec, cfg, ctrl, stat); =20 /* check if only Single-CPU mode is supported on applicable SoCs */ - if (cluster->soc_data->single_cpu_mode) { + if (cluster->soc_data->single_cpu_mode || cluster->soc_data->is_single_co= re) { single_cpu =3D !!(stat & PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY); if (single_cpu && cluster->mode =3D=3D CLUSTER_MODE_SPLIT) { @@ -1074,6 +1079,7 @@ static void k3_r5_adjust_tcm_sizes(struct k3_r5_rproc= *kproc) =20 if (cluster->mode =3D=3D CLUSTER_MODE_LOCKSTEP || cluster->mode =3D=3D CLUSTER_MODE_SINGLECPU || + cluster->mode =3D=3D CLUSTER_MODE_NONE || !cluster->soc_data->tcm_is_double) return; =20 @@ -1147,7 +1153,9 @@ static int k3_r5_rproc_configure_mode(struct k3_r5_rp= roc *kproc) atcm_enable =3D cfg & PROC_BOOT_CFG_FLAG_R5_ATCM_EN ? 1 : 0; btcm_enable =3D cfg & PROC_BOOT_CFG_FLAG_R5_BTCM_EN ? 1 : 0; loczrama =3D cfg & PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE ? 1 : 0; - if (cluster->soc_data->single_cpu_mode) { + if (cluster->soc_data->is_single_core) { + mode =3D CLUSTER_MODE_NONE; + } else if (cluster->soc_data->single_cpu_mode) { mode =3D cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? CLUSTER_MODE_SINGLECPU : CLUSTER_MODE_SPLIT; } else { @@ -1271,7 +1279,8 @@ static int k3_r5_cluster_rproc_init(struct platform_d= evice *pdev) =20 /* create only one rproc in lockstep mode or single-cpu mode */ if (cluster->mode =3D=3D CLUSTER_MODE_LOCKSTEP || - cluster->mode =3D=3D CLUSTER_MODE_SINGLECPU) + cluster->mode =3D=3D CLUSTER_MODE_SINGLECPU || + cluster->mode =3D=3D CLUSTER_MODE_NONE) break; } =20 @@ -1704,21 +1713,32 @@ static int k3_r5_probe(struct platform_device *pdev) * default to most common efuse configurations - Split-mode on AM64x * and LockStep-mode on all others */ - cluster->mode =3D data->single_cpu_mode ? + if (!data->is_single_core) + cluster->mode =3D data->single_cpu_mode ? CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP; + else + cluster->mode =3D CLUSTER_MODE_NONE; + cluster->soc_data =3D data; INIT_LIST_HEAD(&cluster->cores); =20 - ret =3D of_property_read_u32(np, "ti,cluster-mode", &cluster->mode); - if (ret < 0 && ret !=3D -EINVAL) { - dev_err(dev, "invalid format for ti,cluster-mode, ret =3D %d\n", - ret); - return ret; + if (!data->is_single_core) { + ret =3D of_property_read_s32(np, "ti,cluster-mode", &cluster->mode); + if (ret < 0 && ret !=3D -EINVAL) { + dev_err(dev, "invalid format for ti,cluster-mode, ret =3D %d\n", ret); + return ret; + } } =20 num_cores =3D of_get_available_child_count(np); - if (num_cores !=3D 2) { - dev_err(dev, "MCU cluster requires both R5F cores to be enabled, num_cor= es =3D %d\n", + if (num_cores !=3D 2 && !data->is_single_core) { + dev_err(dev, "MCU cluster requires both R5F cores to be enabled but num_= cores is set to =3D %d\n", + num_cores); + return -ENODEV; + } + + if (num_cores !=3D 1 && data->is_single_core) { + dev_err(dev, "SoC supports only single core R5 but num_cores is set to %= d\n", num_cores); return -ENODEV; } @@ -1760,18 +1780,28 @@ static const struct k3_r5_soc_data am65_j721e_soc_d= ata =3D { .tcm_is_double =3D false, .tcm_ecc_autoinit =3D false, .single_cpu_mode =3D false, + .is_single_core =3D false, }; =20 static const struct k3_r5_soc_data j7200_j721s2_soc_data =3D { .tcm_is_double =3D true, .tcm_ecc_autoinit =3D true, .single_cpu_mode =3D false, + .is_single_core =3D false, }; =20 static const struct k3_r5_soc_data am64_soc_data =3D { .tcm_is_double =3D true, .tcm_ecc_autoinit =3D true, .single_cpu_mode =3D true, + .is_single_core =3D false, +}; + +static const struct k3_r5_soc_data am62_soc_data =3D { + .tcm_is_double =3D false, + .tcm_ecc_autoinit =3D true, + .single_cpu_mode =3D false, + .is_single_core =3D true, }; =20 static const struct of_device_id k3_r5_of_match[] =3D { @@ -1779,6 +1809,7 @@ static const struct of_device_id k3_r5_of_match[] =3D= { { .compatible =3D "ti,j721e-r5fss", .data =3D &am65_j721e_soc_data, }, { .compatible =3D "ti,j7200-r5fss", .data =3D &j7200_j721s2_soc_data, }, { .compatible =3D "ti,am64-r5fss", .data =3D &am64_soc_data, }, + { .compatible =3D "ti,am62-r5fss", .data =3D &am62_soc_data, }, { .compatible =3D "ti,j721s2-r5fss", .data =3D &j7200_j721s2_soc_data, }, { /* sentinel */ }, }; --=20 2.17.1