From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15B74C41535 for ; Fri, 23 Dec 2022 09:43:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236182AbiLWJnY (ORCPT ); Fri, 23 Dec 2022 04:43:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236077AbiLWJnK (ORCPT ); Fri, 23 Dec 2022 04:43:10 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9DFE3722C; Fri, 23 Dec 2022 01:43:09 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5B7EC6602CE1; Fri, 23 Dec 2022 09:43:07 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788588; bh=4EyQ1OjZT/baUayxYK+ueqc8j67gyi4x2llaOGk/ij8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N8rBp5+Td/KdXaiYh1HKJVsvFExiZTNHsA4pbwlj2Ib5yTsKddTj2iqzedjY949yg 7V16FMf2Y9RNJFRj4xZYP3/cpaX4VGGMRWnhWHz9WBakWMPKhi3RAiwbdhPep1rIAT ZR+Kfx6LVN/14FoLLIY9VH2qlukGG7RoDAqCGa+QGWVT17kvsOlINu8sWQ6hCNZm0e ons2Cx3HgBuTv6r/WiDWoSJ0UJapkS+RsCAWND78w3aK/eym2XsmymuWsUqQXtQSwe AGZ1HJ36EFjFk2r2DIy3MUqtNx59UhMl7DXftMgo2roTd+WIab8HYpSR1ftVE0vlUC //DeYYDMtMFUw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 01/23] clk: mediatek: mt8192: Correctly unregister and free clocks on failure Date: Fri, 23 Dec 2022 10:42:37 +0100 Message-Id: <20221223094259.87373-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If anything fails during probe of the clock controller(s), unregister (and kfree!) whatever we have previously registered to leave with a clean state and prevent leaks. Fixes: 710573dee31b ("clk: mediatek: Add MT8192 basic clocks support") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Markus Schneider-Pargmann Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8192.c | 72 ++++++++++++++++++++++++------- 1 file changed, 56 insertions(+), 16 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 0e88588b2c49..eff66ca6c6a7 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1100,27 +1100,61 @@ static int clk_mt8192_top_probe(struct platform_dev= ice *pdev) if (IS_ERR(base)) return PTR_ERR(base); =20 - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), t= op_clk_data); - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_= clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); - mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, &m= t8192_clk_lock, - top_clk_data); - mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt81= 92_clk_lock, - top_clk_data); - mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,= &mt8192_clk_lock, - top_clk_data); - r =3D mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_cl= k_data); + r =3D mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_cl= ks), top_clk_data); if (r) return r; =20 + r =3D mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs)= , top_clk_data); + if (r) + goto unregister_fixed_clks; + + r =3D mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_da= ta); + if (r) + goto unregister_early_factors; + + r =3D mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), no= de, + &mt8192_clk_lock, top_clk_data); + if (r) + goto unregister_factors; + + r =3D mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, + &mt8192_clk_lock, top_clk_data); + if (r) + goto unregister_muxes; + + r =3D mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs),= base, + &mt8192_clk_lock, top_clk_data); + if (r) + goto unregister_top_composites; + + r =3D mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_cl= k_data); + if (r) + goto unregister_adj_divs_composites; + r =3D clk_mt8192_reg_mfg_mux_notifier(&pdev->dev, top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk); if (r) - return r; - + goto unregister_gates; =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); + +unregister_gates: + mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); +unregister_adj_divs_composites: + mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top= _clk_data); +unregister_top_composites: + mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_d= ata); +unregister_muxes: + mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_cl= k_data); +unregister_factors: + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); +unregister_early_factors: + mtk_clk_unregister_factors(top_early_divs, ARRAY_SIZE(top_early_divs), to= p_clk_data); +unregister_fixed_clks: + mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + top_clk_data); + return r; } =20 static int clk_mt8192_infra_probe(struct platform_device *pdev) @@ -1139,14 +1173,16 @@ static int clk_mt8192_infra_probe(struct platform_d= evice *pdev) =20 r =3D mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); if (r) - goto free_clk_data; + goto unregister_gates; =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - goto free_clk_data; + goto unregister_gates; =20 return r; =20 +unregister_gates: + mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return r; @@ -1168,10 +1204,12 @@ static int clk_mt8192_peri_probe(struct platform_de= vice *pdev) =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - goto free_clk_data; + goto unregister_gates; =20 return r; =20 +unregister_gates: + mtk_clk_unregister_gates(peri_clks, ARRAY_SIZE(peri_clks), clk_data); free_clk_data: mtk_free_clk_data(clk_data); return r; @@ -1194,10 +1232,12 @@ static int clk_mt8192_apmixed_probe(struct platform= _device *pdev) =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - goto free_clk_data; + goto unregister_gates; =20 return r; =20 +unregister_gates: + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data= ); free_clk_data: mtk_free_clk_data(clk_data); return r; --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BA54C4332F for ; Fri, 23 Dec 2022 09:43:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236203AbiLWJn3 (ORCPT ); Fri, 23 Dec 2022 04:43:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236079AbiLWJnM (ORCPT ); Fri, 23 Dec 2022 04:43:12 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 484D93578D; Fri, 23 Dec 2022 01:43:11 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id CC2996602CE4; Fri, 23 Dec 2022 09:43:08 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788590; bh=X/oZl8ocJQt071EbQHuHIaXUvTU5xZlpFyUlUhGeBQk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dDtyaEv3S2dKjskptbhe/8wP1Sfd0jjFw2TV26gHba+HAigLa9n2QOudgFaAcwXQf oOQ2tPUv5ajYu9c0AFSFbI+A/9NWvVakV6CLROPFxH8QQJCujpLi7c83cjMJ3/6+3m /Uie+lHV5M6mde2SZCsmnJkOOOiVCxG7b0EZyXo0eqLnJ+mfpyS+HMNennF5KSTX6I 8oSB2taVxBGwOoaRz6B84Mh1ysmBvXNpe62AHaX+KBPWw11fFKgFvFYz50msjJ9VOG SLs9/yDWEaA3OmwEtkCiKUafMDglozUqUk4By1uDCO1EOhXzILca/b9XUxkwPhHnQO rhy6RBORwgE1A== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 02/23] clk: mediatek: mt8192: Propagate struct device for gate clocks Date: Fri, 23 Dec 2022 10:42:38 +0100 Message-Id: <20221223094259.87373-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert instances of mtk_clk_register_gates() to use the newer mtk_clk_register_gates_with_dev() to propagate struct device to the clk framework. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8192.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index eff66ca6c6a7..991d78a71644 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1127,7 +1127,8 @@ static int clk_mt8192_top_probe(struct platform_devic= e *pdev) if (r) goto unregister_top_composites; =20 - r =3D mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_cl= k_data); + r =3D mtk_clk_register_gates_with_dev(node, top_clks, ARRAY_SIZE(top_clks= ), + top_clk_data, &pdev->dev); if (r) goto unregister_adj_divs_composites; =20 @@ -1167,7 +1168,8 @@ static int clk_mt8192_infra_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), cl= k_data); + r =3D mtk_clk_register_gates_with_dev(node, infra_clks, ARRAY_SIZE(infra_= clks), + clk_data, &pdev->dev); if (r) goto free_clk_data; =20 @@ -1198,7 +1200,8 @@ static int clk_mt8192_peri_probe(struct platform_devi= ce *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_= data); + r =3D mtk_clk_register_gates_with_dev(node, peri_clks, ARRAY_SIZE(peri_cl= ks), + clk_data, &pdev->dev); if (r) goto free_clk_data; =20 @@ -1226,7 +1229,9 @@ static int clk_mt8192_apmixed_probe(struct platform_d= evice *pdev) return -ENOMEM; =20 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - r =3D mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks)= , clk_data); + r =3D mtk_clk_register_gates_with_dev(node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data, + &pdev->dev); if (r) goto free_clk_data; =20 --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E595C4332F for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1671788591; bh=xMZiAKwpe53kZFQbADFekhYR4L86oA0T01+MfIvvLHU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tef3oBrr/G1OcBlFnGxWOhNONvsFB5fNLR0aeEIyUIh/Au8HeFh16iYZPmTUPLhor +198RTiFE4LNpyAGBsVdkMzbmGu4jhqhXmwdCz1+bI3clGidXMbFpZ6aR65RO2pb77 GEa/6jH1zI1ApjIB8MUeGlG75GDjHs3+3GkI5sHsNKbhD/cNd61WIDvr5g907axben i5YTTPuFcEsRLXX8x7ldRE92znC0VrsCE+TTnCD6/ewwjFr6NaMdUDf/HTuP73+tH7 qB+pylWhzN916GG0vDU1NQWQquL7EQk0YPu5O0dbA6Pz/i34Uxy/ZJbks8RjvkBO5k g/EKKWkvIERSw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 03/23] clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates() Date: Fri, 23 Dec 2022 10:42:39 +0100 Message-Id: <20221223094259.87373-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device") introduces a helper function for the sole purpose of propagating a struct device pointer to the clk API when registering the mtk-gate clocks to take advantage of Runtime PM when/where needed and where a power domain is defined in devicetree. Function mtk_clk_register_gates() then becomes a wrapper around the new mtk_clk_register_gates_with_dev() function that will simply pass NULL as struct device: this is essential when registering drivers with CLK_OF_DECLARE instead of as a platform device, as there will be no struct device to pass... but we can as well simply have only one function that always takes such pointer as a param and pass NULL when unavoidable. This commit removes the mtk_clk_register_gates() wrapper and renames mtk_clk_register_gates_with_dev() to the former and all of the calls to either of the two functions were fixed in all drivers in order to reflect this change. Since a lot of MediaTek clock drivers are actually registering as a platform device, but were still registering the mtk-gate clocks without passing any struct device to the clock framework, they've been changed to pass a valid one now, as to make all those platforms able to use runtime power management where available. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Markus Schneider-Pargmann Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-gate.c | 16 ++++------------ drivers/clk/mediatek/clk-gate.h | 8 ++------ drivers/clk/mediatek/clk-mt2701-aud.c | 2 +- drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701-mm.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 6 +++--- drivers/clk/mediatek/clk-mt2712-mm.c | 2 +- drivers/clk/mediatek/clk-mt2712.c | 6 +++--- drivers/clk/mediatek/clk-mt6765.c | 6 +++--- drivers/clk/mediatek/clk-mt6779-mm.c | 2 +- drivers/clk/mediatek/clk-mt6779.c | 4 ++-- drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++- drivers/clk/mediatek/clk-mt6795-mm.c | 3 ++- drivers/clk/mediatek/clk-mt6795-pericfg.c | 3 ++- drivers/clk/mediatek/clk-mt6797-mm.c | 2 +- drivers/clk/mediatek/clk-mt6797.c | 2 +- drivers/clk/mediatek/clk-mt7622-aud.c | 2 +- drivers/clk/mediatek/clk-mt7622-eth.c | 4 ++-- drivers/clk/mediatek/clk-mt7622-hif.c | 4 ++-- drivers/clk/mediatek/clk-mt7622.c | 9 +++++---- drivers/clk/mediatek/clk-mt7629-eth.c | 5 +++-- drivers/clk/mediatek/clk-mt7629-hif.c | 4 ++-- drivers/clk/mediatek/clk-mt7629.c | 6 +++--- drivers/clk/mediatek/clk-mt7986-eth.c | 6 +++--- drivers/clk/mediatek/clk-mt7986-infracfg.c | 2 +- drivers/clk/mediatek/clk-mt8135.c | 4 ++-- drivers/clk/mediatek/clk-mt8167-aud.c | 2 +- drivers/clk/mediatek/clk-mt8167-img.c | 2 +- drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 2 +- drivers/clk/mediatek/clk-mt8167-mm.c | 2 +- drivers/clk/mediatek/clk-mt8167-vdec.c | 3 ++- drivers/clk/mediatek/clk-mt8167.c | 2 +- drivers/clk/mediatek/clk-mt8173-mm.c | 2 +- drivers/clk/mediatek/clk-mt8173.c | 12 ++++++------ drivers/clk/mediatek/clk-mt8183-audio.c | 2 +- drivers/clk/mediatek/clk-mt8183-mm.c | 2 +- drivers/clk/mediatek/clk-mt8183.c | 8 ++++---- drivers/clk/mediatek/clk-mt8186-mm.c | 3 ++- drivers/clk/mediatek/clk-mt8192-aud.c | 3 ++- drivers/clk/mediatek/clk-mt8192-mm.c | 3 ++- drivers/clk/mediatek/clk-mt8192.c | 12 ++++++------ drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 3 ++- drivers/clk/mediatek/clk-mt8195-topckgen.c | 3 ++- drivers/clk/mediatek/clk-mt8195-vdo0.c | 3 ++- drivers/clk/mediatek/clk-mt8195-vdo1.c | 3 ++- drivers/clk/mediatek/clk-mt8365-mm.c | 5 ++--- drivers/clk/mediatek/clk-mt8365.c | 2 +- drivers/clk/mediatek/clk-mt8516-aud.c | 2 +- drivers/clk/mediatek/clk-mt8516.c | 2 +- drivers/clk/mediatek/clk-mtk.c | 4 ++-- 52 files changed, 103 insertions(+), 103 deletions(-) diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gat= e.c index 0c867136e49d..80deaabfd848 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -202,10 +202,10 @@ static void mtk_clk_unregister_gate(struct clk_hw *hw) kfree(cg); } =20 -int mtk_clk_register_gates_with_dev(struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data, - struct device *dev) +int mtk_clk_register_gates(struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_hw_onecell_data *clk_data, + struct device *dev) { int i; struct clk_hw *hw; @@ -261,14 +261,6 @@ int mtk_clk_register_gates_with_dev(struct device_node= *node, =20 return PTR_ERR(hw); } -EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev); - -int mtk_clk_register_gates(struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data) -{ - return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL); -} EXPORT_SYMBOL_GPL(mtk_clk_register_gates); =20 void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gat= e.h index d9897ef53528..03053c2c2fdd 100644 --- a/drivers/clk/mediatek/clk-gate.h +++ b/drivers/clk/mediatek/clk-gate.h @@ -52,12 +52,8 @@ struct mtk_gate { =20 int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data); - -int mtk_clk_register_gates_with_dev(struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data, - struct device *dev); + struct clk_hw_onecell_data *clk_data, + struct device *dev); =20 void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, struct clk_hw_onecell_data *clk_data); diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/c= lk-mt2701-aud.c index 6ba398eb7df9..ab13ab618fb5 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -152,7 +152,7 @@ static int clk_mt2701_aud_probe(struct platform_device = *pdev) clk_data =3D mtk_alloc_clk_data(CLK_AUD_NR); =20 mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index edf1e2ed2b59..9670e1e170f2 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *p= dev) clk_data =3D mtk_alloc_clk_data(CLK_ETHSYS_NR); =20 mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index 1458109d99d9..11391b144267 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device = *pdev) clk_data =3D mtk_alloc_clk_data(CLK_G3DSYS_NR); =20 mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index 434cbbe8c037..c14c0bb10f88 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -55,7 +55,7 @@ static int clk_mt2701_hif_probe(struct platform_device *p= dev) clk_data =3D mtk_alloc_clk_data(CLK_HIFSYS_NR); =20 mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/cl= k-mt2701-mm.c index 9ea7abad99d2..ec5e516ca099 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -89,7 +89,7 @@ static int clk_mt2701_mm_probe(struct platform_device *pd= ev) clk_data =3D mtk_alloc_clk_data(CLK_MM_NR); =20 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index 9b442af37e67..dff69fabb171 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -690,7 +690,7 @@ static int mtk_topckgen_init(struct platform_device *pd= ev) base, &mt2701_clk_lock, clk_data); =20 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - clk_data); + clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } @@ -796,7 +796,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) } =20 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - infra_clk_data); + infra_clk_data, &pdev->dev); mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), infra_clk_data); =20 @@ -919,7 +919,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR); =20 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data); + clk_data, &pdev->dev); =20 mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, &mt2701_clk_lock, clk_data); diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/cl= k-mt2712-mm.c index 7d44b09b8a0a..6c5f26a73476 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -136,7 +136,7 @@ static int clk_mt2712_mm_probe(struct platform_device *= pdev) clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); =20 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index 56980dd6c2ea..24ec3384c429 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1351,7 +1351,7 @@ static int clk_mt2712_top_probe(struct platform_devic= e *pdev) mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt2712_clk_lock, top_clk_data); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - top_clk_data); + top_clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); =20 @@ -1371,7 +1371,7 @@ static int clk_mt2712_infra_probe(struct platform_dev= ice *pdev) clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); =20 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 @@ -1393,7 +1393,7 @@ static int clk_mt2712_peri_probe(struct platform_devi= ce *pdev) clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); =20 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-m= t6765.c index e9b9e6729733..7401693ef472 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -790,7 +790,7 @@ static int clk_mt6765_apmixed_probe(struct platform_dev= ice *pdev) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); =20 mtk_clk_register_gates(node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); + ARRAY_SIZE(apmixed_clks), clk_data, &pdev->dev); r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 if (r) @@ -829,7 +829,7 @@ static int clk_mt6765_top_probe(struct platform_device = *pdev) mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, &mt6765_clk_lock, clk_data); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 @@ -863,7 +863,7 @@ static int clk_mt6765_ifr_probe(struct platform_device = *pdev) clk_data =3D mtk_alloc_clk_data(CLK_IFR_NR_CLK); =20 mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks), - clk_data); + clk_data, &pdev->dev); r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 if (r) diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/cl= k-mt6779-mm.c index eda8cbee3d23..101808b3e38f 100644 --- a/drivers/clk/mediatek/clk-mt6779-mm.c +++ b/drivers/clk/mediatek/clk-mt6779-mm.c @@ -94,7 +94,7 @@ static int clk_mt6779_mm_probe(struct platform_device *pd= ev) clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); =20 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), - clk_data); + clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-m= t6779.c index 0d0a90ee5eb2..622a2fc6c167 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1222,7 +1222,7 @@ static int clk_mt6779_apmixed_probe(struct platform_d= evice *pdev) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); =20 mtk_clk_register_gates(node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); + ARRAY_SIZE(apmixed_clks), clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } @@ -1264,7 +1264,7 @@ static int clk_mt6779_infra_probe(struct platform_dev= ice *pdev) clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); =20 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt6795-infracfg.c b/drivers/clk/media= tek/clk-mt6795-infracfg.c index df7eed6e071e..4bbd2bfe2ec4 100644 --- a/drivers/clk/mediatek/clk-mt6795-infracfg.c +++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c @@ -101,7 +101,8 @@ static int clk_mt6795_infracfg_probe(struct platform_de= vice *pdev) if (ret) goto free_clk_data; =20 - ret =3D mtk_clk_register_gates(node, infra_gates, ARRAY_SIZE(infra_gates)= , clk_data); + ret =3D mtk_clk_register_gates(node, infra_gates, ARRAY_SIZE(infra_gates), + clk_data, &pdev->dev); if (ret) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt6795-mm.c b/drivers/clk/mediatek/cl= k-mt6795-mm.c index fd73f202f292..10a623b83f68 100644 --- a/drivers/clk/mediatek/clk-mt6795-mm.c +++ b/drivers/clk/mediatek/clk-mt6795-mm.c @@ -87,7 +87,8 @@ static int clk_mt6795_mm_probe(struct platform_device *pd= ev) if (!clk_data) return -ENOMEM; =20 - ret =3D mtk_clk_register_gates(node, mm_gates, ARRAY_SIZE(mm_gates), clk_= data); + ret =3D mtk_clk_register_gates(node, mm_gates, ARRAY_SIZE(mm_gates), + clk_data, &pdev->dev); if (ret) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt6795-pericfg.c b/drivers/clk/mediat= ek/clk-mt6795-pericfg.c index cb28d35dad59..479a8abcb80b 100644 --- a/drivers/clk/mediatek/clk-mt6795-pericfg.c +++ b/drivers/clk/mediatek/clk-mt6795-pericfg.c @@ -109,7 +109,8 @@ static int clk_mt6795_pericfg_probe(struct platform_dev= ice *pdev) if (ret) goto free_clk_data; =20 - ret =3D mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), = clk_data); + ret =3D mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), + clk_data, &pdev->dev); if (ret) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/cl= k-mt6797-mm.c index 0846011fc894..dd96db5f2c0d 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -102,7 +102,7 @@ static int clk_mt6797_mm_probe(struct platform_device *= pdev) clk_data =3D mtk_alloc_clk_data(CLK_MM_NR); =20 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-m= t6797.c index b89f325a4b9b..250ac8bd6a3c 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -597,7 +597,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) } =20 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - infra_clk_data); + infra_clk_data, &pdev->dev); mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), infra_clk_data); =20 diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/c= lk-mt7622-aud.c index 9f2e5aa7b5d9..d0379d8704af 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -139,7 +139,7 @@ static int clk_mt7622_audiosys_init(struct platform_dev= ice *pdev) clk_data =3D mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); =20 mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index 43de0477d5d9..9b4a26ca0f44 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -82,7 +82,7 @@ static int clk_mt7622_ethsys_init(struct platform_device = *pdev) clk_data =3D mtk_alloc_clk_data(CLK_ETH_NR_CLK); =20 mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -104,7 +104,7 @@ static int clk_mt7622_sgmiisys_init(struct platform_dev= ice *pdev) clk_data =3D mtk_alloc_clk_data(CLK_SGMII_NR_CLK); =20 mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index 67e96231dd25..8cf37f75ca77 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -93,7 +93,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_devic= e *pdev) clk_data =3D mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); =20 mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -115,7 +115,7 @@ static int clk_mt7622_pciesys_init(struct platform_devi= ce *pdev) clk_data =3D mtk_alloc_clk_data(CLK_PCIE_NR_CLK); =20 mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 3b55f8641fae..eab450fc824c 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -653,7 +653,7 @@ static int mtk_topckgen_init(struct platform_device *pd= ev) base, &mt7622_clk_lock, clk_data); =20 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - clk_data); + clk_data, &pdev->dev); =20 clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); @@ -671,7 +671,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); =20 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); =20 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), clk_data); @@ -699,7 +699,8 @@ static int mtk_apmixedsys_init(struct platform_device *= pdev) clk_data); =20 mtk_clk_register_gates(node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); + ARRAY_SIZE(apmixed_clks), clk_data, + &pdev->dev); =20 clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk); @@ -721,7 +722,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); =20 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data); + clk_data, &pdev->dev); =20 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, &mt7622_clk_lock, clk_data); diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/c= lk-mt7629-eth.c index 282dd6559465..39aa9eb5355e 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -92,7 +92,8 @@ static int clk_mt7629_ethsys_init(struct platform_device = *pdev) =20 clk_data =3D mtk_alloc_clk_data(CLK_ETH_NR_CLK); =20 - mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data); + mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -115,7 +116,7 @@ static int clk_mt7629_sgmiisys_init(struct platform_dev= ice *pdev) clk_data =3D mtk_alloc_clk_data(CLK_SGMII_NR_CLK); =20 mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK, - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index 0c8b9e139789..44fbd88b4647 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -88,7 +88,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_devic= e *pdev) clk_data =3D mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); =20 mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -110,7 +110,7 @@ static int clk_mt7629_pciesys_init(struct platform_devi= ce *pdev) clk_data =3D mtk_alloc_clk_data(CLK_PCIE_NR_CLK); =20 mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-m= t7629.c index e4a08c811adc..2daceeab7fc4 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -606,7 +606,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); =20 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); =20 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), clk_data); @@ -629,7 +629,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); =20 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data); + clk_data, &pdev->dev); =20 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, &mt7629_clk_lock, clk_data); @@ -656,7 +656,7 @@ static int mtk_apmixedsys_init(struct platform_device *= pdev) clk_data); =20 mtk_clk_register_gates(node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); + ARRAY_SIZE(apmixed_clks), clk_data, &pdev->dev); =20 clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk); diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/c= lk-mt7986-eth.c index 7868c0728e96..765df117afa6 100644 --- a/drivers/clk/mediatek/clk-mt7986-eth.c +++ b/drivers/clk/mediatek/clk-mt7986-eth.c @@ -85,7 +85,7 @@ static void __init mtk_sgmiisys_0_init(struct device_node= *node) clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); =20 mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), - clk_data); + clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -103,7 +103,7 @@ static void __init mtk_sgmiisys_1_init(struct device_no= de *node) clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); =20 mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), - clk_data); + clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 @@ -121,7 +121,7 @@ static void __init mtk_ethsys_init(struct device_node *= node) =20 clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); =20 - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); + mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data, NU= LL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/media= tek/clk-mt7986-infracfg.c index 49666047bf0e..24947ccdb70a 100644 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -193,7 +193,7 @@ static int clk_mt7986_infracfg_probe(struct platform_de= vice *pdev) mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, &mt7986_clk_lock, clk_data); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index b68888a034c4..7193ab38090d 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -568,7 +568,7 @@ static void __init mtk_infrasys_init(struct device_node= *node) clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); =20 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, NULL); =20 clk_prepare_enable(clk_data->hws[CLK_INFRA_M4U]->clk); =20 @@ -596,7 +596,7 @@ static void __init mtk_pericfg_init(struct device_node = *node) clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); =20 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), - clk_data); + clk_data, NULL); mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, &mt8135_clk_lock, clk_data); =20 diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/c= lk-mt8167-aud.c index ce1ae8d243c3..aa229aaf467f 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -55,7 +55,7 @@ static void __init mtk_audsys_init(struct device_node *no= de) =20 clk_data =3D mtk_alloc_clk_data(CLK_AUD_NR_CLK); =20 - mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data); + mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data, NU= LL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/c= lk-mt8167-img.c index e359e563d2b7..1e592fa46c96 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -48,7 +48,7 @@ static void __init mtk_imgsys_init(struct device_node *no= de) =20 clk_data =3D mtk_alloc_clk_data(CLK_IMG_NR_CLK); =20 - mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data); + mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data, NU= LL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8167-mfgcfg.c index 4fd82fe87d6e..b494d04bc851 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -46,7 +46,7 @@ static void __init mtk_mfgcfg_init(struct device_node *no= de) =20 clk_data =3D mtk_alloc_clk_data(CLK_MFG_NR_CLK); =20 - mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data); + mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data, NU= LL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/cl= k-mt8167-mm.c index 73910060577f..5669b5eecca9 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -111,7 +111,7 @@ static int clk_mt8167_mm_probe(struct platform_device *= pdev) data =3D &mt8167_mmsys_driver_data; =20 ret =3D mtk_clk_register_gates(node, data->gates_clk, data->gates_num, - clk_data); + clk_data, &pdev->dev); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/= clk-mt8167-vdec.c index ee4fffb6859d..fcd6fdcd2536 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -61,7 +61,8 @@ static void __init mtk_vdecsys_init(struct device_node *n= ode) =20 clk_data =3D mtk_alloc_clk_data(CLK_VDEC_NR_CLK); =20 - mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), clk_data); + mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), + clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index f900ac4bf7b8..b150f893a4b8 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -937,7 +937,7 @@ static void __init mtk_topckgen_init(struct device_node= *node) =20 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); - mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data); + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data, NU= LL); =20 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/cl= k-mt8173-mm.c index 8abf42c2030c..a99583c62c3b 100644 --- a/drivers/clk/mediatek/clk-mt8173-mm.c +++ b/drivers/clk/mediatek/clk-mt8173-mm.c @@ -125,7 +125,7 @@ static int clk_mt8173_mm_probe(struct platform_device *= pdev) data =3D &mt8173_mmsys_driver_data; =20 ret =3D mtk_clk_register_gates(node, data->gates_clk, data->gates_num, - clk_data); + clk_data, &pdev->dev); if (ret) return ret; =20 diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-m= t8173.c index b57e33cda7a5..dfb819dd1b1b 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -889,7 +889,7 @@ static void __init mtk_infrasys_init(struct device_node= *node) clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); =20 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, NULL); mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); =20 mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), @@ -919,7 +919,7 @@ static void __init mtk_pericfg_init(struct device_node = *node) clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); =20 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), - clk_data); + clk_data, NULL); mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, &mt8173_clk_lock, clk_data); =20 @@ -1063,7 +1063,7 @@ static void __init mtk_imgsys_init(struct device_node= *node) clk_data =3D mtk_alloc_clk_data(CLK_IMG_NR_CLK); =20 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), - clk_data); + clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 @@ -1081,7 +1081,7 @@ static void __init mtk_vdecsys_init(struct device_nod= e *node) clk_data =3D mtk_alloc_clk_data(CLK_VDEC_NR_CLK); =20 mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), - clk_data); + clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -1098,7 +1098,7 @@ static void __init mtk_vencsys_init(struct device_nod= e *node) clk_data =3D mtk_alloc_clk_data(CLK_VENC_NR_CLK); =20 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), - clk_data); + clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -1115,7 +1115,7 @@ static void __init mtk_vencltsys_init(struct device_n= ode *node) clk_data =3D mtk_alloc_clk_data(CLK_VENCLT_NR_CLK); =20 mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks), - clk_data); + clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek= /clk-mt8183-audio.c index b2d7746eddbe..f4c6448b6f74 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -76,7 +76,7 @@ static int clk_mt8183_audio_probe(struct platform_device = *pdev) clk_data =3D mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); =20 mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/cl= k-mt8183-mm.c index 11ecc6fb0065..f93043da26c0 100644 --- a/drivers/clk/mediatek/clk-mt8183-mm.c +++ b/drivers/clk/mediatek/clk-mt8183-mm.c @@ -91,7 +91,7 @@ static int clk_mt8183_mm_probe(struct platform_device *pd= ev) clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); =20 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), - clk_data); + clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 23afc9584638..f99c092476c2 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1101,7 +1101,7 @@ static int clk_mt8183_apmixed_probe(struct platform_d= evice *pdev) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); =20 mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), - clk_data); + clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } @@ -1176,7 +1176,7 @@ static int clk_mt8183_top_probe(struct platform_devic= e *pdev) base, &mt8183_clk_lock, top_clk_data); =20 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - top_clk_data); + top_clk_data, &pdev->dev); =20 ret =3D clk_mt8183_reg_mfg_mux_notifier(&pdev->dev, top_clk_data->hws[CLK_TOP_MUX_MFG]->clk); @@ -1196,7 +1196,7 @@ static int clk_mt8183_infra_probe(struct platform_dev= ice *pdev) clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); =20 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { @@ -1219,7 +1219,7 @@ static int clk_mt8183_peri_probe(struct platform_devi= ce *pdev) clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); =20 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data); + clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt8186-mm.c b/drivers/clk/mediatek/cl= k-mt8186-mm.c index 1d33be407947..35038928eacf 100644 --- a/drivers/clk/mediatek/clk-mt8186-mm.c +++ b/drivers/clk/mediatek/clk-mt8186-mm.c @@ -69,7 +69,8 @@ static int clk_mt8186_mm_probe(struct platform_device *pd= ev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data= ); + r =3D mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), + clk_data, &pdev->dev); if (r) goto free_mm_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/c= lk-mt8192-aud.c index 8c989bffd8c7..3acadca2452a 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -87,7 +87,8 @@ static int clk_mt8192_aud_probe(struct platform_device *p= dev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_da= ta); + r =3D mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), + clk_data, &pdev->dev); if (r) return r; =20 diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/cl= k-mt8192-mm.c index 1be3ff4d407d..226f6976c277 100644 --- a/drivers/clk/mediatek/clk-mt8192-mm.c +++ b/drivers/clk/mediatek/clk-mt8192-mm.c @@ -91,7 +91,8 @@ static int clk_mt8192_mm_probe(struct platform_device *pd= ev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data= ); + r =3D mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), + clk_data, &pdev->dev); if (r) return r; =20 diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 991d78a71644..e1b625b86911 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1127,7 +1127,7 @@ static int clk_mt8192_top_probe(struct platform_devic= e *pdev) if (r) goto unregister_top_composites; =20 - r =3D mtk_clk_register_gates_with_dev(node, top_clks, ARRAY_SIZE(top_clks= ), + r =3D mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data, &pdev->dev); if (r) goto unregister_adj_divs_composites; @@ -1168,7 +1168,7 @@ static int clk_mt8192_infra_probe(struct platform_dev= ice *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates_with_dev(node, infra_clks, ARRAY_SIZE(infra_= clks), + r =3D mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data, &pdev->dev); if (r) goto free_clk_data; @@ -1200,7 +1200,7 @@ static int clk_mt8192_peri_probe(struct platform_devi= ce *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates_with_dev(node, peri_clks, ARRAY_SIZE(peri_cl= ks), + r =3D mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data, &pdev->dev); if (r) goto free_clk_data; @@ -1229,9 +1229,9 @@ static int clk_mt8192_apmixed_probe(struct platform_d= evice *pdev) return -ENOMEM; =20 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - r =3D mtk_clk_register_gates_with_dev(node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data, - &pdev->dev); + r =3D mtk_clk_register_gates(node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data, + &pdev->dev); if (r) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8195-apmixedsys.c index 0dfed6ec4d15..f967e2592dea 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -124,7 +124,8 @@ static int clk_mt8195_apmixed_probe(struct platform_dev= ice *pdev) if (r) goto free_apmixed_data; =20 - r =3D mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks)= , clk_data); + r =3D mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), + clk_data, &pdev->dev); if (r) goto unregister_plls; =20 diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index 93e96419da66..ed604d39f9d5 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1286,7 +1286,8 @@ static int clk_mt8195_topck_probe(struct platform_dev= ice *pdev) if (r) goto unregister_muxes; =20 - r =3D mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_cl= k_data); + r =3D mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), + top_clk_data, &pdev->dev); if (r) goto unregister_composite_divs; =20 diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/= clk-mt8195-vdo0.c index 07b46bfd5040..9ebad476e943 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -104,7 +104,8 @@ static int clk_mt8195_vdo0_probe(struct platform_device= *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_= data); + r =3D mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), + clk_data, &pdev->dev); if (r) goto free_vdo0_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/= clk-mt8195-vdo1.c index 835335b9d87b..a7a588f086c5 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -131,7 +131,8 @@ static int clk_mt8195_vdo1_probe(struct platform_device= *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates(node, vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_= data); + r =3D mtk_clk_register_gates(node, vdo1_clks, ARRAY_SIZE(vdo1_clks), + clk_data, &pdev->dev); if (r) goto free_vdo1_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/cl= k-mt8365-mm.c index 5c8bf18ab1f1..bc6bf0913452 100644 --- a/drivers/clk/mediatek/clk-mt8365-mm.c +++ b/drivers/clk/mediatek/clk-mt8365-mm.c @@ -81,9 +81,8 @@ static int clk_mt8365_mm_probe(struct platform_device *pd= ev) =20 clk_data =3D mtk_alloc_clk_data(CLK_MM_NR_CLK); =20 - ret =3D mtk_clk_register_gates_with_dev(node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data, - dev); + ret =3D mtk_clk_register_gates(node, mm_clks, + ARRAY_SIZE(mm_clks), clk_data, dev); if (ret) goto err_free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-m= t8365.c index adfecb618f10..5a43e5aad16e 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -1020,7 +1020,7 @@ static int clk_mt8365_infra_probe(struct platform_dev= ice *pdev) return -ENOMEM; =20 ret =3D mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks), - clk_data); + clk_data, &pdev->dev); if (ret) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8516-aud.c b/drivers/clk/mediatek/c= lk-mt8516-aud.c index 90f48068a8de..e3a7b3c939f3 100644 --- a/drivers/clk/mediatek/clk-mt8516-aud.c +++ b/drivers/clk/mediatek/clk-mt8516-aud.c @@ -54,7 +54,7 @@ static void __init mtk_audsys_init(struct device_node *no= de) =20 clk_data =3D mtk_alloc_clk_data(CLK_AUD_NR_CLK); =20 - mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data); + mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data, NU= LL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-m= t8516.c index b96db88893e2..a648ee463697 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -691,7 +691,7 @@ static void __init mtk_topckgen_init(struct device_node= *node) =20 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); - mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data); + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data, NU= LL); =20 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 3c1ac8d3010f..e04eef7e2b6f 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks, - clk_data, &pdev->dev); + r =3D mtk_clk_register_gates(node, mcd->clks, mcd->num_clks, + clk_data, &pdev->dev); if (r) goto free_data; =20 --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDF2FC4332F for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1671788593; bh=TEeukEcmEw2M1hk42gs6TWEg0hPcaPFVIEtr7muKTec=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n+sFVnLKV2g0PitOiTd7Tcty7AnIzOwj+3AuwbpZzqEKeF4FCTYhoa1TLKWoLueb1 jTg5T7SkJZaTpurkn4RAMWdBlype9JsnVnRdlqtxfwEKCkbatQUnG7H972pR9Ic2vI vQMLqj1ZRCM2Qf44Iu0/NsVeScUVTEKXdnMj1fnsB4XexdVAMkzfUTrRd23/5gTNeI m68bWK+v16l2hAieGhn4xGNH22to6s/3K1ZdOVZ32GKboyVM30SLz1tlozLgqvR25V SB8swy+5cF/3MwfMJuEr39uaq+YTIfd5G+CYRRgeKI+bwCjt7R7IcAUgLHbErJ/XKL pg3dHgweZbuGw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 04/23] clk: mediatek: cpumux: Propagate struct device where possible Date: Fri, 23 Dec 2022 10:42:40 +0100 Message-Id: <20221223094259.87373-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Take a pointer to a struct device in mtk_clk_register_cpumuxes() and propagate the same to mtk_clk_register_cpumux() =3D> clk_hw_register(). Even though runtime pm is unlikely to be used with CPU muxes, this helps with code consistency and possibly opens to commonization of some mtk_clk_register_(x) functions. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Markus Schneider-Pargmann Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-cpumux.c | 9 +++++---- drivers/clk/mediatek/clk-cpumux.h | 3 ++- drivers/clk/mediatek/clk-mt2701.c | 2 +- drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++- drivers/clk/mediatek/clk-mt7622.c | 2 +- drivers/clk/mediatek/clk-mt7629.c | 2 +- drivers/clk/mediatek/clk-mt8173.c | 2 +- 7 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-c= pumux.c index 25618eff6f2a..889534f7e97d 100644 --- a/drivers/clk/mediatek/clk-cpumux.c +++ b/drivers/clk/mediatek/clk-cpumux.c @@ -59,7 +59,7 @@ static const struct clk_ops clk_cpumux_ops =3D { =20 static struct clk_hw * mtk_clk_register_cpumux(const struct mtk_composite *mux, - struct regmap *regmap) + struct regmap *regmap, struct device *dev) { struct mtk_clk_cpumux *cpumux; int ret; @@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk_composite *mux, cpumux->regmap =3D regmap; cpumux->hw.init =3D &init; =20 - ret =3D clk_hw_register(NULL, &cpumux->hw); + ret =3D clk_hw_register(dev, &cpumux->hw); if (ret) { kfree(cpumux); return ERR_PTR(ret); @@ -104,7 +104,8 @@ static void mtk_clk_unregister_cpumux(struct clk_hw *hw) =20 int mtk_clk_register_cpumuxes(struct device_node *node, const struct mtk_composite *clks, int num, - struct clk_hw_onecell_data *clk_data) + struct clk_hw_onecell_data *clk_data, + struct device *dev) { int i; struct clk_hw *hw; @@ -125,7 +126,7 @@ int mtk_clk_register_cpumuxes(struct device_node *node, continue; } =20 - hw =3D mtk_clk_register_cpumux(mux, regmap); + hw =3D mtk_clk_register_cpumux(mux, regmap, dev); if (IS_ERR(hw)) { pr_err("Failed to register clk %s: %pe\n", mux->name, hw); diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-c= pumux.h index 325adbef25d1..0b7a59d4e0f2 100644 --- a/drivers/clk/mediatek/clk-cpumux.h +++ b/drivers/clk/mediatek/clk-cpumux.h @@ -13,7 +13,8 @@ struct mtk_composite; =20 int mtk_clk_register_cpumuxes(struct device_node *node, const struct mtk_composite *clks, int num, - struct clk_hw_onecell_data *clk_data); + struct clk_hw_onecell_data *clk_data, + struct device *dev); =20 void mtk_clk_unregister_cpumuxes(const struct mtk_composite *clks, int num, struct clk_hw_onecell_data *clk_data); diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index dff69fabb171..dcae25778817 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -770,7 +770,7 @@ static void __init mtk_infrasys_init_early(struct devic= e_node *node) infra_clk_data); =20 mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), - infra_clk_data); + infra_clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); diff --git a/drivers/clk/mediatek/clk-mt6795-infracfg.c b/drivers/clk/media= tek/clk-mt6795-infracfg.c index 4bbd2bfe2ec4..850b24666592 100644 --- a/drivers/clk/mediatek/clk-mt6795-infracfg.c +++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c @@ -106,7 +106,8 @@ static int clk_mt6795_infracfg_probe(struct platform_de= vice *pdev) if (ret) goto free_clk_data; =20 - ret =3D mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),= clk_data); + ret =3D mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), + clk_data, &pdev->dev); if (ret) goto unregister_gates; =20 diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index eab450fc824c..adf3b4535170 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -674,7 +674,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) clk_data, &pdev->dev); =20 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), - clk_data); + clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-m= t7629.c index 2daceeab7fc4..48bc4a6705fb 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -609,7 +609,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) clk_data, &pdev->dev); =20 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), - clk_data); + clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-m= t8173.c index dfb819dd1b1b..125b01b9e2ab 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -893,7 +893,7 @@ static void __init mtk_infrasys_init(struct device_node= *node) mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); =20 mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), - clk_data); + clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2610C4332F for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788594; bh=BJpeugsotBsLMOM6SD/PFiXg/IwoTPpVagtQf6A2tuU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DKh0btc7UyS0//R5o9OAZFgffMmuz4txIhkxzz2BkcBwpWgY8/+fFNX/19tT3mVzZ FUI29syb703TcFdfw0glNBR9YhvaLE1bcWavDbXZgsAwFl73mzzi7EPhuyPiR1Hkyl BiZHL4I4dDYLK3y5haD+MfIG8i4fjML4wtxEHEDB4Ccta+IQMIZCz60W1HB0EtnzXE N2UpB/m/ZSRnJtbMhCMvQrIkYZyel66tntqOQ7VHd83leo7ep9pm+iDIisf/k2tcAl +083ZDDUSCZTkSsvJKWuqdCiIYwWZUXjFDq1gmC4BG9y4mrGjaKU/S8XJuldarYIsf Or5arUwU63cZg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 05/23] clk: mediatek: clk-mtk: Propagate struct device for composites Date: Fri, 23 Dec 2022 10:42:41 +0100 Message-Id: <20221223094259.87373-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Like done for cpumux clocks, propagate struct device for composite clocks registered through clk-mtk helpers to be able to get runtime pm support for MTK clocks. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt2701.c | 4 ++-- drivers/clk/mediatek/clk-mt2712.c | 4 ++-- drivers/clk/mediatek/clk-mt6779.c | 4 ++-- drivers/clk/mediatek/clk-mt6795-pericfg.c | 2 +- drivers/clk/mediatek/clk-mt6795-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt6797.c | 2 +- drivers/clk/mediatek/clk-mt7622.c | 5 +++-- drivers/clk/mediatek/clk-mt7629.c | 4 ++-- drivers/clk/mediatek/clk-mt8135.c | 4 ++-- drivers/clk/mediatek/clk-mt8167.c | 4 ++-- drivers/clk/mediatek/clk-mt8173.c | 4 ++-- drivers/clk/mediatek/clk-mt8183.c | 6 +++--- drivers/clk/mediatek/clk-mt8186-mcu.c | 2 +- drivers/clk/mediatek/clk-mt8186-topckgen.c | 4 ++-- drivers/clk/mediatek/clk-mt8192.c | 4 ++-- drivers/clk/mediatek/clk-mt8195-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt8365.c | 5 +++-- drivers/clk/mediatek/clk-mt8516.c | 4 ++-- drivers/clk/mediatek/clk-mtk.c | 9 +++++---- drivers/clk/mediatek/clk-mtk.h | 3 ++- 20 files changed, 41 insertions(+), 37 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index dcae25778817..bd62acb5d697 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -684,7 +684,7 @@ static int mtk_topckgen_init(struct platform_device *pd= ev) clk_data); =20 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), - base, &mt2701_clk_lock, clk_data); + base, &mt2701_clk_lock, clk_data, &pdev->dev); =20 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt2701_clk_lock, clk_data); @@ -922,7 +922,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) clk_data, &pdev->dev); =20 mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, - &mt2701_clk_lock, clk_data); + &mt2701_clk_lock, clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index 24ec3384c429..5cadcf6ca9b7 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1347,7 +1347,7 @@ static int clk_mt2712_top_probe(struct platform_devic= e *pdev) top_clk_data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt2712_clk_lock, top_clk_data); + &mt2712_clk_lock, top_clk_data, &pdev->dev); mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt2712_clk_lock, top_clk_data); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), @@ -1422,7 +1422,7 @@ static int clk_mt2712_mcu_probe(struct platform_devic= e *pdev) clk_data =3D mtk_alloc_clk_data(CLK_MCU_NR_CLK); =20 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, - &mt2712_clk_lock, clk_data); + &mt2712_clk_lock, clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-m= t6779.c index 622a2fc6c167..825f2f57e868 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1248,10 +1248,10 @@ static int clk_mt6779_top_probe(struct platform_dev= ice *pdev) node, &mt6779_clk_lock, clk_data); =20 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), - base, &mt6779_clk_lock, clk_data); + base, &mt6779_clk_lock, clk_data, &pdev->dev); =20 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), - base, &mt6779_clk_lock, clk_data); + base, &mt6779_clk_lock, clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt6795-pericfg.c b/drivers/clk/mediat= ek/clk-mt6795-pericfg.c index 479a8abcb80b..1fc80bc1592b 100644 --- a/drivers/clk/mediatek/clk-mt6795-pericfg.c +++ b/drivers/clk/mediatek/clk-mt6795-pericfg.c @@ -115,7 +115,7 @@ static int clk_mt6795_pericfg_probe(struct platform_dev= ice *pdev) goto free_clk_data; =20 ret =3D mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), bas= e, - &mt6795_peri_clk_lock, clk_data); + &mt6795_peri_clk_lock, clk_data, &pdev->dev); if (ret) goto unregister_gates; =20 diff --git a/drivers/clk/mediatek/clk-mt6795-topckgen.c b/drivers/clk/media= tek/clk-mt6795-topckgen.c index 8b8307635a35..bb232e1726f1 100644 --- a/drivers/clk/mediatek/clk-mt6795-topckgen.c +++ b/drivers/clk/mediatek/clk-mt6795-topckgen.c @@ -558,7 +558,7 @@ static int clk_mt6795_topckgen_probe(struct platform_de= vice *pdev) goto unregister_factors; =20 ret =3D mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs= ), base, - &mt6795_top_clk_lock, clk_data); + &mt6795_top_clk_lock, clk_data, &pdev->dev); if (ret) goto unregister_muxes; =20 diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-m= t6797.c index 250ac8bd6a3c..581bc7d9f66d 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -397,7 +397,7 @@ static int mtk_topckgen_init(struct platform_device *pd= ev) clk_data); =20 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt6797_clk_lock, clk_data); + &mt6797_clk_lock, clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index adf3b4535170..fb4e2552ba76 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -647,7 +647,8 @@ static int mtk_topckgen_init(struct platform_device *pd= ev) clk_data); =20 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), - base, &mt7622_clk_lock, clk_data); + base, &mt7622_clk_lock, clk_data, + &pdev->dev); =20 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt7622_clk_lock, clk_data); @@ -725,7 +726,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) clk_data, &pdev->dev); =20 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, - &mt7622_clk_lock, clk_data); + &mt7622_clk_lock, clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-m= t7629.c index 48bc4a6705fb..890f1944565e 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -589,7 +589,7 @@ static int mtk_topckgen_init(struct platform_device *pd= ev) clk_data); =20 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), - base, &mt7629_clk_lock, clk_data); + base, &mt7629_clk_lock, clk_data, &pdev->dev); =20 clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); @@ -632,7 +632,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) clk_data, &pdev->dev); =20 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, - &mt7629_clk_lock, clk_data); + &mt7629_clk_lock, clk_data, &pdev->dev); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 7193ab38090d..253fe271ee97 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -549,7 +549,7 @@ static void __init mtk_topckgen_init(struct device_node= *node) mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_= data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8135_clk_lock, clk_data); + &mt8135_clk_lock, clk_data, NULL); =20 clk_prepare_enable(clk_data->hws[CLK_TOP_CCI_SEL]->clk); =20 @@ -598,7 +598,7 @@ static void __init mtk_pericfg_init(struct device_node = *node) mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), clk_data, NULL); mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, - &mt8135_clk_lock, clk_data); + &mt8135_clk_lock, clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-m= t8167.c index b150f893a4b8..cc064e98643a 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -941,7 +941,7 @@ static void __init mtk_topckgen_init(struct device_node= *node) =20 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8167_clk_lock, clk_data); + &mt8167_clk_lock, clk_data, NULL); mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8167_clk_lock, clk_data); =20 @@ -967,7 +967,7 @@ static void __init mtk_infracfg_init(struct device_node= *node) clk_data =3D mtk_alloc_clk_data(CLK_IFR_NR_CLK); =20 mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base, - &mt8167_clk_lock, clk_data); + &mt8167_clk_lock, clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-m= t8173.c index 125b01b9e2ab..617f68274004 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -870,7 +870,7 @@ static void __init mtk_topckgen_init(struct device_node= *node) mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8173_clk_lock, clk_data); + &mt8173_clk_lock, clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -921,7 +921,7 @@ static void __init mtk_pericfg_init(struct device_node = *node) mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), clk_data, NULL); mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, - &mt8173_clk_lock, clk_data); + &mt8173_clk_lock, clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index f99c092476c2..194906ca4b5b 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1170,10 +1170,10 @@ static int clk_mt8183_top_probe(struct platform_dev= ice *pdev) node, &mt8183_clk_lock, top_clk_data); =20 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), - base, &mt8183_clk_lock, top_clk_data); + base, &mt8183_clk_lock, top_clk_data, &pdev->dev); =20 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), - base, &mt8183_clk_lock, top_clk_data); + base, &mt8183_clk_lock, top_clk_data, &pdev->dev); =20 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data, &pdev->dev); @@ -1237,7 +1237,7 @@ static int clk_mt8183_mcu_probe(struct platform_devic= e *pdev) clk_data =3D mtk_alloc_clk_data(CLK_MCU_NR_CLK); =20 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, - &mt8183_clk_lock, clk_data); + &mt8183_clk_lock, clk_data, &pdev->dev); =20 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt8186-mcu.c b/drivers/clk/mediatek/c= lk-mt8186-mcu.c index dfc305c1fc5d..c4a5557cb830 100644 --- a/drivers/clk/mediatek/clk-mt8186-mcu.c +++ b/drivers/clk/mediatek/clk-mt8186-mcu.c @@ -66,7 +66,7 @@ static int clk_mt8186_mcu_probe(struct platform_device *p= dev) } =20 r =3D mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, - NULL, clk_data); + NULL, clk_data, &pdev->dev); if (r) goto free_mcu_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/media= tek/clk-mt8186-topckgen.c index c2beda7ef976..b79954a42481 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -743,12 +743,12 @@ static int clk_mt8186_topck_probe(struct platform_dev= ice *pdev) goto unregister_factors; =20 r =3D mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8186_clk_lock, clk_data); + &mt8186_clk_lock, clk_data, &pdev->dev); if (r) goto unregister_muxes; =20 r =3D mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs),= base, - &mt8186_clk_lock, clk_data); + &mt8186_clk_lock, clk_data, &pdev->dev); if (r) goto unregister_composite_muxes; =20 diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index e1b625b86911..27ad629062c4 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1118,12 +1118,12 @@ static int clk_mt8192_top_probe(struct platform_dev= ice *pdev) goto unregister_factors; =20 r =3D mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8192_clk_lock, top_clk_data); + &mt8192_clk_lock, top_clk_data, &pdev->dev); if (r) goto unregister_muxes; =20 r =3D mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs),= base, - &mt8192_clk_lock, top_clk_data); + &mt8192_clk_lock, top_clk_data, &pdev->dev); if (r) goto unregister_top_composites; =20 diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index ed604d39f9d5..437c12d19b03 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1282,7 +1282,7 @@ static int clk_mt8195_topck_probe(struct platform_dev= ice *pdev) goto unregister_muxes; =20 r =3D mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs),= base, - &mt8195_clk_lock, top_clk_data); + &mt8195_clk_lock, top_clk_data, &pdev->dev); if (r) goto unregister_muxes; =20 diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-m= t8365.c index 5a43e5aad16e..00c15f89a5f6 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -954,7 +954,7 @@ static int clk_mt8365_top_probe(struct platform_device = *pdev) =20 ret =3D mtk_clk_register_composites(top_misc_mux_gates, ARRAY_SIZE(top_misc_mux_gates), base, - &mt8365_clk_lock, clk_data); + &mt8365_clk_lock, clk_data, &pdev->dev); if (ret) goto unregister_muxes; =20 @@ -1081,7 +1081,8 @@ static int clk_mt8365_mcu_probe(struct platform_devic= e *pdev) return -ENOMEM; =20 ret =3D mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), - base, &mt8365_clk_lock, clk_data); + base, &mt8365_clk_lock, clk_data, + &pdev->dev); if (ret) goto free_clk_data; =20 diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-m= t8516.c index a648ee463697..b50b2d1387b6 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -695,7 +695,7 @@ static void __init mtk_topckgen_init(struct device_node= *node) =20 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8516_clk_lock, clk_data); + &mt8516_clk_lock, clk_data, NULL); mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8516_clk_lock, clk_data); =20 @@ -721,7 +721,7 @@ static void __init mtk_infracfg_init(struct device_node= *node) clk_data =3D mtk_alloc_clk_data(CLK_IFR_NR_CLK); =20 mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base, - &mt8516_clk_lock, clk_data); + &mt8516_clk_lock, clk_data, NULL); =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index e04eef7e2b6f..a1ab34305b95 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -198,7 +198,7 @@ void mtk_clk_unregister_factors(const struct mtk_fixed_= factor *clks, int num, EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors); =20 static struct clk_hw *mtk_clk_register_composite(const struct mtk_composit= e *mc, - void __iomem *base, spinlock_t *lock) + void __iomem *base, spinlock_t *lock, struct device *dev) { struct clk_hw *hw; struct clk_mux *mux =3D NULL; @@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_composite(const = struct mtk_composite *mc, div_ops =3D &clk_divider_ops; } =20 - hw =3D clk_hw_register_composite(NULL, mc->name, parent_names, num_parent= s, + hw =3D clk_hw_register_composite(dev, mc->name, parent_names, num_parents, mux_hw, mux_ops, div_hw, div_ops, gate_hw, gate_ops, @@ -310,7 +310,8 @@ static void mtk_clk_unregister_composite(struct clk_hw = *hw) =20 int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, - struct clk_hw_onecell_data *clk_data) + struct clk_hw_onecell_data *clk_data, + struct device *dev) { struct clk_hw *hw; int i; @@ -327,7 +328,7 @@ int mtk_clk_register_composites(const struct mtk_compos= ite *mcs, int num, continue; } =20 - hw =3D mtk_clk_register_composite(mc, base, lock); + hw =3D mtk_clk_register_composite(mc, base, lock, dev); =20 if (IS_ERR(hw)) { pr_err("Failed to register clk %s: %pe\n", mc->name, diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f2db6b57d5b5..15122504c02d 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -156,7 +156,8 @@ struct mtk_composite { =20 int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, - struct clk_hw_onecell_data *clk_data); + struct clk_hw_onecell_data *clk_data, + struct device *dev); void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int nu= m, struct clk_hw_onecell_data *clk_data); =20 --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06205C4332F for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788595; bh=ty48ueu2BRL62kzjZYVVfEEdsnCwD4EJP8TQYVQJie4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lGvbpEQpl/I9I3E4Z3oa44NRiq2VfxPFtsP4S83fnHt3pDPTguqZ9R9gW59+pXrc6 rOJhkhAlEIfSI3VqKSvHALQytuhr4iZZxnnUv67fsNKCSNwwSaHMPfBkBv7xnhAs5f VoOBgDUPL7VAyYWrsdnpvWmFw1tMTsRDahNzDD+6plVWEEmaTBjdbe6sJoFmimoNDy C+1mNLv/kAhNZ0d35I1vAKRunvGjiZZxrdqWEPabpnYhmJf6EgFj4YLbvf8vurQtxx WxQhTQ9qfBKIijvw3yRtN6igqBzdpbILTsc+Rl+FB7HOfgAWAM5HhHYmD0B8RbabdS stsoRKaftGiGg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 06/23] clk: mediatek: clk-mux: Propagate struct device for mtk-mux Date: Fri, 23 Dec 2022 10:42:42 +0100 Message-Id: <20221223094259.87373-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Like done for other clocks, propagate struct device for mtk mux clocks registered through clk-mux helpers to enable runtime pm support. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt6765.c | 2 +- drivers/clk/mediatek/clk-mt6779.c | 2 +- drivers/clk/mediatek/clk-mt6795-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt7986-infracfg.c | 2 +- drivers/clk/mediatek/clk-mt7986-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt8183.c | 2 +- drivers/clk/mediatek/clk-mt8186-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt8192.c | 2 +- drivers/clk/mediatek/clk-mt8195-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt8365.c | 2 +- drivers/clk/mediatek/clk-mux.c | 9 +++++---- drivers/clk/mediatek/clk-mux.h | 3 ++- 12 files changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-m= t6765.c index 7401693ef472..30d0fe9acb37 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -827,7 +827,7 @@ static int clk_mt6765_top_probe(struct platform_device = *pdev) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt6765_clk_lock, clk_data); + &mt6765_clk_lock, clk_data, &pdev->dev); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data, &pdev->dev); =20 diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-m= t6779.c index 825f2f57e868..6d1fb19be77b 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1245,7 +1245,7 @@ static int clk_mt6779_top_probe(struct platform_devic= e *pdev) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); =20 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), - node, &mt6779_clk_lock, clk_data); + node, &mt6779_clk_lock, clk_data, &pdev->dev); =20 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), base, &mt6779_clk_lock, clk_data, &pdev->dev); diff --git a/drivers/clk/mediatek/clk-mt6795-topckgen.c b/drivers/clk/media= tek/clk-mt6795-topckgen.c index bb232e1726f1..19440fe5460d 100644 --- a/drivers/clk/mediatek/clk-mt6795-topckgen.c +++ b/drivers/clk/mediatek/clk-mt6795-topckgen.c @@ -553,7 +553,7 @@ static int clk_mt6795_topckgen_probe(struct platform_de= vice *pdev) goto unregister_fixed_clks; =20 ret =3D mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt6795_top_clk_lock, clk_data); + &mt6795_top_clk_lock, clk_data, &pdev->dev); if (ret) goto unregister_factors; =20 diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/media= tek/clk-mt7986-infracfg.c index 24947ccdb70a..fe64a226c4ac 100644 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -191,7 +191,7 @@ static int clk_mt7986_infracfg_probe(struct platform_de= vice *pdev) =20 mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, - &mt7986_clk_lock, clk_data); + &mt7986_clk_lock, clk_data, &pdev->dev); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data, &pdev->dev); =20 diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/media= tek/clk-mt7986-topckgen.c index de5121cf2877..d7df9585787f 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -304,7 +304,7 @@ static int clk_mt7986_topckgen_probe(struct platform_de= vice *pdev) clk_data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt7986_clk_lock, clk_data); + &mt7986_clk_lock, clk_data, &pdev->dev); =20 clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk); diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 194906ca4b5b..10a82b542376 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1167,7 +1167,7 @@ static int clk_mt8183_top_probe(struct platform_devic= e *pdev) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); =20 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), - node, &mt8183_clk_lock, top_clk_data); + node, &mt8183_clk_lock, top_clk_data, &pdev->dev); =20 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), base, &mt8183_clk_lock, top_clk_data, &pdev->dev); diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/media= tek/clk-mt8186-topckgen.c index b79954a42481..d05143891b69 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -738,7 +738,7 @@ static int clk_mt8186_topck_probe(struct platform_devic= e *pdev) goto unregister_fixed_clks; =20 r =3D mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), no= de, - &mt8186_clk_lock, clk_data); + &mt8186_clk_lock, clk_data, &pdev->dev); if (r) goto unregister_factors; =20 diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 27ad629062c4..3ca068a4c552 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1113,7 +1113,7 @@ static int clk_mt8192_top_probe(struct platform_devic= e *pdev) goto unregister_early_factors; =20 r =3D mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), no= de, - &mt8192_clk_lock, top_clk_data); + &mt8192_clk_lock, top_clk_data, &pdev->dev); if (r) goto unregister_factors; =20 diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/media= tek/clk-mt8195-topckgen.c index 437c12d19b03..6d6a11d4a536 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1263,7 +1263,7 @@ static int clk_mt8195_topck_probe(struct platform_dev= ice *pdev) goto unregister_fixed_clks; =20 r =3D mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), no= de, - &mt8195_clk_lock, top_clk_data); + &mt8195_clk_lock, top_clk_data, &pdev->dev); if (r) goto unregister_factors; =20 diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-m= t8365.c index 00c15f89a5f6..abb719b4661a 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -948,7 +948,7 @@ static int clk_mt8365_top_probe(struct platform_device = *pdev) goto unregister_fixed_clks; =20 ret =3D mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt8365_clk_lock, clk_data); + &mt8365_clk_lock, clk_data, &pdev->dev); if (ret) goto unregister_factors; =20 diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index ba1720b9e231..cd37abdf47c9 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -156,7 +156,7 @@ EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops); =20 static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux, struct regmap *regmap, - spinlock_t *lock) + spinlock_t *lock, struct device *dev) { struct mtk_clk_mux *clk_mux; struct clk_init_data init =3D {}; @@ -177,7 +177,7 @@ static struct clk_hw *mtk_clk_register_mux(const struct= mtk_mux *mux, clk_mux->lock =3D lock; clk_mux->hw.init =3D &init; =20 - ret =3D clk_hw_register(NULL, &clk_mux->hw); + ret =3D clk_hw_register(dev, &clk_mux->hw); if (ret) { kfree(clk_mux); return ERR_PTR(ret); @@ -201,7 +201,8 @@ static void mtk_clk_unregister_mux(struct clk_hw *hw) int mtk_clk_register_muxes(const struct mtk_mux *muxes, int num, struct device_node *node, spinlock_t *lock, - struct clk_hw_onecell_data *clk_data) + struct clk_hw_onecell_data *clk_data, + struct device *dev) { struct regmap *regmap; struct clk_hw *hw; @@ -222,7 +223,7 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, continue; } =20 - hw =3D mtk_clk_register_mux(mux, regmap, lock); + hw =3D mtk_clk_register_mux(mux, regmap, lock, dev); =20 if (IS_ERR(hw)) { pr_err("Failed to register clk %s: %pe\n", mux->name, diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index 83ff420f4ebe..3fe07719e5c6 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -86,7 +86,8 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; int mtk_clk_register_muxes(const struct mtk_mux *muxes, int num, struct device_node *node, spinlock_t *lock, - struct clk_hw_onecell_data *clk_data); + struct clk_hw_onecell_data *clk_data, + struct device *dev); =20 void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num, struct clk_hw_onecell_data *clk_data); --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B23F8C3DA6E for ; Fri, 23 Dec 2022 09:43:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236216AbiLWJn5 (ORCPT ); Fri, 23 Dec 2022 04:43:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236126AbiLWJnT (ORCPT ); Fri, 23 Dec 2022 04:43:19 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69D20379C6; Fri, 23 Dec 2022 01:43:18 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0EB5A6602CE0; Fri, 23 Dec 2022 09:43:16 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788597; bh=K3qkzfY6G2DncdZI0kKDSL9TE5yrQJlLDsPQh9qExmY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h7rfYJziYRTHZ0eQUwgwBzY8/kMqSYFctHhDbsLYwP9y+abK/xGYat6S3B1xP8Aji RURnwCX9FzTzYvhgCloZxW5ZVmgSiYQsb85RCCrjM6mtrxq688whSy+BkHlguRMrHP OQrZLpC8ouLxLML5ryoVfuAOpN1RJFn+tejNxuSaqY+HBAAReO0dfUrmLuSCfkhKXL yI5h7DocKpQ4cCE1t3phW3PDvBoAqxQ4dGibUGcfZWnbNeX5/Vvxeo9gSGdz3Te4WU oQUJrODFfsfSZwEGqqeutAMV9Go/029L+U7tI6Dc5xNLMJnrKMoBhoCZSDc8aCW4g8 RUZivulr8ltjA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 07/23] clk: mediatek: clk-mtk: Add dummy clock ops Date: Fri, 23 Dec 2022 10:42:43 +0100 Message-Id: <20221223094259.87373-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to migrate some (few) old clock drivers to the common mtk_clk_simple_probe() function, add dummy clock ops to be able to insert a dummy clock with ID 0 at the beginning of the list. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Miles Chen =20 Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mtk.c | 15 +++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index a1ab34305b95..d05364e17e95 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -18,6 +18,21 @@ #include "clk-mtk.h" #include "clk-gate.h" =20 +const struct mtk_gate_regs cg_regs_dummy =3D { 0, 0, 0 }; + +static int mtk_clk_dummy_enable(struct clk_hw *hw) +{ + return 0; +} + +static void mtk_clk_dummy_disable(struct clk_hw *hw) { } + +const struct clk_ops mtk_clk_dummy_ops =3D { + .enable =3D mtk_clk_dummy_enable, + .disable =3D mtk_clk_dummy_disable, +}; +EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops); + static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data, unsigned int clk_num) { diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 15122504c02d..dd43235285db 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -22,6 +22,25 @@ =20 struct platform_device; =20 +/* + * We need the clock IDs to start from zero but to maintain devicetree + * backwards compatibility we can't change bindings to start from zero. + * Only a few platforms are affected, so we solve issues given by the + * commonized MTK clocks probe function(s) by adding a dummy clock at + * the beginning where needed. + */ +#define CLK_DUMMY 0 + +extern const struct clk_ops mtk_clk_dummy_ops; +extern const struct mtk_gate_regs cg_regs_dummy; + +#define GATE_DUMMY(_id, _name) { \ + .id =3D _id, \ + .name =3D _name, \ + .regs =3D &cg_regs_dummy, \ + .ops =3D &mtk_clk_dummy_ops, \ + } + struct mtk_fixed_clk { int id; const char *name; --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA816C4332F for ; Fri, 23 Dec 2022 09:44:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236000AbiLWJoG (ORCPT ); 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b=f+YXAXl3bBhx2arl+3/9PBNym83Sf3n1R232xc66spDcHgmnmPR7/w7+YVVYMI37H DuzSU4DkAbieAD00d4x/+yDQfZ+cww8Yn6uWS86IeFi6b5qJpbkvyK1FZaX+/XcW6H ExEHvLjGDAQDQVMNgIc5+8v6HtHAySA82rB538bAYGW8p+tNwB2gdNYG779usiCotg D7n8qCjXTt4hT3Oz2J2VmYVsq4Sr/wG3eKvx0Q3k9qJkMpFPUXAqcU++vvRvbkGu1m uzge/gLq0/PXALvb6Elmb+QuWlfvtXyKB/2solZx4l+TKTm+75qsIQ5gsc4HJezcGW i5pBbbXBqVe5w== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 08/23] clk: mediatek: mt8173: Migrate to platform driver and common probe Date: Fri, 23 Dec 2022 10:42:44 +0100 Message-Id: <20221223094259.87373-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver is using CLK_OF_DECLARE() for all clocks: while this definitely works, it's not preferred as this makes it impossible to compile non boot critical clock drivers as modules and to take advantage of clock controller Runtime PM. As a preparation for a larger cleanup, migrate all of the clock controller drivers for MT8173 to platform_driver and use the common mtk_clk_simple_probe() where possible. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8173.c | 478 +++++++++++++++++------------- 1 file changed, 273 insertions(+), 205 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-m= t8173.c index 617f68274004..70cdc0719658 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "clk-cpumux.h" #include "clk-gate.h" @@ -15,6 +17,9 @@ =20 #include =20 +#define REGOFF_REF2USB 0x8 +#define REGOFF_HDMI_REF 0x40 + /* * For some clocks, we don't care what their actual rates are. And these * clocks may change their rate on different products or different scenari= os. @@ -24,7 +29,7 @@ =20 static DEFINE_SPINLOCK(mt8173_clk_lock); =20 -static const struct mtk_fixed_clk fixed_clks[] __initconst =3D { +static const struct mtk_fixed_clk fixed_clks[] =3D { FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE), FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ= ), FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE), @@ -33,7 +38,7 @@ static const struct mtk_fixed_clk fixed_clks[] __initcons= t =3D { FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE), }; =20 -static const struct mtk_fixed_factor top_divs[] __initconst =3D { +static const struct mtk_fixed_factor top_divs[] =3D { FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2), FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3), =20 @@ -129,7 +134,7 @@ static const struct mtk_fixed_factor top_divs[] __initc= onst =3D { FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4), }; =20 -static const char * const axi_parents[] __initconst =3D { +static const char * const axi_parents[] =3D { "clk26m", "syspll1_d2", "syspll_d5", @@ -140,17 +145,17 @@ static const char * const axi_parents[] __initconst = =3D { "dmpll_d4" }; =20 -static const char * const mem_parents[] __initconst =3D { +static const char * const mem_parents[] =3D { "clk26m", "dmpll_ck" }; =20 -static const char * const ddrphycfg_parents[] __initconst =3D { +static const char * const ddrphycfg_parents[] =3D { "clk26m", "syspll1_d8" }; =20 -static const char * const mm_parents[] __initconst =3D { +static const char * const mm_parents[] =3D { "clk26m", "vencpll_d2", "main_h364m", @@ -162,14 +167,14 @@ static const char * const mm_parents[] __initconst = =3D { "dmpll_d2" }; =20 -static const char * const pwm_parents[] __initconst =3D { +static const char * const pwm_parents[] =3D { "clk26m", "univpll2_d4", "univpll3_d2", "univpll1_d4" }; =20 -static const char * const vdec_parents[] __initconst =3D { +static const char * const vdec_parents[] =3D { "clk26m", "vcodecpll_ck", "tvdpll_445p5m", @@ -182,7 +187,7 @@ static const char * const vdec_parents[] __initconst = =3D { "dmpll_d4" }; =20 -static const char * const venc_parents[] __initconst =3D { +static const char * const venc_parents[] =3D { "clk26m", "vcodecpll_ck", "tvdpll_445p5m", @@ -195,7 +200,7 @@ static const char * const venc_parents[] __initconst = =3D { "dmpll_d4" }; =20 -static const char * const mfg_parents[] __initconst =3D { +static const char * const mfg_parents[] =3D { "clk26m", "mmpll_ck", "dmpll_ck", @@ -214,7 +219,7 @@ static const char * const mfg_parents[] __initconst =3D= { "univpll2_d2" }; =20 -static const char * const camtg_parents[] __initconst =3D { +static const char * const camtg_parents[] =3D { "clk26m", "univpll_d26", "univpll2_d2", @@ -223,12 +228,12 @@ static const char * const camtg_parents[] __initconst= =3D { "univpll1_d4" }; =20 -static const char * const uart_parents[] __initconst =3D { +static const char * const uart_parents[] =3D { "clk26m", "univpll2_d8" }; =20 -static const char * const spi_parents[] __initconst =3D { +static const char * const spi_parents[] =3D { "clk26m", "syspll3_d2", "syspll1_d4", @@ -238,20 +243,20 @@ static const char * const spi_parents[] __initconst = =3D { "univpll1_d8" }; =20 -static const char * const usb20_parents[] __initconst =3D { +static const char * const usb20_parents[] =3D { "clk26m", "univpll1_d8", "univpll3_d4" }; =20 -static const char * const usb30_parents[] __initconst =3D { +static const char * const usb30_parents[] =3D { "clk26m", "univpll3_d2", "usb_syspll_125m", "univpll2_d4" }; =20 -static const char * const msdc50_0_h_parents[] __initconst =3D { +static const char * const msdc50_0_h_parents[] =3D { "clk26m", "syspll1_d2", "syspll2_d2", @@ -260,7 +265,7 @@ static const char * const msdc50_0_h_parents[] __initco= nst =3D { "univpll1_d4" }; =20 -static const char * const msdc50_0_parents[] __initconst =3D { +static const char * const msdc50_0_parents[] =3D { "clk26m", "msdcpll_ck", "msdcpll_d2", @@ -278,7 +283,7 @@ static const char * const msdc50_0_parents[] __initcons= t =3D { "msdcpll2_d4" }; =20 -static const char * const msdc30_1_parents[] __initconst =3D { +static const char * const msdc30_1_parents[] =3D { "clk26m", "univpll2_d2", "msdcpll_d4", @@ -289,7 +294,7 @@ static const char * const msdc30_1_parents[] __initcons= t =3D { "vencpll_d4" }; =20 -static const char * const msdc30_2_parents[] __initconst =3D { +static const char * const msdc30_2_parents[] =3D { "clk26m", "univpll2_d2", "msdcpll_d4", @@ -300,7 +305,7 @@ static const char * const msdc30_2_parents[] __initcons= t =3D { "vencpll_d2" }; =20 -static const char * const msdc30_3_parents[] __initconst =3D { +static const char * const msdc30_3_parents[] =3D { "clk26m", "msdcpll2_ck", "msdcpll2_d2", @@ -317,14 +322,14 @@ static const char * const msdc30_3_parents[] __initco= nst =3D { "msdcpll_d4" }; =20 -static const char * const audio_parents[] __initconst =3D { +static const char * const audio_parents[] =3D { "clk26m", "syspll3_d4", "syspll4_d4", "syspll1_d16" }; =20 -static const char * const aud_intbus_parents[] __initconst =3D { +static const char * const aud_intbus_parents[] =3D { "clk26m", "syspll1_d4", "syspll4_d2", @@ -334,7 +339,7 @@ static const char * const aud_intbus_parents[] __initco= nst =3D { "dmpll_d8" }; =20 -static const char * const pmicspi_parents[] __initconst =3D { +static const char * const pmicspi_parents[] =3D { "clk26m", "syspll1_d8", "syspll3_d4", @@ -345,7 +350,7 @@ static const char * const pmicspi_parents[] __initconst= =3D { "dmpll_d16" }; =20 -static const char * const scp_parents[] __initconst =3D { +static const char * const scp_parents[] =3D { "clk26m", "syspll1_d2", "univpll_d5", @@ -354,14 +359,14 @@ static const char * const scp_parents[] __initconst = =3D { "dmpll_d4" }; =20 -static const char * const atb_parents[] __initconst =3D { +static const char * const atb_parents[] =3D { "clk26m", "syspll1_d2", "univpll_d5", "dmpll_d2" }; =20 -static const char * const venc_lt_parents[] __initconst =3D { +static const char * const venc_lt_parents[] =3D { "clk26m", "univpll_d3", "vcodecpll_ck", @@ -376,7 +381,7 @@ static const char * const venc_lt_parents[] __initconst= =3D { "dmpll_ck" }; =20 -static const char * const dpi0_parents[] __initconst =3D { +static const char * const dpi0_parents[] =3D { "clk26m", "tvdpll_d2", "tvdpll_d4", @@ -386,13 +391,13 @@ static const char * const dpi0_parents[] __initconst = =3D { "tvdpll_d16" }; =20 -static const char * const irda_parents[] __initconst =3D { +static const char * const irda_parents[] =3D { "clk26m", "univpll2_d4", "syspll2_d4" }; =20 -static const char * const cci400_parents[] __initconst =3D { +static const char * const cci400_parents[] =3D { "clk26m", "vencpll_ck", "armca7pll_754m", @@ -403,41 +408,41 @@ static const char * const cci400_parents[] __initcons= t =3D { "dmpll_ck" }; =20 -static const char * const aud_1_parents[] __initconst =3D { +static const char * const aud_1_parents[] =3D { "clk26m", "apll1_ck", "univpll2_d4", "univpll2_d8" }; =20 -static const char * const aud_2_parents[] __initconst =3D { +static const char * const aud_2_parents[] =3D { "clk26m", "apll2_ck", "univpll2_d4", "univpll2_d8" }; =20 -static const char * const mem_mfg_in_parents[] __initconst =3D { +static const char * const mem_mfg_in_parents[] =3D { "clk26m", "mmpll_ck", "dmpll_ck", "clk26m" }; =20 -static const char * const axi_mfg_in_parents[] __initconst =3D { +static const char * const axi_mfg_in_parents[] =3D { "clk26m", "axi_sel", "dmpll_d2" }; =20 -static const char * const scam_parents[] __initconst =3D { +static const char * const scam_parents[] =3D { "clk26m", "syspll3_d2", "univpll2_d4", "dmpll_d4" }; =20 -static const char * const spinfi_ifr_parents[] __initconst =3D { +static const char * const spinfi_ifr_parents[] =3D { "clk26m", "univpll2_d8", "univpll3_d4", @@ -448,14 +453,14 @@ static const char * const spinfi_ifr_parents[] __init= const =3D { "univpll1_d4" }; =20 -static const char * const hdmi_parents[] __initconst =3D { +static const char * const hdmi_parents[] =3D { "clk26m", "hdmitx_dig_cts", "hdmitxpll_d2", "hdmitxpll_d3" }; =20 -static const char * const dpilvds_parents[] __initconst =3D { +static const char * const dpilvds_parents[] =3D { "clk26m", "lvdspll", "lvdspll_d2", @@ -464,7 +469,7 @@ static const char * const dpilvds_parents[] __initconst= =3D { "fpc_ck" }; =20 -static const char * const msdc50_2_h_parents[] __initconst =3D { +static const char * const msdc50_2_h_parents[] =3D { "clk26m", "syspll1_d2", "syspll2_d2", @@ -473,72 +478,72 @@ static const char * const msdc50_2_h_parents[] __init= const =3D { "univpll1_d4" }; =20 -static const char * const hdcp_parents[] __initconst =3D { +static const char * const hdcp_parents[] =3D { "clk26m", "syspll4_d2", "syspll3_d4", "univpll2_d4" }; =20 -static const char * const hdcp_24m_parents[] __initconst =3D { +static const char * const hdcp_24m_parents[] =3D { "clk26m", "univpll_d26", "univpll_d52", "univpll2_d8" }; =20 -static const char * const rtc_parents[] __initconst =3D { +static const char * const rtc_parents[] =3D { "clkrtc_int", "clkrtc_ext", "clk26m", "univpll3_d8" }; =20 -static const char * const i2s0_m_ck_parents[] __initconst =3D { +static const char * const i2s0_m_ck_parents[] =3D { "apll1_div1", "apll2_div1" }; =20 -static const char * const i2s1_m_ck_parents[] __initconst =3D { +static const char * const i2s1_m_ck_parents[] =3D { "apll1_div2", "apll2_div2" }; =20 -static const char * const i2s2_m_ck_parents[] __initconst =3D { +static const char * const i2s2_m_ck_parents[] =3D { "apll1_div3", "apll2_div3" }; =20 -static const char * const i2s3_m_ck_parents[] __initconst =3D { +static const char * const i2s3_m_ck_parents[] =3D { "apll1_div4", "apll2_div4" }; =20 -static const char * const i2s3_b_ck_parents[] __initconst =3D { +static const char * const i2s3_b_ck_parents[] =3D { "apll1_div5", "apll2_div5" }; =20 -static const char * const ca53_parents[] __initconst =3D { +static const char * const ca53_parents[] =3D { "clk26m", "armca7pll", "mainpll", "univpll" }; =20 -static const char * const ca72_parents[] __initconst =3D { +static const char * const ca72_parents[] =3D { "clk26m", "armca15pll", "mainpll", "univpll" }; =20 -static const struct mtk_composite cpu_muxes[] __initconst =3D { +static const struct mtk_composite cpu_muxes[] =3D { MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), }; =20 -static const struct mtk_composite top_muxes[] __initconst =3D { +static const struct mtk_composite top_muxes[] =3D { /* CLK_CFG_0 */ MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1), @@ -614,7 +619,7 @@ static const struct mtk_composite top_muxes[] __initcon= st =3D { MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1), }; =20 -static const struct mtk_gate_regs infra_cg_regs __initconst =3D { +static const struct mtk_gate_regs infra_cg_regs =3D { .set_ofs =3D 0x0040, .clr_ofs =3D 0x0044, .sta_ofs =3D 0x0048, @@ -629,7 +634,7 @@ static const struct mtk_gate_regs infra_cg_regs __initc= onst =3D { .ops =3D &mtk_clk_gate_ops_setclr, \ } =20 -static const struct mtk_gate infra_clks[] __initconst =3D { +static const struct mtk_gate infra_clks[] =3D { GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1), GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5), @@ -643,17 +648,17 @@ static const struct mtk_gate infra_clks[] __initconst= =3D { GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), }; =20 -static const struct mtk_fixed_factor infra_divs[] __initconst =3D { +static const struct mtk_fixed_factor infra_early_divs[] =3D { FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), }; =20 -static const struct mtk_gate_regs peri0_cg_regs __initconst =3D { +static const struct mtk_gate_regs peri0_cg_regs =3D { .set_ofs =3D 0x0008, .clr_ofs =3D 0x0010, .sta_ofs =3D 0x0018, }; =20 -static const struct mtk_gate_regs peri1_cg_regs __initconst =3D { +static const struct mtk_gate_regs peri1_cg_regs =3D { .set_ofs =3D 0x000c, .clr_ofs =3D 0x0014, .sta_ofs =3D 0x001c, @@ -677,7 +682,7 @@ static const struct mtk_gate_regs peri1_cg_regs __initc= onst =3D { .ops =3D &mtk_clk_gate_ops_setclr, \ } =20 -static const struct mtk_gate peri_gates[] __initconst =3D { +static const struct mtk_gate peri_gates[] =3D { /* PERI0 */ GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0), GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1), @@ -717,19 +722,19 @@ static const struct mtk_gate peri_gates[] __initconst= =3D { GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2), }; =20 -static const char * const uart_ck_sel_parents[] __initconst =3D { +static const char * const uart_ck_sel_parents[] =3D { "clk26m", "uart_sel", }; =20 -static const struct mtk_composite peri_clks[] __initconst =3D { +static const struct mtk_composite peri_clks[] =3D { MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), }; =20 -static const struct mtk_gate_regs cg_regs_4_8_0 __initconst =3D { +static const struct mtk_gate_regs cg_regs_4_8_0 =3D { .set_ofs =3D 0x0004, .clr_ofs =3D 0x0008, .sta_ofs =3D 0x0000, @@ -744,7 +749,8 @@ static const struct mtk_gate_regs cg_regs_4_8_0 __initc= onst =3D { .ops =3D &mtk_clk_gate_ops_setclr, \ } =20 -static const struct mtk_gate img_clks[] __initconst =3D { +static const struct mtk_gate img_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "img_dummy"), GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0), GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5), GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6), @@ -754,13 +760,13 @@ static const struct mtk_gate img_clks[] __initconst = =3D { GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11), }; =20 -static const struct mtk_gate_regs vdec0_cg_regs __initconst =3D { +static const struct mtk_gate_regs vdec0_cg_regs =3D { .set_ofs =3D 0x0000, .clr_ofs =3D 0x0004, .sta_ofs =3D 0x0000, }; =20 -static const struct mtk_gate_regs vdec1_cg_regs __initconst =3D { +static const struct mtk_gate_regs vdec1_cg_regs =3D { .set_ofs =3D 0x0008, .clr_ofs =3D 0x000c, .sta_ofs =3D 0x0008, @@ -784,7 +790,8 @@ static const struct mtk_gate_regs vdec1_cg_regs __initc= onst =3D { .ops =3D &mtk_clk_gate_ops_setclr_inv, \ } =20 -static const struct mtk_gate vdec_clks[] __initconst =3D { +static const struct mtk_gate vdec_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "vdec_dummy"), GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0), GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0), }; @@ -798,7 +805,8 @@ static const struct mtk_gate vdec_clks[] __initconst = =3D { .ops =3D &mtk_clk_gate_ops_setclr_inv, \ } =20 -static const struct mtk_gate venc_clks[] __initconst =3D { +static const struct mtk_gate venc_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "venc_dummy"), GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0), GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4), GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8), @@ -814,7 +822,8 @@ static const struct mtk_gate venc_clks[] __initconst = =3D { .ops =3D &mtk_clk_gate_ops_setclr_inv, \ } =20 -static const struct mtk_gate venclt_clks[] __initconst =3D { +static const struct mtk_gate venclt_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "venclt_dummy"), GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0), GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), }; @@ -837,10 +846,11 @@ static const struct mtk_clk_rst_desc clk_rst_desc[] = =3D { } }; =20 -static struct clk_hw_onecell_data *mt8173_top_clk_data __initdata; -static struct clk_hw_onecell_data *mt8173_pll_clk_data __initdata; +static struct clk_hw_onecell_data *mt8173_top_clk_data; +static struct clk_hw_onecell_data *mt8173_pll_clk_data; +static struct clk_hw_onecell_data *infra_clk_data; =20 -static void __init mtk_clk_enable_critical(void) +static void mtk_clk_enable_critical(void) { if (!mt8173_top_clk_data || !mt8173_pll_clk_data) return; @@ -853,102 +863,149 @@ static void __init mtk_clk_enable_critical(void) clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_RTC_SEL]->clk); } =20 -static void __init mtk_topckgen_init(struct device_node *node) +static int clk_mt8173_topck_probe(struct platform_device *pdev) { + struct device_node *node =3D pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; void __iomem *base; int r; =20 - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); =20 mt8173_top_clk_data =3D clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); + if (IS_ERR_OR_NULL(clk_data)) + return -ENOMEM; =20 - mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8173_clk_lock, clk_data, NULL); + r =3D mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk= _data); + if (r) + goto free_clk_data; + + r =3D mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + if (r) + goto unregister_fixed_clks; + + r =3D mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, + &mt8173_clk_lock, clk_data, &pdev->dev); + if (r) + goto unregister_factors; =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + goto unregister_composites; =20 mtk_clk_enable_critical(); + return 0; + +unregister_composites: + mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data); +unregister_factors: + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); +unregister_fixed_clks: + mtk_clk_unregister_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_dat= a); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; } -CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init= ); =20 -static void __init mtk_infrasys_init(struct device_node *node) +static void clk_mt8173_infra_init_early(struct device_node *node) { - struct clk_hw_onecell_data *clk_data; + int i; + + infra_clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + if (!infra_clk_data) + return; + + for (i =3D 0; i < CLK_INFRA_NR_CLK; i++) + infra_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); + + mtk_clk_register_factors(infra_early_divs, ARRAY_SIZE(infra_early_divs), = infra_clk_data); + + of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); +} +CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg", + clk_mt8173_infra_init_early); + +static int clk_mt8173_infra_probe(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; int r; =20 - clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + r =3D mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), + infra_clk_data, &pdev->dev); + if (r) + return r; =20 - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, NULL); - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); + r =3D mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), + infra_clk_data, &pdev->dev); + if (r) + goto unregister_gates; =20 - mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), - clk_data, NULL); + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); + if (r) + goto unregister_cpumuxes; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r =3D mtk_register_reset_controller(node, &clk_rst_desc[0]); if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + goto unregister_clk_hw; + + return 0; =20 - mtk_register_reset_controller(node, &clk_rst_desc[0]); +unregister_clk_hw: + of_clk_del_provider(node); +unregister_cpumuxes: + mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_d= ata); +unregister_gates: + mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), infra_clk_da= ta); + return r; } -CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init= ); =20 -static void __init mtk_pericfg_init(struct device_node *node) +static int clk_mt8173_peri_probe(struct platform_device *pdev) { + struct device_node *node =3D pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; int r; void __iomem *base; =20 - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); =20 clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); + if (IS_ERR_OR_NULL(clk_data)) + return -ENOMEM; =20 - mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), - clk_data, NULL); - mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, - &mt8173_clk_lock, clk_data, NULL); + r =3D mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), + clk_data, &pdev->dev); + if (r) + goto free_clk_data; + + r =3D mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, + &mt8173_clk_lock, clk_data, &pdev->dev); + if (r) + goto unregister_gates; =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + goto unregister_composites; =20 - mtk_register_reset_controller(node, &clk_rst_desc[1]); + r =3D mtk_register_reset_controller(node, &clk_rst_desc[1]); + if (r) + goto unregister_clk_hw; + + return 0; + +unregister_clk_hw: + of_clk_del_provider(node); +unregister_composites: + mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data); +unregister_gates: + mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; } -CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); - -struct mtk_clk_usb { - int id; - const char *name; - const char *parent; - u32 reg_ofs; -}; - -#define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent =3D _parent, \ - .reg_ofs =3D _reg_ofs, \ - } - -static const struct mtk_clk_usb apmixed_usb[] __initconst =3D { - APMIXED_USB(CLK_APMIXED_REF2USB_TX, "ref2usb_tx", "clk26m", 0x8), -}; =20 #define MT8173_PLL_FMAX (3000UL * MHZ) =20 @@ -1007,119 +1064,130 @@ static const struct mtk_pll_data plls[] =3D { PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0= x0, 0x2f4, 0), }; =20 -static void __init mtk_apmixedsys_init(struct device_node *node) +static int clk_mt8173_apmixed_probe(struct platform_device *pdev) { + struct device_node *node =3D pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; void __iomem *base; struct clk_hw *hw; - int r, i; + int r; =20 base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } + if (!base) + return PTR_ERR(base); =20 mt8173_pll_clk_data =3D clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CL= K); - if (!clk_data) { - iounmap(base); - return; - } - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (IS_ERR_OR_NULL(clk_data)) + return -ENOMEM; =20 - for (i =3D 0; i < ARRAY_SIZE(apmixed_usb); i++) { - const struct mtk_clk_usb *cku =3D &apmixed_usb[i]; - - hw =3D mtk_clk_register_ref2usb_tx(cku->name, cku->parent, base + cku->r= eg_ofs); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", cku->name, PTR_ERR(hw)); - continue; - } + r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (r) + goto free_clk_data; =20 - clk_data->hws[cku->id] =3D hw; + hw =3D mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_= REF2USB); + if (IS_ERR(hw)) { + r =3D PTR_ERR(hw); + dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r); + goto unregister_plls; } + clk_data->hws[CLK_APMIXED_REF2USB_TX] =3D hw; =20 - hw =3D clk_hw_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0, - base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO, - NULL); + hw =3D devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m"= , 0, + base + REGOFF_HDMI_REF, 16, 3, + CLK_DIVIDER_POWER_OF_TWO, NULL); clk_data->hws[CLK_APMIXED_HDMI_REF] =3D hw; =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + goto unregister_ref2usb; =20 mtk_clk_enable_critical(); + return 0; + +unregister_ref2usb: + mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; } -CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys", - mtk_apmixedsys_init); - -static void __init mtk_imgsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_IMG_NR_CLK); =20 - mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), - clk_data, NULL); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static const struct mtk_clk_desc img_desc =3D { + .clks =3D img_clks, + .num_clks =3D ARRAY_SIZE(img_clks), +}; =20 - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init); +static const struct mtk_clk_desc vdec_desc =3D { + .clks =3D vdec_clks, + .num_clks =3D ARRAY_SIZE(vdec_clks), +}; =20 -static void __init mtk_vdecsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; +static const struct mtk_clk_desc venc_desc =3D { + .clks =3D venc_clks, + .num_clks =3D ARRAY_SIZE(venc_clks), +}; =20 - clk_data =3D mtk_alloc_clk_data(CLK_VDEC_NR_CLK); +static const struct mtk_clk_desc venc_lt_desc =3D { + .clks =3D venclt_clks, + .num_clks =3D ARRAY_SIZE(venclt_clks), +}; =20 - mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), - clk_data, NULL); +static const struct of_device_id of_match_clk_mt8173_simple[] =3D { + { .compatible =3D "mediatek,mt8173-imgsys", .data =3D &img_desc }, + { .compatible =3D "mediatek,mt8173-vdecsys", .data =3D &vdec_desc }, + { .compatible =3D "mediatek,mt8173-vencsys", .data =3D &venc_desc }, + { .compatible =3D "mediatek,mt8173-vencltsys", .data =3D &venc_lt_desc }, + { /* sentinel */ } +}; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init); +static struct platform_driver clk_mt8173_simple_drv =3D { + .driver =3D { + .name =3D "clk-mt8173-simple", + .of_match_table =3D of_match_clk_mt8173_simple, + }, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, +}; =20 -static void __init mtk_vencsys_init(struct device_node *node) +static int clk_mt8173_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; + int (*clk_probe)(struct platform_device *pdev); int r; =20 - clk_data =3D mtk_alloc_clk_data(CLK_VENC_NR_CLK); + clk_probe =3D of_device_get_match_data(&pdev->dev); + if (!clk_probe) + return -EINVAL; =20 - mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), - clk_data, NULL); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r =3D clk_probe(pdev); if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev-= >name, r); + + return r; } -CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init); =20 -static void __init mtk_vencltsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; +static const struct of_device_id of_match_clk_mt8173[] =3D { + { .compatible =3D "mediatek,mt8173-apmixedsys", .data =3D clk_mt8173_apmi= xed_probe }, + { .compatible =3D "mediatek,mt8173-infracfg", .data =3D clk_mt8173_infra_= probe }, + { .compatible =3D "mediatek,mt8173-topckgen", .data =3D clk_mt8173_topck_= probe }, + { .compatible =3D "mediatek,mt8173-pericfg", .data =3D clk_mt8173_peri_pr= obe }, + { /* sentinel */ } +}; =20 - clk_data =3D mtk_alloc_clk_data(CLK_VENCLT_NR_CLK); +static struct platform_driver clk_mt8173_drv =3D { + .probe =3D clk_mt8173_probe, + .driver =3D { + .name =3D "clk-mt8173", + .of_match_table =3D of_match_clk_mt8173, + }, +}; =20 - mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks), - clk_data, NULL); +static int __init clk_mt8173_init(void) +{ + int ret =3D platform_driver_register(&clk_mt8173_drv); =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + if (ret) + return ret; + return platform_driver_register(&clk_mt8173_simple_drv); } -CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_i= nit); +arch_initcall(clk_mt8173_init); --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D668C3DA6E for ; Fri, 23 Dec 2022 09:44:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229708AbiLWJoM (ORCPT ); Fri, 23 Dec 2022 04:44:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236192AbiLWJn2 (ORCPT ); Fri, 23 Dec 2022 04:43:28 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99A54379EC; Fri, 23 Dec 2022 01:43:21 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E73A96602CE3; Fri, 23 Dec 2022 09:43:18 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788600; bh=QXf/TTxdVVZOWmiCAJM2h74LJbKT6ebqnjt5TKAXqqU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UYmW3QEsXcDNHN4yvnBZr6fx714WT8fCxe55I1fx/Ob32373cZ0wA0BBkneYMquqC mBRhhKSfqzLCqeqh7YT+tt8RY5VVqstVTSNYvarkm+lgY2mH8l/aUVmGwskPElBkMB 0rKHvRJ3tjGGvJqaQzl633pQz5ULnH8FTB1RZrUrYDzceKsLbuRgs+wZeMIfp7PvJV JtoEp1jBvbbTWbt4GvPifL0PCMqmhPv/ovHX+YkORW5zivEQVmgEbBphkAhLZ0hdZZ KqAkYEFzBnXPXU8ZnahC4dXOFNDAGiM56D0O+wy5caEz61u1jjE7D/2OX0eHoZlTRF WTpQthvjTk48w== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 09/23] clk: mediatek: mt8173: Remove mtk_clk_enable_critical() Date: Fri, 23 Dec 2022 10:42:45 +0100 Message-Id: <20221223094259.87373-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The entire point of mtk_clk_enable_critical() is to raise the refcount of some clocks so that they won't be turned off during runtime, but this is the same as what the CLK_IS_CRITICAL flag does. Set CLK_IS_CRITICAL on all of the critical clocks and remove the aforementioned function as a cleanup. No functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8173.c | 41 ++++++++++++------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-m= t8173.c index 70cdc0719658..02231f8ba6d9 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -546,8 +546,11 @@ static const struct mtk_composite cpu_muxes[] =3D { static const struct mtk_composite top_muxes[] =3D { /* CLK_CFG_0 */ MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), - MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1), - MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x004= 0, 16, 1, 23), + MUX_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", + ddrphycfg_parents, 0x0040, 16, 1, 23, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31), /* CLK_CFG_1 */ MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7), @@ -581,7 +584,9 @@ static const struct mtk_composite top_muxes[] =3D { */ MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, = 7, 0), MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15), - MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3,= 23), + MUX_GATE_FLAGS(CLK_TOP_CCI400_SEL, "cci400_sel", + cci400_parents, 0x00a0, 16, 3, 23, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31= ), /* CLK_CFG_7 */ MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7), @@ -596,7 +601,8 @@ static const struct mtk_composite top_muxes[] =3D { MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x= 00d0, 0, 3, 7), MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15), MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, = 16, 2, 23), - MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2), + MUX_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), =20 DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, = 4, 24), DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, = 8, 0), @@ -846,23 +852,8 @@ static const struct mtk_clk_rst_desc clk_rst_desc[] = =3D { } }; =20 -static struct clk_hw_onecell_data *mt8173_top_clk_data; -static struct clk_hw_onecell_data *mt8173_pll_clk_data; static struct clk_hw_onecell_data *infra_clk_data; =20 -static void mtk_clk_enable_critical(void) -{ - if (!mt8173_top_clk_data || !mt8173_pll_clk_data) - return; - - clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA15PLL]->clk); - clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA7PLL]->clk); - clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_MEM_SEL]->clk); - clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk); - clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_CCI400_SEL]->clk); - clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_RTC_SEL]->clk); -} - static int clk_mt8173_topck_probe(struct platform_device *pdev) { struct device_node *node =3D pdev->dev.of_node; @@ -874,7 +865,7 @@ static int clk_mt8173_topck_probe(struct platform_devic= e *pdev) if (IS_ERR(base)) return PTR_ERR(base); =20 - mt8173_top_clk_data =3D clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); + clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); if (IS_ERR_OR_NULL(clk_data)) return -ENOMEM; =20 @@ -895,7 +886,6 @@ static int clk_mt8173_topck_probe(struct platform_devic= e *pdev) if (r) goto unregister_composites; =20 - mtk_clk_enable_critical(); return 0; =20 unregister_composites: @@ -1048,8 +1038,10 @@ static const struct mtk_pll_div_table mmpll_div_tabl= e[] =3D { }; =20 static const struct mtk_pll_data plls[] =3D { - PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, 0, 21, 0x204, = 24, 0x0, 0x204, 0), - PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, 0, 21, 0x214, 24= , 0x0, 0x214, 0), + PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO, + 21, 0x204, 24, 0x0, 0x204, 0), + PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO, + 21, 0x214, 24, 0x0, 0x214, 0), PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BA= R, 21, 0x220, 4, 0x0, 0x224, 0), PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BA= R, 7, 0x230, 4, 0x0, 0x234, 14), PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0,= 0x244, 0, mmpll_div_table), @@ -1076,7 +1068,7 @@ static int clk_mt8173_apmixed_probe(struct platform_d= evice *pdev) if (!base) return PTR_ERR(base); =20 - mt8173_pll_clk_data =3D clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CL= K); + clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (IS_ERR_OR_NULL(clk_data)) return -ENOMEM; =20 @@ -1101,7 +1093,6 @@ static int clk_mt8173_apmixed_probe(struct platform_d= evice *pdev) if (r) goto unregister_ref2usb; =20 - mtk_clk_enable_critical(); return 0; =20 unregister_ref2usb: --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79A58C3DA7D for ; Fri, 23 Dec 2022 09:44:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236005AbiLWJo0 (ORCPT ); Fri, 23 Dec 2022 04:44:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236218AbiLWJn5 (ORCPT ); Fri, 23 Dec 2022 04:43:57 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CED4B379E6; Fri, 23 Dec 2022 01:43:22 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 630246602CFC; Fri, 23 Dec 2022 09:43:20 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788601; bh=2Ogxv7N0nGYgBJ2r5OXZoOfXwi2BBC7K3iyBitduybY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WXnql/2jwJzCWdBCVEcSwexUuZtkr7/EK6+MQbRFs0ALMFe1P0jweT4cf7luIjZK2 l2HRPvpyxM7z1Ei0XY4qQcDqBbu7+QEi1u1q+XbBARqTWP1sjinjsqIU08NXlWgIaW Yf4zJBPku815VRA+BdQLmX7uW0hkCIPeMR5+qEUdnldbCN+mKDJZSpPv19zEzRzyXQ qMQdLta63AXQyns3cSovWSdjSKILgYnvHDScyNo27m/87OYcmmCtyFt4KjP+Vi7m+9 NoKiB260Z6bAO3gcA4mDRpBRRD52h4fzn3qWUpf49RJ01fICLQcbx9yCm3VSx9BB+Z OwSnh1v/ISU9w== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 10/23] clk: mediatek: mt8173: Break down clock drivers and allow module build Date: Fri, 23 Dec 2022 10:42:46 +0100 Message-Id: <20221223094259.87373-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Split the giant clock driver for MT8173 into smaller drivers and make it possible to build the non boot critical clock controller drivers as modules by adding remove functions. Some spare code style cleanups were also performed. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/Kconfig | 30 +- drivers/clk/mediatek/Makefile | 6 +- drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 157 ++++ drivers/clk/mediatek/clk-mt8173-img.c | 55 ++ drivers/clk/mediatek/clk-mt8173-infracfg.c | 154 ++++ drivers/clk/mediatek/clk-mt8173-pericfg.c | 171 ++++ .../{clk-mt8173.c =3D> clk-mt8173-topckgen.c} | 811 ++++-------------- drivers/clk/mediatek/clk-mt8173-vdecsys.c | 57 ++ drivers/clk/mediatek/clk-mt8173-vencsys.c | 64 ++ 9 files changed, 853 insertions(+), 652 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt8173-apmixedsys.c create mode 100644 drivers/clk/mediatek/clk-mt8173-img.c create mode 100644 drivers/clk/mediatek/clk-mt8173-infracfg.c create mode 100644 drivers/clk/mediatek/clk-mt8173-pericfg.c rename drivers/clk/mediatek/{clk-mt8173.c =3D> clk-mt8173-topckgen.c} (50%) create mode 100644 drivers/clk/mediatek/clk-mt8173-vdecsys.c create mode 100644 drivers/clk/mediatek/clk-mt8173-vencsys.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index c504ebca21ee..b11646a9bf6e 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -457,19 +457,41 @@ config COMMON_CLK_MT8167_VDECSYS This driver supports MediaTek MT8167 vdecsys clocks. =20 config COMMON_CLK_MT8173 - bool "Clock driver for MediaTek MT8173" + tristate "Clock driver for MediaTek MT8173" depends on ARCH_MEDIATEK || COMPILE_TEST select COMMON_CLK_MEDIATEK default ARCH_MEDIATEK help - This driver supports MediaTek MT8173 clocks. + This driver supports MediaTek MT8173 basic clocks and clocks + required for various peripherals found on MediaTek. + +config COMMON_CLK_MT8173_IMGSYS + tristate "Clock driver for MediaTek MT8173 imgsys" + depends on COMMON_CLK_MT8173 + default COMMON_CLK_MT8173 + help + This driver supports MediaTek MT8173 imgsys clocks. =20 config COMMON_CLK_MT8173_MMSYS - bool "Clock driver for MediaTek MT8173 mmsys" + tristate "Clock driver for MediaTek MT8173 mmsys" + depends on COMMON_CLK_MT8173 + default COMMON_CLK_MT8173 + help + This driver supports MediaTek MT8173 mmsys clocks. + +config COMMON_CLK_MT8173_VDECSYS + tristate "Clock driver for MediaTek MT8173 VDECSYS" + depends on COMMON_CLK_MT8173 + default COMMON_CLK_MT8173 + help + This driver supports MediaTek MT8173 vdecsys clocks. + +config COMMON_CLK_MT8173_VENCSYS + tristate "Clock driver for MediaTek MT8173 VENCSYS" depends on COMMON_CLK_MT8173 default COMMON_CLK_MT8173 help - This driver supports MediaTek MT8173 mmsys clocks. + This driver supports MediaTek MT8173 vencsys clocks. =20 config COMMON_CLK_MT8183 bool "Clock driver for MediaTek MT8183" diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e24080fd6e7f..a5c216c94831 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -64,8 +64,12 @@ obj-$(CONFIG_COMMON_CLK_MT8167_IMGSYS) +=3D clk-mt8167-i= mg.o obj-$(CONFIG_COMMON_CLK_MT8167_MFGCFG) +=3D clk-mt8167-mfgcfg.o obj-$(CONFIG_COMMON_CLK_MT8167_MMSYS) +=3D clk-mt8167-mm.o obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) +=3D clk-mt8167-vdec.o -obj-$(CONFIG_COMMON_CLK_MT8173) +=3D clk-mt8173.o +obj-$(CONFIG_COMMON_CLK_MT8173) +=3D clk-mt8173-apmixedsys.o clk-mt8173-in= fracfg.o \ + clk-mt8173-pericfg.o clk-mt8173-topckgen.o +obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) +=3D clk-mt8173-img.o obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) +=3D clk-mt8173-mm.o +obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) +=3D clk-mt8173-vdecsys.o +obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) +=3D clk-mt8173-vencsys.o obj-$(CONFIG_COMMON_CLK_MT8183) +=3D clk-mt8183.o obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) +=3D clk-mt8183-audio.o obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) +=3D clk-mt8183-cam.o diff --git a/drivers/clk/mediatek/clk-mt8173-apmixedsys.c b/drivers/clk/med= iatek/clk-mt8173-apmixedsys.c new file mode 100644 index 000000000000..a56c5845d07a --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8173-apmixedsys.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-pll.h" + +#define REGOFF_REF2USB 0x8 +#define REGOFF_HDMI_REF 0x40 + +#define MT8173_PLL_FMAX (3000UL * MHZ) + +#define CON0_MT8173_RST_BAR BIT(24) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift, _div_table) { \ + .id =3D _id, \ + .name =3D _name, \ + .reg =3D _reg, \ + .pwr_reg =3D _pwr_reg, \ + .en_mask =3D _en_mask, \ + .flags =3D _flags, \ + .rst_bar_mask =3D CON0_MT8173_RST_BAR, \ + .fmax =3D MT8173_PLL_FMAX, \ + .pcwbits =3D _pcwbits, \ + .pd_reg =3D _pd_reg, \ + .pd_shift =3D _pd_shift, \ + .tuner_reg =3D _tuner_reg, \ + .pcw_reg =3D _pcw_reg, \ + .pcw_shift =3D _pcw_shift, \ + .div_table =3D _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ + _pcw_shift) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ + NULL) + +static const struct mtk_pll_div_table mmpll_div_table[] =3D { + { .div =3D 0, .freq =3D MT8173_PLL_FMAX }, + { .div =3D 1, .freq =3D 1000000000 }, + { .div =3D 2, .freq =3D 702000000 }, + { .div =3D 3, .freq =3D 253500000 }, + { .div =3D 4, .freq =3D 126750000 }, + { } /* sentinel */ +}; + +static const struct mtk_pll_data plls[] =3D { + PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO, + 21, 0x204, 24, 0x0, 0x204, 0), + PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO, + 21, 0x214, 24, 0x0, 0x214, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BA= R, 21, + 0x220, 4, 0x0, 0x224, 0), + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BA= R, 7, + 0x230, 4, 0x0, 0x234, 14), + PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, + 0x244, 0, mmpll_div_table), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0= , 0x254, 0), + PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0= , 0x264, 0), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, = 0x274, 0), + PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x28= 4, 0), + PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4,= 0x0, 0x294, 0), + PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, = 0x2a4, 0), + PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2b8, = 0x2b8, 0), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0, 0, 21, 0x2d0, 4, 0x0= , 0x2d4, 0), + PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0= x0, 0x2f4, 0), +}; + +static const struct of_device_id of_match_clk_mt8173_apmixed[] =3D { + { .compatible =3D "mediatek,mt8173-apmixedsys" }, + { /* sentinel */ } +}; + +static int clk_mt8173_apmixed_probe(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data; + void __iomem *base; + struct clk_hw *hw; + int r; + + base =3D of_iomap(node, 0); + if (!base) + return PTR_ERR(base); + + clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (IS_ERR_OR_NULL(clk_data)) + return -ENOMEM; + + r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (r) + goto free_clk_data; + + hw =3D mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_= REF2USB); + if (IS_ERR(hw)) { + r =3D PTR_ERR(hw); + dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r); + goto unregister_plls; + } + clk_data->hws[CLK_APMIXED_REF2USB_TX] =3D hw; + + hw =3D devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m"= , 0, + base + REGOFF_HDMI_REF, 16, 3, + CLK_DIVIDER_POWER_OF_TWO, NULL); + clk_data->hws[CLK_APMIXED_HDMI_REF] =3D hw; + + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + goto unregister_ref2usb; + + return 0; + +unregister_ref2usb: + mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; +} + +static int clk_mt8173_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static struct platform_driver clk_mt8173_apmixed_drv =3D { + .probe =3D clk_mt8173_apmixed_probe, + .remove =3D clk_mt8173_apmixed_remove, + .driver =3D { + .name =3D "clk-mt8173-apmixed", + .of_match_table =3D of_match_clk_mt8173_apmixed, + }, +}; +module_platform_driver(clk_mt8173_apmixed_drv); + +MODULE_DESCRIPTION("MediaTek MT8173 apmixed clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8173-img.c b/drivers/clk/mediatek/c= lk-mt8173-img.c new file mode 100644 index 000000000000..7b50ffb7a8a5 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8173-img.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs img_cg_regs =3D { + .set_ofs =3D 0x0004, + .clr_ofs =3D 0x0008, + .sta_ofs =3D 0x0000, +}; + +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_set= clr) + +static const struct mtk_gate img_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "img_dummy"), + GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0), + GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5), + GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6), + GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7), + GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8), + GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9), + GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11), +}; + +static const struct mtk_clk_desc img_desc =3D { + .clks =3D img_clks, + .num_clks =3D ARRAY_SIZE(img_clks), +}; + +static const struct of_device_id of_match_clk_mt8173_imgsys[] =3D { + { .compatible =3D "mediatek,mt8173-imgsys", .data =3D &img_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8173_vdecsys_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8173-imgsys", + .of_match_table =3D of_match_clk_mt8173_imgsys, + }, +}; +module_platform_driver(clk_mt8173_vdecsys_drv); + +MODULE_DESCRIPTION("MediaTek MT8173 vdecsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/media= tek/clk-mt8173-infracfg.c new file mode 100644 index 000000000000..ee4b992c89c6 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include "clk-cpumux.h" +#include "clk-gate.h" +#include "clk-mtk.h" +#include "reset.h" + +#define GATE_ICG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, \ + _shift, &mtk_clk_gate_ops_setclr) + +static struct clk_hw_onecell_data *infra_clk_data; + +static const struct mtk_gate_regs infra_cg_regs =3D { + .set_ofs =3D 0x0040, + .clr_ofs =3D 0x0044, + .sta_ofs =3D 0x0048, +}; + +static const char * const ca53_parents[] __initconst =3D { + "clk26m", + "armca7pll", + "mainpll", + "univpll" +}; + +static const char * const ca72_parents[] __initconst =3D { + "clk26m", + "armca15pll", + "mainpll", + "univpll" +}; + +static const struct mtk_composite cpu_muxes[] =3D { + MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), + MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), +}; + +static const struct mtk_fixed_factor infra_early_divs[] =3D { + FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), +}; + +static const struct mtk_gate infra_gates[] =3D { + GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), + GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1), + GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5), + GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), + GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7), + GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), + GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15), + GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), + GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18), + GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22), + GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), +}; + +static u16 infrasys_rst_ofs[] =3D { 0x30, 0x34 }; + +static const struct mtk_clk_rst_desc clk_rst_desc =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D infrasys_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), +}; + +static const struct of_device_id of_match_clk_mt8173_infracfg[] =3D { + { .compatible =3D "mediatek,mt8173-infracfg" }, + { /* sentinel */ } +}; + +static void clk_mt8173_infra_init_early(struct device_node *node) +{ + int i; + + infra_clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + if (!infra_clk_data) + return; + + for (i =3D 0; i < CLK_INFRA_NR_CLK; i++) + infra_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); + + mtk_clk_register_factors(infra_early_divs, ARRAY_SIZE(infra_early_divs), = infra_clk_data); + + of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); +} +CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg", + clk_mt8173_infra_init_early); + +static int clk_mt8173_infracfg_probe(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + int r; + + r =3D mtk_clk_register_gates(node, infra_gates, ARRAY_SIZE(infra_gates), + infra_clk_data, &pdev->dev); + if (r) + return r; + + r =3D mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), + infra_clk_data, &pdev->dev); + if (r) + goto unregister_gates; + + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); + if (r) + goto unregister_cpumuxes; + + r =3D mtk_register_reset_controller(node, &clk_rst_desc); + if (r) + goto unregister_clk_hw; + + return 0; + +unregister_clk_hw: + of_clk_del_provider(node); +unregister_cpumuxes: + mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_d= ata); +unregister_gates: + mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), infra_clk_= data); + return r; +} + +static int clk_mt8173_infracfg_remove(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); + mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static struct platform_driver clk_mt8173_infracfg_drv =3D { + .driver =3D { + .name =3D "clk-mt8173-infracfg", + .of_match_table =3D of_match_clk_mt8173_infracfg, + }, + .probe =3D clk_mt8173_infracfg_probe, + .remove =3D clk_mt8173_infracfg_remove, +}; +module_platform_driver(clk_mt8173_infracfg_drv); + +MODULE_DESCRIPTION("MediaTek MT8173 infracfg clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8173-pericfg.c b/drivers/clk/mediat= ek/clk-mt8173-pericfg.c new file mode 100644 index 000000000000..30c0fa263cc0 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8173-pericfg.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include "clk-gate.h" +#include "clk-mtk.h" +#include "reset.h" + +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, \ + _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, \ + _shift, &mtk_clk_gate_ops_setclr) + +static DEFINE_SPINLOCK(mt8173_clk_lock); + +static const struct mtk_gate_regs peri0_cg_regs =3D { + .set_ofs =3D 0x0008, + .clr_ofs =3D 0x0010, + .sta_ofs =3D 0x0018, +}; + +static const struct mtk_gate_regs peri1_cg_regs =3D { + .set_ofs =3D 0x000c, + .clr_ofs =3D 0x0014, + .sta_ofs =3D 0x001c, +}; + +static const char * const uart_ck_sel_parents[] =3D { + "clk26m", + "uart_sel", +}; + +static const struct mtk_composite peri_clks[] =3D { + MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), + MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), + MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), + MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), +}; + +static const struct mtk_gate peri_gates[] =3D { + /* PERI0 */ + GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0), + GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1), + GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2), + GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3), + GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4), + GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5), + GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6), + GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7), + GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8), + GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9), + GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10), + GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11), + GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12), + GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13), + GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14), + GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15), + GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16), + GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17), + GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18), + GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19), + GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20), + GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21), + GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22), + GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23), + GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24), + GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25), + GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26), + GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27), + GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28), + GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29), + GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30), + GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31), + /* PERI1 */ + GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0), + GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1), + GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2), +}; + +static u16 pericfg_rst_ofs[] =3D { 0x0, 0x4 }; + +static const struct mtk_clk_rst_desc clk_rst_desc =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D pericfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), +}; + +static const struct of_device_id of_match_clk_mt8173_pericfg[] =3D { + { .compatible =3D "mediatek,mt8173-pericfg" }, + { /* sentinel */ } +}; + +static int clk_mt8173_pericfg_probe(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data; + int r; + void __iomem *base; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); + if (IS_ERR_OR_NULL(clk_data)) + return -ENOMEM; + + r =3D mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), + clk_data, &pdev->dev); + if (r) + goto free_clk_data; + + r =3D mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, + &mt8173_clk_lock, clk_data, &pdev->dev); + if (r) + goto unregister_gates; + + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) + goto unregister_composites; + + r =3D mtk_register_reset_controller(node, &clk_rst_desc); + if (r) + goto unregister_clk_hw; + + return 0; + +unregister_clk_hw: + of_clk_del_provider(node); +unregister_composites: + mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data); +unregister_gates: + mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; +} + +static int clk_mt8173_pericfg_remove(struct platform_device *pdev) +{ + struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data); + mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static struct platform_driver clk_mt8173_pericfg_drv =3D { + .driver =3D { + .name =3D "clk-mt8173-pericfg", + .of_match_table =3D of_match_clk_mt8173_pericfg, + }, + .probe =3D clk_mt8173_pericfg_probe, + .remove =3D clk_mt8173_pericfg_remove, +}; +module_platform_driver(clk_mt8173_pericfg_drv); + +MODULE_DESCRIPTION("MediaTek MT8173 pericfg clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-m= t8173-topckgen.c similarity index 50% rename from drivers/clk/mediatek/clk-mt8173.c rename to drivers/clk/mediatek/clk-mt8173-topckgen.c index 02231f8ba6d9..c7323639c502 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173-topckgen.c @@ -1,138 +1,34 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 MediaTek Inc. - * Author: James Liao + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno */ =20 -#include -#include -#include -#include +#include +#include #include - -#include "clk-cpumux.h" #include "clk-gate.h" #include "clk-mtk.h" -#include "clk-pll.h" - -#include - -#define REGOFF_REF2USB 0x8 -#define REGOFF_HDMI_REF 0x40 +#include "clk-mux.h" =20 /* * For some clocks, we don't care what their actual rates are. And these * clocks may change their rate on different products or different scenari= os. * So we model these clocks' rate as 0, to denote it's not an actual rate. */ -#define DUMMY_RATE 0 - -static DEFINE_SPINLOCK(mt8173_clk_lock); - -static const struct mtk_fixed_clk fixed_clks[] =3D { - FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE), - FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ= ), - FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE), - FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE), - FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE), - FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE), -}; - -static const struct mtk_fixed_factor top_divs[] =3D { - FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2), - FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3), - - FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0), - FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0), - FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0), - FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0), - - FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4), - FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3), - - FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0), - FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0), - FACTOR_FLAGS(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5, 0), - FACTOR_FLAGS(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7, 0), - FACTOR_FLAGS(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26, 0), - - FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1), - FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793), - FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1), - - FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2), - FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3), - - FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1), - FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1), - - FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), - FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), +#define DUMMY_RATE 0 =20 - FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1), - FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2), - FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4), - FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8), - FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16), +#define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gat= e, _flags) \ + MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \ + (_reg + 0x4), (_reg + 0x8), _shift, _width, \ + _gate, 0, -1, _flags) =20 - FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), - FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), - FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), +#define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _f= lags) \ + TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \ + _gate, CLK_SET_RATE_PARENT | _flags) =20 - FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), - FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), - - FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), - FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), - FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), - FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1), - FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2), - FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4), - - FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0), - FACTOR_FLAGS(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4, 0), - - FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1), - FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2), - FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4), - FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8), - FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16), - - FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1, 0), - FACTOR_FLAGS(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2, 0), - - FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3), - FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4), - - FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1), - FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2), - FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4), -}; +static DEFINE_SPINLOCK(mt8173_top_clk_lock); =20 static const char * const axi_parents[] =3D { "clk26m", @@ -524,23 +420,109 @@ static const char * const i2s3_b_ck_parents[] =3D { "apll2_div5" }; =20 -static const char * const ca53_parents[] =3D { - "clk26m", - "armca7pll", - "mainpll", - "univpll" +static const struct mtk_fixed_clk fixed_clks[] =3D { + FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE), + FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ= ), + FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE), + FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE), + FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE), + FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE), }; =20 -static const char * const ca72_parents[] =3D { - "clk26m", - "armca15pll", - "mainpll", - "univpll" -}; +static const struct mtk_fixed_factor top_divs[] =3D { + FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2), + FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3), + + FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0), + FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0), + FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0), + FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0), + + FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4), + FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3), + + FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0), + FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0), + FACTOR_FLAGS(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5, 0), + FACTOR_FLAGS(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7, 0), + FACTOR_FLAGS(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26, 0), + + FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1), + FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793), + FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1), + + FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2), + FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3), + + FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1), + FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1), + + FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), + FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), + + FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1), + FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2), + FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4), + FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8), + FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16), + + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), + + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), + + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), + FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1), + FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2), + FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4), + + FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0), + FACTOR_FLAGS(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4, 0), + + FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1), + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2), + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4), + FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8), + FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16), =20 -static const struct mtk_composite cpu_muxes[] =3D { - MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), - MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), + FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1, 0), + FACTOR_FLAGS(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2, 0), + + FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3), + FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4), + + FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1), + FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2), + FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4), }; =20 static const struct mtk_composite top_muxes[] =3D { @@ -564,25 +546,35 @@ static const struct mtk_composite top_muxes[] =3D { MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31= ), /* CLK_CFG_3 */ MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7), - MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x= 0070, 8, 3, 15), - MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, = 16, 4, 23), - MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, = 24, 3, 31), + MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, + 0x0070, 8, 3, 15), + MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, + 0x0070, 16, 4, 23), + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, + 0x0070, 24, 3, 31), /* CLK_CFG_4 */ - MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, = 0, 3, 7), - MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, = 8, 4, 15), - MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23= ), - MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x= 0080, 24, 3, 31), + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, + 0x0080, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, + 0x0080, 8, 4, 15), + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, + 0x0080, 16, 2, 23), + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, + 0x0080, 24, 3, 31), /* CLK_CFG_5 */ - MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, = 3, 7 /* 7:5 */), + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, + 0x0090, 0, 3, 7 /* 7:5 */), MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15), MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23), - MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, = 4, 31), + MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, + 0x0090, 24, 4, 31), /* CLK_CFG_6 */ /* * The dpi0_sel clock should not propagate rate changes to its parent * clock so the dpi driver can have full control over PLL and divider. */ - MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, = 7, 0), + MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, + 0x00a0, 0, 3, 7, 0), MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15), MUX_GATE_FLAGS(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23, @@ -590,17 +582,23 @@ static const struct mtk_composite top_muxes[] =3D { MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31= ), /* CLK_CFG_7 */ MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7), - MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x= 00b0, 8, 2, 15), - MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x= 00b0, 16, 2, 23), + MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, + 0x00b0, 8, 2, 15), + MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, + 0x00b0, 16, 2, 23), MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31), /* CLK_CFG_12 */ - MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x= 00c0, 0, 3, 7), + MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, + 0x00c0, 0, 3, 7), MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15), - MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24,= 3, 31), + MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, + 0x00c0, 24, 3, 31), /* CLK_CFG_13 */ - MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x= 00d0, 0, 3, 7), + MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, + 0x00d0, 0, 3, 7), MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15), - MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, = 16, 2, 23), + MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, + 0x00d0, 16, 2, 23), MUX_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), =20 @@ -625,236 +623,12 @@ static const struct mtk_composite top_muxes[] =3D { MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1), }; =20 -static const struct mtk_gate_regs infra_cg_regs =3D { - .set_ofs =3D 0x0040, - .clr_ofs =3D 0x0044, - .sta_ofs =3D 0x0048, -}; - -#define GATE_ICG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &infra_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate infra_clks[] =3D { - GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), - GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1), - GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5), - GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), - GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7), - GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), - GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15), - GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), - GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18), - GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22), - GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), -}; - -static const struct mtk_fixed_factor infra_early_divs[] =3D { - FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), -}; - -static const struct mtk_gate_regs peri0_cg_regs =3D { - .set_ofs =3D 0x0008, - .clr_ofs =3D 0x0010, - .sta_ofs =3D 0x0018, -}; - -static const struct mtk_gate_regs peri1_cg_regs =3D { - .set_ofs =3D 0x000c, - .clr_ofs =3D 0x0014, - .sta_ofs =3D 0x001c, -}; - -#define GATE_PERI0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } - -#define GATE_PERI1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &peri1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate peri_gates[] =3D { - /* PERI0 */ - GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0), - GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1), - GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2), - GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3), - GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4), - GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5), - GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6), - GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7), - GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8), - GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9), - GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10), - GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11), - GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12), - GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13), - GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14), - GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15), - GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16), - GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17), - GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18), - GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19), - GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20), - GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21), - GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22), - GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23), - GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24), - GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25), - GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26), - GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27), - GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28), - GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29), - GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30), - GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31), - /* PERI1 */ - GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0), - GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1), - GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2), -}; - -static const char * const uart_ck_sel_parents[] =3D { - "clk26m", - "uart_sel", -}; - -static const struct mtk_composite peri_clks[] =3D { - MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), - MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), - MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), - MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), -}; - -static const struct mtk_gate_regs cg_regs_4_8_0 =3D { - .set_ofs =3D 0x0004, - .clr_ofs =3D 0x0008, - .sta_ofs =3D 0x0000, -}; - -#define GATE_IMG(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &cg_regs_4_8_0, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr, \ - } - -static const struct mtk_gate img_clks[] =3D { - GATE_DUMMY(CLK_DUMMY, "img_dummy"), - GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0), - GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5), - GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6), - GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7), - GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8), - GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9), - GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11), -}; - -static const struct mtk_gate_regs vdec0_cg_regs =3D { - .set_ofs =3D 0x0000, - .clr_ofs =3D 0x0004, - .sta_ofs =3D 0x0000, -}; - -static const struct mtk_gate_regs vdec1_cg_regs =3D { - .set_ofs =3D 0x0008, - .clr_ofs =3D 0x000c, - .sta_ofs =3D 0x0008, -}; - -#define GATE_VDEC0(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec0_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } - -#define GATE_VDEC1(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &vdec1_cg_regs, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } - -static const struct mtk_gate vdec_clks[] =3D { - GATE_DUMMY(CLK_DUMMY, "vdec_dummy"), - GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0), - GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0), -}; - -#define GATE_VENC(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &cg_regs_4_8_0, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } - -static const struct mtk_gate venc_clks[] =3D { - GATE_DUMMY(CLK_DUMMY, "venc_dummy"), - GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0), - GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4), - GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8), - GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12), -}; - -#define GATE_VENCLT(_id, _name, _parent, _shift) { \ - .id =3D _id, \ - .name =3D _name, \ - .parent_name =3D _parent, \ - .regs =3D &cg_regs_4_8_0, \ - .shift =3D _shift, \ - .ops =3D &mtk_clk_gate_ops_setclr_inv, \ - } - -static const struct mtk_gate venclt_clks[] =3D { - GATE_DUMMY(CLK_DUMMY, "venclt_dummy"), - GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0), - GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), -}; - -static u16 infrasys_rst_ofs[] =3D { 0x30, 0x34, }; -static u16 pericfg_rst_ofs[] =3D { 0x0, 0x4, }; - -static const struct mtk_clk_rst_desc clk_rst_desc[] =3D { - /* infrasys */ - { - .version =3D MTK_RST_SIMPLE, - .rst_bank_ofs =3D infrasys_rst_ofs, - .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), - }, - /* pericfg */ - { - .version =3D MTK_RST_SIMPLE, - .rst_bank_ofs =3D pericfg_rst_ofs, - .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), - } +static const struct of_device_id of_match_clk_mt8173_topckgen[] =3D { + { .compatible =3D "mediatek,mt8173-topckgen" }, + { /* sentinel */ } }; =20 -static struct clk_hw_onecell_data *infra_clk_data; - -static int clk_mt8173_topck_probe(struct platform_device *pdev) +static int clk_mt8173_topckgen_probe(struct platform_device *pdev) { struct device_node *node =3D pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; @@ -878,7 +652,7 @@ static int clk_mt8173_topck_probe(struct platform_devic= e *pdev) goto unregister_fixed_clks; =20 r =3D mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8173_clk_lock, clk_data, &pdev->dev); + &mt8173_top_clk_lock, clk_data, &pdev->dev); if (r) goto unregister_factors; =20 @@ -899,286 +673,29 @@ static int clk_mt8173_topck_probe(struct platform_de= vice *pdev) return r; } =20 -static void clk_mt8173_infra_init_early(struct device_node *node) -{ - int i; - - infra_clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - if (!infra_clk_data) - return; - - for (i =3D 0; i < CLK_INFRA_NR_CLK; i++) - infra_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); - - mtk_clk_register_factors(infra_early_divs, ARRAY_SIZE(infra_early_divs), = infra_clk_data); - - of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); -} -CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg", - clk_mt8173_infra_init_early); - -static int clk_mt8173_infra_probe(struct platform_device *pdev) +static int clk_mt8173_topckgen_remove(struct platform_device *pdev) { + struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); struct device_node *node =3D pdev->dev.of_node; - int r; - - r =3D mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - infra_clk_data, &pdev->dev); - if (r) - return r; - - r =3D mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), - infra_clk_data, &pdev->dev); - if (r) - goto unregister_gates; =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); - if (r) - goto unregister_cpumuxes; - - r =3D mtk_register_reset_controller(node, &clk_rst_desc[0]); - if (r) - goto unregister_clk_hw; - - return 0; - -unregister_clk_hw: of_clk_del_provider(node); -unregister_cpumuxes: - mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_d= ata); -unregister_gates: - mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), infra_clk_da= ta); - return r; -} - -static int clk_mt8173_peri_probe(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); - if (IS_ERR_OR_NULL(clk_data)) - return -ENOMEM; - - r =3D mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), - clk_data, &pdev->dev); - if (r) - goto free_clk_data; - - r =3D mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, - &mt8173_clk_lock, clk_data, &pdev->dev); - if (r) - goto unregister_gates; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_composites; - - r =3D mtk_register_reset_controller(node, &clk_rst_desc[1]); - if (r) - goto unregister_clk_hw; - - return 0; - -unregister_clk_hw: - of_clk_del_provider(node); -unregister_composites: - mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data); -unregister_gates: - mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data); -free_clk_data: + mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data); + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + mtk_clk_unregister_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_dat= a); mtk_free_clk_data(clk_data); - return r; -} - -#define MT8173_PLL_FMAX (3000UL * MHZ) - -#define CON0_MT8173_RST_BAR BIT(24) - -#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift, _div_table) { \ - .id =3D _id, \ - .name =3D _name, \ - .reg =3D _reg, \ - .pwr_reg =3D _pwr_reg, \ - .en_mask =3D _en_mask, \ - .flags =3D _flags, \ - .rst_bar_mask =3D CON0_MT8173_RST_BAR, \ - .fmax =3D MT8173_PLL_FMAX, \ - .pcwbits =3D _pcwbits, \ - .pd_reg =3D _pd_reg, \ - .pd_shift =3D _pd_shift, \ - .tuner_reg =3D _tuner_reg, \ - .pcw_reg =3D _pcw_reg, \ - .pcw_shift =3D _pcw_shift, \ - .div_table =3D _div_table, \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \ - _pcw_shift) \ - PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ - _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ - NULL) - -static const struct mtk_pll_div_table mmpll_div_table[] =3D { - { .div =3D 0, .freq =3D MT8173_PLL_FMAX }, - { .div =3D 1, .freq =3D 1000000000 }, - { .div =3D 2, .freq =3D 702000000 }, - { .div =3D 3, .freq =3D 253500000 }, - { .div =3D 4, .freq =3D 126750000 }, - { } /* sentinel */ -}; - -static const struct mtk_pll_data plls[] =3D { - PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO, - 21, 0x204, 24, 0x0, 0x204, 0), - PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO, - 21, 0x214, 24, 0x0, 0x214, 0), - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BA= R, 21, 0x220, 4, 0x0, 0x224, 0), - PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BA= R, 7, 0x230, 4, 0x0, 0x234, 14), - PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0,= 0x244, 0, mmpll_div_table), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0= , 0x254, 0), - PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0= , 0x264, 0), - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, = 0x274, 0), - PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x28= 4, 0), - PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4,= 0x0, 0x294, 0), - PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, = 0x2a4, 0), - PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2b8, = 0x2b8, 0), - PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0, 0, 21, 0x2d0, 4, 0x0= , 0x2d4, 0), - PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0= x0, 0x2f4, 0), -}; - -static int clk_mt8173_apmixed_probe(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - struct clk_hw *hw; - int r; - - base =3D of_iomap(node, 0); - if (!base) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (IS_ERR_OR_NULL(clk_data)) - return -ENOMEM; - - r =3D mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - if (r) - goto free_clk_data; - - hw =3D mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_= REF2USB); - if (IS_ERR(hw)) { - r =3D PTR_ERR(hw); - dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r); - goto unregister_plls; - } - clk_data->hws[CLK_APMIXED_REF2USB_TX] =3D hw; - - hw =3D devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m"= , 0, - base + REGOFF_HDMI_REF, 16, 3, - CLK_DIVIDER_POWER_OF_TWO, NULL); - clk_data->hws[CLK_APMIXED_HDMI_REF] =3D hw; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_ref2usb; =20 return 0; - -unregister_ref2usb: - mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); -unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static const struct mtk_clk_desc img_desc =3D { - .clks =3D img_clks, - .num_clks =3D ARRAY_SIZE(img_clks), -}; - -static const struct mtk_clk_desc vdec_desc =3D { - .clks =3D vdec_clks, - .num_clks =3D ARRAY_SIZE(vdec_clks), -}; - -static const struct mtk_clk_desc venc_desc =3D { - .clks =3D venc_clks, - .num_clks =3D ARRAY_SIZE(venc_clks), -}; - -static const struct mtk_clk_desc venc_lt_desc =3D { - .clks =3D venclt_clks, - .num_clks =3D ARRAY_SIZE(venclt_clks), -}; - -static const struct of_device_id of_match_clk_mt8173_simple[] =3D { - { .compatible =3D "mediatek,mt8173-imgsys", .data =3D &img_desc }, - { .compatible =3D "mediatek,mt8173-vdecsys", .data =3D &vdec_desc }, - { .compatible =3D "mediatek,mt8173-vencsys", .data =3D &venc_desc }, - { .compatible =3D "mediatek,mt8173-vencltsys", .data =3D &venc_lt_desc }, - { /* sentinel */ } -}; - -static struct platform_driver clk_mt8173_simple_drv =3D { - .driver =3D { - .name =3D "clk-mt8173-simple", - .of_match_table =3D of_match_clk_mt8173_simple, - }, - .probe =3D mtk_clk_simple_probe, - .remove =3D mtk_clk_simple_remove, -}; - -static int clk_mt8173_probe(struct platform_device *pdev) -{ - int (*clk_probe)(struct platform_device *pdev); - int r; - - clk_probe =3D of_device_get_match_data(&pdev->dev); - if (!clk_probe) - return -EINVAL; - - r =3D clk_probe(pdev); - if (r) - dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev-= >name, r); - - return r; } =20 -static const struct of_device_id of_match_clk_mt8173[] =3D { - { .compatible =3D "mediatek,mt8173-apmixedsys", .data =3D clk_mt8173_apmi= xed_probe }, - { .compatible =3D "mediatek,mt8173-infracfg", .data =3D clk_mt8173_infra_= probe }, - { .compatible =3D "mediatek,mt8173-topckgen", .data =3D clk_mt8173_topck_= probe }, - { .compatible =3D "mediatek,mt8173-pericfg", .data =3D clk_mt8173_peri_pr= obe }, - { /* sentinel */ } -}; - -static struct platform_driver clk_mt8173_drv =3D { - .probe =3D clk_mt8173_probe, +static struct platform_driver clk_mt8173_topckgen_drv =3D { .driver =3D { - .name =3D "clk-mt8173", - .of_match_table =3D of_match_clk_mt8173, + .name =3D "clk-mt8173-topckgen", + .of_match_table =3D of_match_clk_mt8173_topckgen, }, + .probe =3D clk_mt8173_topckgen_probe, + .remove =3D clk_mt8173_topckgen_remove, }; +module_platform_driver(clk_mt8173_topckgen_drv); =20 -static int __init clk_mt8173_init(void) -{ - int ret =3D platform_driver_register(&clk_mt8173_drv); - - if (ret) - return ret; - return platform_driver_register(&clk_mt8173_simple_drv); -} -arch_initcall(clk_mt8173_init); +MODULE_DESCRIPTION("MediaTek MT8173 topckgen clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8173-vdecsys.c b/drivers/clk/mediat= ek/clk-mt8173-vdecsys.c new file mode 100644 index 000000000000..5105b8e0969d --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8173-vdecsys.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include "clk-gate.h" +#include "clk-mtk.h" + +#define GATE_VDEC(_id, _name, _parent, _regs) \ + GATE_MTK(_id, _name, _parent, _regs, 0, \ + &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate_regs vdec0_cg_regs =3D { + .set_ofs =3D 0x0000, + .clr_ofs =3D 0x0004, + .sta_ofs =3D 0x0000, +}; + +static const struct mtk_gate_regs vdec1_cg_regs =3D { + .set_ofs =3D 0x0008, + .clr_ofs =3D 0x000c, + .sta_ofs =3D 0x0008, +}; + +static const struct mtk_gate vdec_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "vdec_dummy"), + GATE_VDEC(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", &vdec0_cg_regs), + GATE_VDEC(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", &vdec1_cg_regs), +}; + +static const struct mtk_clk_desc vdec_desc =3D { + .clks =3D vdec_clks, + .num_clks =3D ARRAY_SIZE(vdec_clks), +}; + +static const struct of_device_id of_match_clk_mt8173_vdecsys[] =3D { + { .compatible =3D "mediatek,mt8173-vdecsys", .data =3D &vdec_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8173_vdecsys_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8173-vdecsys", + .of_match_table =3D of_match_clk_mt8173_vdecsys, + }, +}; +module_platform_driver(clk_mt8173_vdecsys_drv); + +MODULE_DESCRIPTION("MediaTek MT8173 vdecsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt8173-vencsys.c b/drivers/clk/mediat= ek/clk-mt8173-vencsys.c new file mode 100644 index 000000000000..ff4f1cb735de --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8173-vencsys.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs venc_cg_regs =3D { + .set_ofs =3D 0x4, + .clr_ofs =3D 0x8, + .sta_ofs =3D 0x0, +}; + +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_se= tclr_inv) + +static const struct mtk_gate venc_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "venc_dummy"), + GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0), + GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4), + GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8), + GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12), +}; + +static const struct mtk_gate venclt_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "venclt_dummy"), + GATE_VENC(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0), + GATE_VENC(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), +}; + +static const struct mtk_clk_desc venc_desc =3D { + .clks =3D venc_clks, + .num_clks =3D ARRAY_SIZE(venc_clks), +}; + +static const struct mtk_clk_desc venc_lt_desc =3D { + .clks =3D venclt_clks, + .num_clks =3D ARRAY_SIZE(venclt_clks), +}; + +static const struct of_device_id of_match_clk_mt8173_vencsys[] =3D { + { .compatible =3D "mediatek,mt8173-vencsys", .data =3D &venc_desc }, + { .compatible =3D "mediatek,mt8173-vencltsys", .data =3D &venc_lt_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8173_vencsys_drv =3D { + .driver =3D { + .name =3D "clk-mt8173-vencsys", + .of_match_table =3D of_match_clk_mt8173_vencsys, + }, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, +}; +module_platform_driver(clk_mt8173_vencsys_drv); + +MODULE_DESCRIPTION("MediaTek MT8173 vencsys clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7094EC4708D for ; Fri, 23 Dec 2022 09:44:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236258AbiLWJo3 (ORCPT ); Fri, 23 Dec 2022 04:44:29 -0500 Received: from lindbergh.monkeyblade.net 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b=VLb9AsLZR4A/2kD0aYno8zsn3ULXeoNpXUi2EX1392VhyguaIHFn4vYvkE8bgFfvx 2Lf05ky1mIFG7VUkYKi3l0SgE4stQluMp0QEFKQMMNtkKcWrz9AgUzzYDb4jMEElr5 +W8mLg5ToES6LAM4PZMbBrmnYwf886+OG7Fu5lkvj6nRfJkritL98haTTovBehUauu LQgouWv1dOG5rQBaix/UVFcNd5pot4f2YUuLlGsHO3qHiGWiMpirhhtyBOKOnGrSOg NHq1ZLZ/CWhVV1IM5zfxnuX5t59vYfFNTBxgSIwq4aht73Jb+g/HJS9yAoH3MEOMFP LE0fJgwliDmKQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 11/23] clk: mediatek: Switch to mtk_clk_simple_probe() where possible Date: Fri, 23 Dec 2022 10:42:47 +0100 Message-Id: <20221223094259.87373-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" mtk_clk_simple_probe() is a function that registers mtk gate clocks and, if reset data is present, a reset controller and across all of the MTK clock drivers, such a function is duplicated many times: switch to the common mtk_clk_simple_probe() function for all of the clock drivers that are registering as platform drivers. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt2701-aud.c | 26 +++---- drivers/clk/mediatek/clk-mt2701-eth.c | 34 +++------ drivers/clk/mediatek/clk-mt2701-g3d.c | 56 +++----------- drivers/clk/mediatek/clk-mt2701-hif.c | 36 +++------ drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++------------- drivers/clk/mediatek/clk-mt6779.c | 42 ++++++----- drivers/clk/mediatek/clk-mt7622-aud.c | 49 +++---------- drivers/clk/mediatek/clk-mt7622-eth.c | 82 ++++----------------- drivers/clk/mediatek/clk-mt7622-hif.c | 85 ++++----------------- drivers/clk/mediatek/clk-mt7629-hif.c | 85 ++++----------------- drivers/clk/mediatek/clk-mt8183-audio.c | 19 +++-- drivers/clk/mediatek/clk-mt8183.c | 75 ++++++++----------- drivers/clk/mediatek/clk-mt8192-aud.c | 25 +++---- drivers/clk/mediatek/clk-mt8192.c | 98 ++++++++----------------- 14 files changed, 236 insertions(+), 559 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/c= lk-mt2701-aud.c index ab13ab618fb5..1fd6d96b34dc 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -76,6 +76,7 @@ static const struct mtk_gate_regs audio3_cg_regs =3D { }; =20 static const struct mtk_gate audio_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "aud_dummy"), /* AUDIO0 */ GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2), GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20), @@ -138,29 +139,26 @@ static const struct mtk_gate audio_clks[] =3D { GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), }; =20 +static const struct mtk_clk_desc audio_desc =3D { + .clks =3D audio_clks, + .num_clks =3D ARRAY_SIZE(audio_clks), +}; + static const struct of_device_id of_match_clk_mt2701_aud[] =3D { - { .compatible =3D "mediatek,mt2701-audsys", }, - {} + { .compatible =3D "mediatek,mt2701-audsys", .data =3D &audio_desc }, + { /* sentinel */ } }; =20 static int clk_mt2701_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; int r; =20 - clk_data =3D mtk_alloc_clk_data(CLK_AUD_NR); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r =3D mtk_clk_simple_probe(pdev); if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); - - goto err_clk_provider; + return r; } =20 r =3D devm_of_platform_populate(&pdev->dev); @@ -170,13 +168,13 @@ static int clk_mt2701_aud_probe(struct platform_devic= e *pdev) return 0; =20 err_plat_populate: - of_clk_del_provider(node); -err_clk_provider: + mtk_clk_simple_remove(pdev); return r; } =20 static struct platform_driver clk_mt2701_aud_drv =3D { .probe =3D clk_mt2701_aud_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt2701-aud", .of_match_table =3D of_match_clk_mt2701_aud, diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index 9670e1e170f2..bd3fddf53ce1 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -26,6 +26,7 @@ static const struct mtk_gate_regs eth_cg_regs =3D { } =20 static const struct mtk_gate eth_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "eth_dummy"), GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), @@ -44,35 +45,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 +static const struct mtk_clk_desc eth_desc =3D { + .clks =3D eth_clks, + .num_clks =3D ARRAY_SIZE(eth_clks), + .rst_desc =3D &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt2701_eth[] =3D { - { .compatible =3D "mediatek,mt2701-ethsys", }, + { .compatible =3D "mediatek,mt2701-ethsys", .data =3D ð_desc }, {} }; =20 -static int clk_mt2701_eth_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_ETHSYS_NR); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - static struct platform_driver clk_mt2701_eth_drv =3D { - .probe =3D clk_mt2701_eth_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt2701-eth", .of_match_table =3D of_match_clk_mt2701_eth, diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index 11391b144267..499a170ba5f9 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -32,6 +32,7 @@ static const struct mtk_gate_regs g3d_cg_regs =3D { }; =20 static const struct mtk_gate g3d_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "g3d_dummy"), GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), }; =20 @@ -43,57 +44,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 -static int clk_mt2701_g3dsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_G3DSYS_NR); - - mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} +static const struct mtk_clk_desc g3d_desc =3D { + .clks =3D g3d_clks, + .num_clks =3D ARRAY_SIZE(g3d_clks), + .rst_desc =3D &clk_rst_desc, +}; =20 static const struct of_device_id of_match_clk_mt2701_g3d[] =3D { - { - .compatible =3D "mediatek,mt2701-g3dsys", - .data =3D clk_mt2701_g3dsys_init, - }, { - /* sentinel */ - } + { .compatible =3D "mediatek,mt2701-g3dsys", .data =3D &g3d_desc }, + { /* sentinel */ } }; =20 -static int clk_mt2701_g3d_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init =3D of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r =3D clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt2701_g3d_drv =3D { - .probe =3D clk_mt2701_g3d_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt2701-g3d", .of_match_table =3D of_match_clk_mt2701_g3d, diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index c14c0bb10f88..5d113838b3e4 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -26,6 +26,7 @@ static const struct mtk_gate_regs hif_cg_regs =3D { } =20 static const struct mtk_gate hif_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "hif_dummy"), GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21), GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22), GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24), @@ -41,37 +42,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 +static const struct mtk_clk_desc hif_desc =3D { + .clks =3D hif_clks, + .num_clks =3D ARRAY_SIZE(hif_clks), + .rst_desc =3D &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt2701_hif[] =3D { - { .compatible =3D "mediatek,mt2701-hifsys", }, + { .compatible =3D "mediatek,mt2701-hifsys", .data =3D &hif_desc }, {} }; =20 -static int clk_mt2701_hif_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_HIFSYS_NR); - - mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - return r; - } - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return 0; -} - static struct platform_driver clk_mt2701_hif_drv =3D { - .probe =3D clk_mt2701_hif_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt2701-hif", .of_match_table =3D of_match_clk_mt2701_hif, diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index 5cadcf6ca9b7..c4bee791f570 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1362,50 +1362,6 @@ static int clk_mt2712_top_probe(struct platform_devi= ce *pdev) return r; } =20 -static int clk_mt2712_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r !=3D 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); - - return r; -} - -static int clk_mt2712_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r !=3D 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); - - return r; -} - static int clk_mt2712_mcu_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1440,12 +1396,6 @@ static const struct of_device_id of_match_clk_mt2712= [] =3D { }, { .compatible =3D "mediatek,mt2712-topckgen", .data =3D clk_mt2712_top_probe, - }, { - .compatible =3D "mediatek,mt2712-infracfg", - .data =3D clk_mt2712_infra_probe, - }, { - .compatible =3D "mediatek,mt2712-pericfg", - .data =3D clk_mt2712_peri_probe, }, { .compatible =3D "mediatek,mt2712-mcucfg", .data =3D clk_mt2712_mcu_probe, @@ -1472,6 +1422,33 @@ static int clk_mt2712_probe(struct platform_device *= pdev) return r; } =20 +static const struct mtk_clk_desc infra_desc =3D { + .clks =3D infra_clks, + .num_clks =3D ARRAY_SIZE(infra_clks), + .rst_desc =3D &clk_rst_desc[0], +}; + +static const struct mtk_clk_desc peri_desc =3D { + .clks =3D peri_clks, + .num_clks =3D ARRAY_SIZE(peri_clks), + .rst_desc =3D &clk_rst_desc[1], +}; + +static const struct of_device_id of_match_clk_mt2712_simple[] =3D { + { .compatible =3D "mediatek,mt2712-infracfg", .data =3D &infra_desc }, + { .compatible =3D "mediatek,mt2712-pericfg", .data =3D &peri_desc, }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt2712_simple_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt2712-simple", + .of_match_table =3D of_match_clk_mt2712_simple, + }, +}; + static struct platform_driver clk_mt2712_drv =3D { .probe =3D clk_mt2712_probe, .driver =3D { @@ -1482,7 +1459,11 @@ static struct platform_driver clk_mt2712_drv =3D { =20 static int __init clk_mt2712_init(void) { - return platform_driver_register(&clk_mt2712_drv); + int ret =3D platform_driver_register(&clk_mt2712_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt2712_simple_drv); } =20 arch_initcall(clk_mt2712_init); diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-m= t6779.c index 6d1fb19be77b..479fb38766ea 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -880,6 +880,7 @@ static const struct mtk_gate_regs infra3_cg_regs =3D { &mtk_clk_gate_ops_setclr) =20 static const struct mtk_gate infra_clks[] =3D { + GATE_DUMMY(CLK_DUMMY, "ifa_dummy"), /* INFRA0 */ GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0), @@ -1256,19 +1257,6 @@ static int clk_mt6779_top_probe(struct platform_devi= ce *pdev) return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } =20 -static int clk_mt6779_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - static const struct of_device_id of_match_clk_mt6779[] =3D { { .compatible =3D "mediatek,mt6779-apmixed", @@ -1276,9 +1264,6 @@ static const struct of_device_id of_match_clk_mt6779[= ] =3D { }, { .compatible =3D "mediatek,mt6779-topckgen", .data =3D clk_mt6779_top_probe, - }, { - .compatible =3D "mediatek,mt6779-infracfg_ao", - .data =3D clk_mt6779_infra_probe, }, { /* sentinel */ } @@ -1302,6 +1287,25 @@ static int clk_mt6779_probe(struct platform_device *= pdev) return r; } =20 +static const struct mtk_clk_desc infra_desc =3D { + .clks =3D infra_clks, + .num_clks =3D ARRAY_SIZE(infra_clks), +}; + +static const struct of_device_id of_match_clk_mt6779_infra[] =3D { + { .compatible =3D "mediatek,mt6779-infracfg_ao", .data =3D &infra_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6779_infra_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6779-infra", + .of_match_table =3D of_match_clk_mt6779_infra, + }, +}; + static struct platform_driver clk_mt6779_drv =3D { .probe =3D clk_mt6779_probe, .driver =3D { @@ -1312,7 +1316,11 @@ static struct platform_driver clk_mt6779_drv =3D { =20 static int __init clk_mt6779_init(void) { - return platform_driver_register(&clk_mt6779_drv); + int ret =3D platform_driver_register(&clk_mt6779_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt6779_infra_drv); } =20 arch_initcall(clk_mt6779_init); diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/c= lk-mt7622-aud.c index d0379d8704af..86464cc750e2 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -130,24 +130,21 @@ static const struct mtk_gate audio_clks[] =3D { GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), }; =20 -static int clk_mt7622_audiosys_init(struct platform_device *pdev) +static const struct mtk_clk_desc audio_desc =3D { + .clks =3D audio_clks, + .num_clks =3D ARRAY_SIZE(audio_clks), +}; + +static int clk_mt7622_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; int r; =20 - clk_data =3D mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r =3D mtk_clk_simple_probe(pdev); if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); - - goto err_clk_provider; + return r; } =20 r =3D devm_of_platform_populate(&pdev->dev); @@ -157,40 +154,18 @@ static int clk_mt7622_audiosys_init(struct platform_d= evice *pdev) return 0; =20 err_plat_populate: - of_clk_del_provider(node); -err_clk_provider: + mtk_clk_simple_remove(pdev); return r; } =20 static const struct of_device_id of_match_clk_mt7622_aud[] =3D { - { - .compatible =3D "mediatek,mt7622-audsys", - .data =3D clk_mt7622_audiosys_init, - }, { - /* sentinel */ - } + { .compatible =3D "mediatek,mt7622-audsys", .data =3D &audio_desc }, + { /* sentinel */ } }; =20 -static int clk_mt7622_aud_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init =3D of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r =3D clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_aud_drv =3D { .probe =3D clk_mt7622_aud_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt7622-aud", .of_match_table =3D of_match_clk_mt7622_aud, diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index 9b4a26ca0f44..7dd0cec802f7 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -73,80 +73,26 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 -static int clk_mt7622_ethsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_ETH_NR_CLK); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_SGMII_NR_CLK); - - mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); +static const struct mtk_clk_desc eth_desc =3D { + .clks =3D eth_clks, + .num_clks =3D ARRAY_SIZE(eth_clks), + .rst_desc =3D &clk_rst_desc, +}; =20 - return r; -} +static const struct mtk_clk_desc sgmii_desc =3D { + .clks =3D eth_clks, + .num_clks =3D ARRAY_SIZE(sgmii_clks), +}; =20 static const struct of_device_id of_match_clk_mt7622_eth[] =3D { - { - .compatible =3D "mediatek,mt7622-ethsys", - .data =3D clk_mt7622_ethsys_init, - }, { - .compatible =3D "mediatek,mt7622-sgmiisys", - .data =3D clk_mt7622_sgmiisys_init, - }, { - /* sentinel */ - } + { .compatible =3D "mediatek,mt7622-ethsys", .data =3D ð_desc }, + { .compatible =3D "mediatek,mt7622-sgmiisys", .data =3D &sgmii_desc }, + { /* sentinel */ } }; =20 -static int clk_mt7622_eth_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init =3D of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r =3D clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_eth_drv =3D { - .probe =3D clk_mt7622_eth_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt7622-eth", .of_match_table =3D of_match_clk_mt7622_eth, diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index 8cf37f75ca77..ab5cad0c2b1c 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -84,82 +84,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 -static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - - mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7622_pciesys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - - mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +static const struct mtk_clk_desc ssusb_desc =3D { + .clks =3D ssusb_clks, + .num_clks =3D ARRAY_SIZE(ssusb_clks), + .rst_desc =3D &clk_rst_desc, +}; =20 - return r; -} +static const struct mtk_clk_desc pcie_desc =3D { + .clks =3D pcie_clks, + .num_clks =3D ARRAY_SIZE(pcie_clks), + .rst_desc =3D &clk_rst_desc, +}; =20 static const struct of_device_id of_match_clk_mt7622_hif[] =3D { - { - .compatible =3D "mediatek,mt7622-pciesys", - .data =3D clk_mt7622_pciesys_init, - }, { - .compatible =3D "mediatek,mt7622-ssusbsys", - .data =3D clk_mt7622_ssusbsys_init, - }, { - /* sentinel */ - } + { .compatible =3D "mediatek,mt7622-pciesys", .data =3D &pcie_desc }, + { .compatible =3D "mediatek,mt7622-ssusbsys", .data =3D &ssusb_desc }, + { /* sentinel */ } }; =20 -static int clk_mt7622_hif_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init =3D of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r =3D clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_hif_drv =3D { - .probe =3D clk_mt7622_hif_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt7622-hif", .of_match_table =3D of_match_clk_mt7622_hif, diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index 44fbd88b4647..c3eb09ea6036 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -79,82 +79,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 -static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - - mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7629_pciesys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - - mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +static const struct mtk_clk_desc ssusb_desc =3D { + .clks =3D ssusb_clks, + .num_clks =3D ARRAY_SIZE(ssusb_clks), + .rst_desc =3D &clk_rst_desc, +}; =20 - return r; -} +static const struct mtk_clk_desc pcie_desc =3D { + .clks =3D pcie_clks, + .num_clks =3D ARRAY_SIZE(pcie_clks), + .rst_desc =3D &clk_rst_desc, +}; =20 static const struct of_device_id of_match_clk_mt7629_hif[] =3D { - { - .compatible =3D "mediatek,mt7629-pciesys", - .data =3D clk_mt7629_pciesys_init, - }, { - .compatible =3D "mediatek,mt7629-ssusbsys", - .data =3D clk_mt7629_ssusbsys_init, - }, { - /* sentinel */ - } + { .compatible =3D "mediatek,mt7629-pciesys", .data =3D &pcie_desc }, + { .compatible =3D "mediatek,mt7629-ssusbsys", .data =3D &ssusb_desc }, + { /* sentinel */ } }; =20 -static int clk_mt7629_hif_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init =3D of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r =3D clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7629_hif_drv =3D { - .probe =3D clk_mt7629_hif_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt7629-hif", .of_match_table =3D of_match_clk_mt7629_hif, diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek= /clk-mt8183-audio.c index f4c6448b6f74..f5600450b4d1 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -67,35 +67,34 @@ static const struct mtk_gate audio_clks[] =3D { 20), }; =20 +static const struct mtk_clk_desc audio_desc =3D { + .clks =3D audio_clks, + .num_clks =3D ARRAY_SIZE(audio_clks), +}; + static int clk_mt8183_audio_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; int r; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); =20 - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r =3D mtk_clk_simple_probe(pdev); if (r) return r; =20 r =3D devm_of_platform_populate(&pdev->dev); if (r) - of_clk_del_provider(node); + mtk_clk_simple_remove(pdev); =20 return r; } =20 static const struct of_device_id of_match_clk_mt8183_audio[] =3D { - { .compatible =3D "mediatek,mt8183-audiosys", }, + { .compatible =3D "mediatek,mt8183-audiosys", .data =3D &audio_desc }, {} }; =20 static struct platform_driver clk_mt8183_audio_drv =3D { .probe =3D clk_mt8183_audio_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt8183-audio", .of_match_table =3D of_match_clk_mt8183_audio, diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 10a82b542376..f1d84c0730d5 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1187,43 +1187,6 @@ static int clk_mt8183_top_probe(struct platform_devi= ce *pdev) top_clk_data); } =20 -static int clk_mt8183_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - dev_err(&pdev->dev, - "%s(): could not register clock provider: %d\n", - __func__, r); - return r; - } - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt8183_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - - clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - static int clk_mt8183_mcu_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1249,12 +1212,6 @@ static const struct of_device_id of_match_clk_mt8183= [] =3D { }, { .compatible =3D "mediatek,mt8183-topckgen", .data =3D clk_mt8183_top_probe, - }, { - .compatible =3D "mediatek,mt8183-infracfg", - .data =3D clk_mt8183_infra_probe, - }, { - .compatible =3D "mediatek,mt8183-pericfg", - .data =3D clk_mt8183_peri_probe, }, { .compatible =3D "mediatek,mt8183-mcucfg", .data =3D clk_mt8183_mcu_probe, @@ -1281,6 +1238,32 @@ static int clk_mt8183_probe(struct platform_device *= pdev) return r; } =20 +static const struct mtk_clk_desc infra_desc =3D { + .clks =3D infra_clks, + .num_clks =3D ARRAY_SIZE(infra_clks), + .rst_desc =3D &clk_rst_desc, +}; + +static const struct mtk_clk_desc peri_desc =3D { + .clks =3D peri_clks, + .num_clks =3D ARRAY_SIZE(peri_clks), +}; + +static const struct of_device_id of_match_clk_mt8183_simple[] =3D { + { .compatible =3D "mediatek,mt8183-infracfg", .data =3D &infra_desc }, + { .compatible =3D "mediatek,mt8183-pericfg", .data =3D &peri_desc, }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8183_simple_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8183-simple", + .of_match_table =3D of_match_clk_mt8183_simple, + }, +}; + static struct platform_driver clk_mt8183_drv =3D { .probe =3D clk_mt8183_probe, .driver =3D { @@ -1291,7 +1274,11 @@ static struct platform_driver clk_mt8183_drv =3D { =20 static int __init clk_mt8183_init(void) { - return platform_driver_register(&clk_mt8183_drv); + int ret =3D platform_driver_register(&clk_mt8183_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt8183_simple_drv); } =20 arch_initcall(clk_mt8183_init); diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/c= lk-mt8192-aud.c index 3acadca2452a..d52f671e20ce 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -77,39 +77,34 @@ static const struct mtk_gate aud_clks[] =3D { GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4), }; =20 +static const struct mtk_clk_desc aud_desc =3D { + .clks =3D aud_clks, + .num_clks =3D ARRAY_SIZE(aud_clks), +}; + static int clk_mt8192_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; int r; =20 - clk_data =3D mtk_alloc_clk_data(CLK_AUD_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), - clk_data, &pdev->dev); - if (r) - return r; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r =3D mtk_clk_simple_probe(pdev); if (r) return r; =20 r =3D devm_of_platform_populate(&pdev->dev); if (r) - of_clk_del_provider(node); + mtk_clk_simple_remove(pdev); =20 return r; } =20 static const struct of_device_id of_match_clk_mt8192_aud[] =3D { - { .compatible =3D "mediatek,mt8192-audsys", }, - {} + { .compatible =3D "mediatek,mt8192-audsys", .data =3D &aud_desc }, + { /* sentinel */ } }; =20 static struct platform_driver clk_mt8192_aud_drv =3D { .probe =3D clk_mt8192_aud_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt8192-aud", .of_match_table =3D of_match_clk_mt8192_aud, diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 3ca068a4c552..9a9d51bfb84d 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1158,66 +1158,6 @@ static int clk_mt8192_top_probe(struct platform_devi= ce *pdev) return r; } =20 -static int clk_mt8192_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - if (r) - goto free_clk_data; - - r =3D mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - if (r) - goto unregister_gates; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - return r; - -unregister_gates: - mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8192_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - - clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r =3D mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - if (r) - goto free_clk_data; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - return r; - -unregister_gates: - mtk_clk_unregister_gates(peri_clks, ARRAY_SIZE(peri_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - static int clk_mt8192_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1255,12 +1195,6 @@ static const struct of_device_id of_match_clk_mt8192= [] =3D { }, { .compatible =3D "mediatek,mt8192-topckgen", .data =3D clk_mt8192_top_probe, - }, { - .compatible =3D "mediatek,mt8192-infracfg", - .data =3D clk_mt8192_infra_probe, - }, { - .compatible =3D "mediatek,mt8192-pericfg", - .data =3D clk_mt8192_peri_probe, }, { /* sentinel */ } @@ -1282,6 +1216,32 @@ static int clk_mt8192_probe(struct platform_device *= pdev) return r; } =20 +static const struct mtk_clk_desc infra_desc =3D { + .clks =3D infra_clks, + .num_clks =3D ARRAY_SIZE(infra_clks), + .rst_desc =3D &clk_rst_desc, +}; + +static const struct mtk_clk_desc peri_desc =3D { + .clks =3D peri_clks, + .num_clks =3D ARRAY_SIZE(peri_clks), +}; + +static const struct of_device_id of_match_clk_mt8192_simple[] =3D { + { .compatible =3D "mediatek,mt8192-infracfg", .data =3D &infra_desc }, + { .compatible =3D "mediatek,mt8192-pericfg", .data =3D &peri_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8192_simple_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8192-simple", + .of_match_table =3D of_match_clk_mt8192_simple, + }, +}; + static struct platform_driver clk_mt8192_drv =3D { .probe =3D clk_mt8192_probe, .driver =3D { @@ -1292,7 +1252,11 @@ static struct platform_driver clk_mt8192_drv =3D { =20 static int __init clk_mt8192_init(void) { - return platform_driver_register(&clk_mt8192_drv); + int ret =3D platform_driver_register(&clk_mt8192_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt8192_simple_drv); } =20 arch_initcall(clk_mt8192_init); --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB60DC4332F for ; Fri, 23 Dec 2022 09:44:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236259AbiLWJod (ORCPT ); Fri, 23 Dec 2022 04:44:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236228AbiLWJoI (ORCPT ); Fri, 23 Dec 2022 04:44:08 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACA1B37F8A; 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charset="utf-8" As a preparation to increase probe functions commonization across various MediaTek SoC clock controller drivers, extend function mtk_clk_simple_probe() to be able to register not only gates, but also fixed clocks, factors, muxes and composites. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Miles Chen Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++--- drivers/clk/mediatek/clk-mtk.h | 10 ++++ 2 files changed, 103 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d05364e17e95..b0a6225cd7b2 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -11,12 +11,14 @@ #include #include #include +#include #include #include #include =20 #include "clk-mtk.h" #include "clk-gate.h" +#include "clk-mux.h" =20 const struct mtk_gate_regs cg_regs_dummy =3D { 0, 0, 0 }; =20 @@ -465,20 +467,71 @@ int mtk_clk_simple_probe(struct platform_device *pdev) const struct mtk_clk_desc *mcd; struct clk_hw_onecell_data *clk_data; struct device_node *node =3D pdev->dev.of_node; - int r; + void __iomem *base; + int num_clks, r; =20 mcd =3D of_device_get_match_data(&pdev->dev); if (!mcd) return -EINVAL; =20 - clk_data =3D mtk_alloc_clk_data(mcd->num_clks); + /* Composite clocks needs us to pass iomem pointer */ + if (mcd->composite_clks) { + if (!mcd->shared_io) + base =3D devm_platform_ioremap_resource(pdev, 0); + else + base =3D of_iomap(node, 0); + + if (IS_ERR_OR_NULL(base)) + return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM; + } + + /* Calculate how many clk_hw_onecell_data entries to allocate */ + num_clks =3D mcd->num_clks + mcd->num_composite_clks; + num_clks +=3D mcd->num_fixed_clks + mcd->num_factor_clks; + num_clks +=3D mcd->num_mux_clks; + + clk_data =3D mtk_alloc_clk_data(num_clks); if (!clk_data) return -ENOMEM; =20 - r =3D mtk_clk_register_gates(node, mcd->clks, mcd->num_clks, - clk_data, &pdev->dev); - if (r) - goto free_data; + if (mcd->fixed_clks) { + r =3D mtk_clk_register_fixed_clks(mcd->fixed_clks, + mcd->num_fixed_clks, clk_data); + if (r) + goto free_data; + } + + if (mcd->factor_clks) { + r =3D mtk_clk_register_factors(mcd->factor_clks, + mcd->num_factor_clks, clk_data); + if (r) + goto unregister_fixed_clks; + } + + if (mcd->mux_clks) { + r =3D mtk_clk_register_muxes(mcd->mux_clks, mcd->num_mux_clks, + node, mcd->clk_lock, clk_data, + &pdev->dev); + if (r) + goto unregister_factors; + }; + + if (mcd->composite_clks) { + /* We don't check composite_lock because it's optional */ + r =3D mtk_clk_register_composites(mcd->composite_clks, + mcd->num_composite_clks, + base, mcd->clk_lock, + clk_data, &pdev->dev); + if (r) + goto unregister_muxes; + } + + if (mcd->clks) { + r =3D mtk_clk_register_gates(node, mcd->clks, mcd->num_clks, + clk_data, &pdev->dev); + if (r) + goto unregister_composites; + } =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -496,9 +549,28 @@ int mtk_clk_simple_probe(struct platform_device *pdev) return r; =20 unregister_clks: - mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); + if (mcd->clks) + mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); +unregister_composites: + if (mcd->composite_clks) + mtk_clk_unregister_composites(mcd->composite_clks, + mcd->num_composite_clks, clk_data); +unregister_muxes: + if (mcd->mux_clks) + mtk_clk_unregister_muxes(mcd->mux_clks, + mcd->num_mux_clks, clk_data); +unregister_factors: + if (mcd->factor_clks) + mtk_clk_unregister_factors(mcd->factor_clks, + mcd->num_factor_clks, clk_data); +unregister_fixed_clks: + if (mcd->fixed_clks) + mtk_clk_unregister_fixed_clks(mcd->fixed_clks, + mcd->num_fixed_clks, clk_data); free_data: mtk_free_clk_data(clk_data); + if (mcd->shared_io && base) + iounmap(base); return r; } EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); @@ -510,7 +582,20 @@ int mtk_clk_simple_remove(struct platform_device *pdev) struct device_node *node =3D pdev->dev.of_node; =20 of_clk_del_provider(node); - mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); + if (mcd->clks) + mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); + if (mcd->composite_clks) + mtk_clk_unregister_composites(mcd->composite_clks, + mcd->num_composite_clks, clk_data); + if (mcd->mux_clks) + mtk_clk_unregister_muxes(mcd->mux_clks, + mcd->num_mux_clks, clk_data); + if (mcd->factor_clks) + mtk_clk_unregister_factors(mcd->factor_clks, + mcd->num_factor_clks, clk_data); + if (mcd->fixed_clks) + mtk_clk_unregister_fixed_clks(mcd->fixed_clks, + mcd->num_fixed_clks, clk_data); mtk_free_clk_data(clk_data); =20 return 0; diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index dd43235285db..1d036ba6ca07 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -220,7 +220,17 @@ void mtk_clk_unregister_ref2usb_tx(struct clk_hw *hw); struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; + const struct mtk_composite *composite_clks; + size_t num_composite_clks; + const struct mtk_fixed_clk *fixed_clks; + size_t num_fixed_clks; + const struct mtk_fixed_factor *factor_clks; + size_t num_factor_clks; + const struct mtk_mux *mux_clks; + size_t num_mux_clks; const struct mtk_clk_rst_desc *rst_desc; + spinlock_t *clk_lock; + bool shared_io; }; =20 int mtk_clk_simple_probe(struct platform_device *pdev); --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D082CC4332F for ; Fri, 23 Dec 2022 09:44:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236264AbiLWJoj (ORCPT ); Fri, 23 Dec 2022 04:44:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230284AbiLWJoT (ORCPT ); Fri, 23 Dec 2022 04:44:19 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 275EA37F91; Fri, 23 Dec 2022 01:43:27 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BC1506602CEA; Fri, 23 Dec 2022 09:43:24 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788606; bh=kSf24d+l6ie0Bp+huwOu4Hdsuv2jfHEiIOETIGVoitY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kHjzrhQqUKKwcumLy9ynCwXkBY1AdHTy81qCE40ZtGTGhkkPDx+tS7zx83K3Ytms8 LreW2y8wWMl7bFEvns9z45fuSQqSCYxEuxHKpg1YGGEFNPp/eXuzzkuHSLsbTqY+a6 wfqlQ5I9JjP99f/HUnJ9iR3aZFmvmANodMt1IREBED1LZOIlByF66lTuZmrauNeHVe Esoj6yG/hz7Z9fvuRE36vB2Cm1z/byC43+qENFE9sMm3sEQTDrkH71TyhhKZKtw2/Q 2vAfKNL1NESIdjhtsLnQOy/aZXrFmHWNz9M2EDaFGeReZvOOezyfEqmPycB+UskXbb AHnsjdcq5Ji4w== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 13/23] clk: mediatek: mt8173: Migrate pericfg/topckgen to mtk_clk_simple_probe() Date: Fri, 23 Dec 2022 10:42:49 +0100 Message-Id: <20221223094259.87373-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Function mtk_clk_simple_probe() gained the ability to register multiple clock types: migrate MT8173's pericfg and topckgen to this common probe function to reduce duplication and code size. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Miles Chen Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8173-pericfg.c | 75 ++++----------------- drivers/clk/mediatek/clk-mt8173-topckgen.c | 76 ++++------------------ 2 files changed, 27 insertions(+), 124 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8173-pericfg.c b/drivers/clk/mediat= ek/clk-mt8173-pericfg.c index 30c0fa263cc0..e87294b72c2c 100644 --- a/drivers/clk/mediatek/clk-mt8173-pericfg.c +++ b/drivers/clk/mediatek/clk-mt8173-pericfg.c @@ -46,6 +46,7 @@ static const struct mtk_composite peri_clks[] =3D { }; =20 static const struct mtk_gate peri_gates[] =3D { + GATE_DUMMY(CLK_DUMMY, "peri_gate_dummy"), /* PERI0 */ GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0), GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1), @@ -93,77 +94,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc =3D { .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), }; =20 +static const struct mtk_clk_desc peri_desc =3D { + .clks =3D peri_gates, + .num_clks =3D ARRAY_SIZE(peri_gates), + .composite_clks =3D peri_clks, + .num_composite_clks =3D ARRAY_SIZE(peri_clks), + .clk_lock =3D &mt8173_clk_lock, + .rst_desc =3D &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt8173_pericfg[] =3D { - { .compatible =3D "mediatek,mt8173-pericfg" }, + { .compatible =3D "mediatek,mt8173-pericfg", .data =3D &peri_desc }, { /* sentinel */ } }; =20 -static int clk_mt8173_pericfg_probe(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data; - int r; - void __iomem *base; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_PERI_NR_CLK); - if (IS_ERR_OR_NULL(clk_data)) - return -ENOMEM; - - r =3D mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), - clk_data, &pdev->dev); - if (r) - goto free_clk_data; - - r =3D mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, - &mt8173_clk_lock, clk_data, &pdev->dev); - if (r) - goto unregister_gates; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_composites; - - r =3D mtk_register_reset_controller(node, &clk_rst_desc); - if (r) - goto unregister_clk_hw; - - return 0; - -unregister_clk_hw: - of_clk_del_provider(node); -unregister_composites: - mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data); -unregister_gates: - mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8173_pericfg_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data); - mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data); - mtk_free_clk_data(clk_data); - - return 0; -} - static struct platform_driver clk_mt8173_pericfg_drv =3D { .driver =3D { .name =3D "clk-mt8173-pericfg", .of_match_table =3D of_match_clk_mt8173_pericfg, }, - .probe =3D clk_mt8173_pericfg_probe, - .remove =3D clk_mt8173_pericfg_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; module_platform_driver(clk_mt8173_pericfg_drv); =20 diff --git a/drivers/clk/mediatek/clk-mt8173-topckgen.c b/drivers/clk/media= tek/clk-mt8173-topckgen.c index c7323639c502..257961528fe2 100644 --- a/drivers/clk/mediatek/clk-mt8173-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8173-topckgen.c @@ -421,6 +421,7 @@ static const char * const i2s3_b_ck_parents[] =3D { }; =20 static const struct mtk_fixed_clk fixed_clks[] =3D { + FIXED_CLK(CLK_DUMMY, "topck_dummy", "clk26m", DUMMY_RATE), FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE), FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ= ), FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE), @@ -623,77 +624,28 @@ static const struct mtk_composite top_muxes[] =3D { MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1), }; =20 +static const struct mtk_clk_desc topck_desc =3D { + .fixed_clks =3D fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .clk_lock =3D &mt8173_top_clk_lock, +}; + static const struct of_device_id of_match_clk_mt8173_topckgen[] =3D { - { .compatible =3D "mediatek,mt8173-topckgen" }, + { .compatible =3D "mediatek,mt8173-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; =20 -static int clk_mt8173_topckgen_probe(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data; - void __iomem *base; - int r; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (IS_ERR_OR_NULL(clk_data)) - return -ENOMEM; - - r =3D mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk= _data); - if (r) - goto free_clk_data; - - r =3D mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - if (r) - goto unregister_fixed_clks; - - r =3D mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8173_top_clk_lock, clk_data, &pdev->dev); - if (r) - goto unregister_factors; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_composites; - - return 0; - -unregister_composites: - mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data); -unregister_factors: - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -unregister_fixed_clks: - mtk_clk_unregister_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_dat= a); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8173_topckgen_remove(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - struct device_node *node =3D pdev->dev.of_node; - - of_clk_del_provider(node); - mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data); - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_unregister_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_dat= a); - mtk_free_clk_data(clk_data); - - return 0; -} - static struct platform_driver clk_mt8173_topckgen_drv =3D { .driver =3D { .name =3D "clk-mt8173-topckgen", .of_match_table =3D of_match_clk_mt8173_topckgen, }, - .probe =3D clk_mt8173_topckgen_probe, - .remove =3D clk_mt8173_topckgen_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; module_platform_driver(clk_mt8173_topckgen_drv); =20 --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96178C4332F for ; Fri, 23 Dec 2022 09:45:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235834AbiLWJpF (ORCPT ); Fri, 23 Dec 2022 04:45:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236037AbiLWJoW (ORCPT ); Fri, 23 Dec 2022 04:44:22 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9837C379D1; Fri, 23 Dec 2022 01:43:28 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 33C7D6602CF5; Fri, 23 Dec 2022 09:43:26 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788607; bh=+5r0+X37dkosdusytuUq/Z+7ifnc20ly7nlXTCnoZBA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=crfqKeG70rjts/h7VW98kwWha+M24Iu3of6U9mL/JuOTvjSGPTjYhH06pfNfG7ODh bWWFtWB0lwBYcE0CJyRBfX225PwXqSN7w7Bjbt754NBNSMDGGDkh+48hEA0rT/vcQG 53j2z1CZoqPAELMKmsvrnRZBCeLSxC7KcpSnAfJwYeSu6XmEZQq0hSH4jPZ5lhE9Vn 5E0F+9dfSS/41OATna7JO6STFCnY4yvPmFo4GJ76E4ehyp5gXY+FTLAxzAEMA4jVKs 0SUqVHFa1Os3uqw7XAVLxaB3NHvTNXTpTp57hyVxQZwb99IdPSuDUQMyKzav5DsZU7 DH9Eo3o36UqQg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 14/23] clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs Date: Fri, 23 Dec 2022 10:42:50 +0100 Message-Id: <20221223094259.87373-15-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver is registered early in clk_mt8192_top_init_early() and then again in clk_mt8192_top_probe(): the difference between the two is that the early one is probed with CLK_OF_DECLARE_DRIVER and the latter is regularly probed as a platform_driver. Knowing that it is not necessary for this platform to register the TOP_CSW_F26M_D2 clock that early, move it to top_divs and register it with the others during platform_driver probe for topckgen; While at it, since the only reason why the early probe existed was to register that clock, remove that entirely - leaving this driver to use only platform_driver. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Miles Chen Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8192.c | 39 ++++++------------------------- 1 file changed, 7 insertions(+), 32 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 9a9d51bfb84d..ec9dc7fe848e 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -26,10 +26,6 @@ static const struct mtk_fixed_clk top_fixed_clks[] =3D { FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000), }; =20 -static const struct mtk_fixed_factor top_early_divs[] =3D { - FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2), -}; - static const struct mtk_fixed_factor top_divs[] =3D { FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0), FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0), @@ -95,6 +91,7 @@ static const struct mtk_fixed_factor top_divs[] =3D { FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10), FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16), FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20), + FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2), FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1), FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0), FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", = 1, 2, 0), @@ -1047,27 +1044,6 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), }; =20 -static struct clk_hw_onecell_data *top_clk_data; - -static void clk_mt8192_top_init_early(struct device_node *node) -{ - int i; - - top_clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!top_clk_data) - return; - - for (i =3D 0; i < CLK_TOP_NR_CLK; i++) - top_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); - - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_= clk_data); - - of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); -} - -CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen", - clk_mt8192_top_init_early); - /* Register mux notifier for MFG mux */ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) { @@ -1093,6 +1069,7 @@ static int clk_mt8192_reg_mfg_mux_notifier(struct dev= ice *dev, struct clk *clk) static int clk_mt8192_top_probe(struct platform_device *pdev) { struct device_node *node =3D pdev->dev.of_node; + struct clk_hw_onecell_data *top_clk_data; int r; void __iomem *base; =20 @@ -1100,17 +1077,17 @@ static int clk_mt8192_top_probe(struct platform_dev= ice *pdev) if (IS_ERR(base)) return PTR_ERR(base); =20 + top_clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); + if (!top_clk_data) + return; + r =3D mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_cl= ks), top_clk_data); if (r) return r; =20 - r =3D mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs)= , top_clk_data); - if (r) - goto unregister_fixed_clks; - r =3D mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_da= ta); if (r) - goto unregister_early_factors; + goto unregister_fixed_clks; =20 r =3D mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), no= de, &mt8192_clk_lock, top_clk_data, &pdev->dev); @@ -1150,8 +1127,6 @@ static int clk_mt8192_top_probe(struct platform_devic= e *pdev) mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_cl= k_data); unregister_factors: mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); -unregister_early_factors: - mtk_clk_unregister_factors(top_early_divs, ARRAY_SIZE(top_early_divs), to= p_clk_data); unregister_fixed_clks: mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data); --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F1C2C3DA6E for ; Fri, 23 Dec 2022 09:45:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236104AbiLWJpK (ORCPT ); Fri, 23 Dec 2022 04:45:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236211AbiLWJoX (ORCPT ); Fri, 23 Dec 2022 04:44:23 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DAC237FAD; Fri, 23 Dec 2022 01:43:30 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A03B76602D0D; Fri, 23 Dec 2022 09:43:27 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788608; bh=p4HuxSnc6rYIjz4n4YZOsHO8uVPvIY0fR52pGIHTaV4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aEtFMMjzr1Ic9EYQcGv+RtSahEiiR3Eiud0LCrk6AJp+Tjdsi//JSTCUJ1vTs0WND zE5FGQftHmWaXthWoFparZTgmhkYmN3fOahoNRIow2RTpHRkg+Kd5J57YhVJ1oOTHm 5OiM7xAN3xvXitMz4Yo6hQMJi0NNIdQ2icuauGrlA76RUIl/29fzA72GwNqqZGRvK9 fPjJ8aU9GZ3o4q+OjgoeKxWVIPn1Fy30EWmtYRQ9kdstbfF/DADe7F5TNNv+H6KEn6 IO8chWSw9ZHWWtLp+83+UQGQamAoonGEOjZS2QJaulXNFxuv2TXiePF+ih0Ws8UIsq ILW3+vCh1swJw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 15/23] clk: mediatek: mt8192: Join top_adj_divs and top_muxes Date: Fri, 23 Dec 2022 10:42:51 +0100 Message-Id: <20221223094259.87373-16-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These two are both mtk_composite arrays, one dependent on another, but that's something that the clock framework is supposed to sort out and anyway registering them separately isn't going to ease the framework's job in checking dependencies. Put the contents of top_adj_divs in top_muxes to join them together and register them in one shot. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8192.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index ec9dc7fe848e..702770326286 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -698,9 +698,7 @@ static struct mtk_composite top_muxes[] =3D { MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s_m_parents, 0x320= , 23, 1), MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s_m_parents, 0x320= , 24, 1), MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s_m_parents, 0x320= , 25, 1), -}; - -static const struct mtk_composite top_adj_divs[] =3D { + /* APLL_DIV */ DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0,= 0x328, 8, 0), DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1,= 0x328, 8, 8), DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2,= 0x328, 8, 16), @@ -1099,15 +1097,10 @@ static int clk_mt8192_top_probe(struct platform_dev= ice *pdev) if (r) goto unregister_muxes; =20 - r =3D mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs),= base, - &mt8192_clk_lock, top_clk_data, &pdev->dev); - if (r) - goto unregister_top_composites; - r =3D mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data, &pdev->dev); if (r) - goto unregister_adj_divs_composites; + goto unregister_top_composites; =20 r =3D clk_mt8192_reg_mfg_mux_notifier(&pdev->dev, top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk); @@ -1119,8 +1112,6 @@ static int clk_mt8192_top_probe(struct platform_devic= e *pdev) =20 unregister_gates: mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); -unregister_adj_divs_composites: - mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top= _clk_data); unregister_top_composites: mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_d= ata); unregister_muxes: --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3440C4332F for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788610; bh=qJD6neFrISC/cTuT2H409HfAsDBdlpEBNGJzQ7fGoL0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ks6XI8UlxDNSzxfGJZE27BhA1Pa2x9TXspFKv8xIOn9zGDkc9R8kbLBOrEDikIwES sjaoQwcb4hBpOj8W6ZlaF4b4qJ6ndvA9lyGSPGoHjIc+SAnET8tlAiYupIePfPzXc9 JjUsIS9CIYVVPJGcbgAZm1p3zp2Ndg+oSocisST3C82viOYHGHhmmAg+2K3RL7N7rW mHwdZPSpoi9G1qy/+DK9ifO5+n3J7XnoQ6+hGFixqe9P/LJIFTkIGZWmcWCTt/cORr B7+nTDPrbEGQda92QNR8nCleFsipf8GiXGeqLm7bDWi6RxfAlQjYG0wX1CPw2aEB9P /eeOqaHaZZRsQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 16/23] clk: mediatek: mt8186: Join top_adj_div and top_muxes Date: Fri, 23 Dec 2022 10:42:52 +0100 Message-Id: <20221223094259.87373-17-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Like done for MT8192, join the two to register them in one shot, as there's no point in doing that separately from one another. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8186-topckgen.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/media= tek/clk-mt8186-topckgen.c index d05143891b69..63befb1f492d 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -669,9 +669,6 @@ static struct mtk_composite top_muxes[] =3D { MUX(CLK_TOP_APLL_I2S4_MCK_SEL, "apll_i2s4_mck_sel", apll_mck_parents, 0x0= 320, 19, 1), MUX(CLK_TOP_APLL_TDMOUT_MCK_SEL, "apll_tdmout_mck_sel", apll_mck_parents, 0x0320, 20, 1), -}; - -static const struct mtk_composite top_adj_divs[] =3D { DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "apll_i2s0_mck_sel", 0x0320, 0, 0x0328, 8, 0), DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "apll_i2s1_mck_sel", @@ -747,26 +744,19 @@ static int clk_mt8186_topck_probe(struct platform_dev= ice *pdev) if (r) goto unregister_muxes; =20 - r =3D mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs),= base, - &mt8186_clk_lock, clk_data, &pdev->dev); - if (r) - goto unregister_composite_muxes; - r =3D clk_mt8186_reg_mfg_mux_notifier(&pdev->dev, clk_data->hws[CLK_TOP_MFG]->clk); if (r) - goto unregister_composite_divs; + goto unregister_composite_muxes; =20 r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - goto unregister_composite_divs; + goto unregister_composite_muxes; =20 platform_set_drvdata(pdev, clk_data); =20 return r; =20 -unregister_composite_divs: - mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), clk= _data); unregister_composite_muxes: mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data); unregister_muxes: @@ -787,7 +777,6 @@ static int clk_mt8186_topck_remove(struct platform_devi= ce *pdev) =20 of_clk_del_provider(node); mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), clk= _data); - mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data); mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_da= ta); mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),= clk_data); --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA6D2C4332F for ; Fri, 23 Dec 2022 09:45:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236309AbiLWJpU (ORCPT ); Fri, 23 Dec 2022 04:45:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236174AbiLWJo0 (ORCPT ); Fri, 23 Dec 2022 04:44:26 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFF79389CA; Fri, 23 Dec 2022 01:43:32 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8A0916602CE6; Fri, 23 Dec 2022 09:43:30 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788611; bh=Uhu9GD9MVCGtK+Cy9WGWrUBM/Iih3hCMigVFtPFuyag=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f7AZpSWd1k0sg1/RdUG0Z3mcp++c5+63TzpbY3wkuzEvxUmWAFe0ZMhy6UcgpVGuE 5zmyqn3X5FMe/ARef/u8nzErvv0y4oVaEirXW6/GFOd4rXWdJLqZX3dO7TtYxXWXCU Da7XYl2Fijq7LqRnIUWHmPHonAOdBhtcOGVN23CCR+LVYAaB88NqZwJ307RHwbE//7 KfW1vECTAGd6hp1tsmGlQjhNqY07HBJx9xZBbWWqeOwpUEbP7yp2zojwDRnsLw9zTz fSXMTTL6NaUZS84V6K6jxA02A7eF6rAOUvcotOgvoNo5KiJ8Iq67p3/jv3TbgSRRpZ ZwUAFqGf66THg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 17/23] clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs Date: Fri, 23 Dec 2022 10:42:53 +0100 Message-Id: <20221223094259.87373-18-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Join the two to register them in one shot. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8183.c | 34 +++++++++++++------------------ 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index f1d84c0730d5..be2a53b3a881 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -613,21 +613,6 @@ static const char * const apll_i2s5_parents[] =3D { "aud_2_sel" }; =20 -static struct mtk_composite top_aud_muxes[] =3D { - MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, - 0x320, 8, 1), - MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, - 0x320, 9, 1), - MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, - 0x320, 10, 1), - MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, - 0x320, 11, 1), - MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, - 0x320, 12, 1), - MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, - 0x328, 20, 1), -}; - static const char * const mcu_mp0_parents[] =3D { "clk26m", "armpll_ll", @@ -658,7 +643,19 @@ static struct mtk_composite mcu_muxes[] =3D { MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2), }; =20 -static struct mtk_composite top_aud_divs[] =3D { +static struct mtk_composite top_aud_comp[] =3D { + MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents, + 0x320, 8, 1), + MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents, + 0x320, 9, 1), + MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents, + 0x320, 10, 1), + MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents, + 0x320, 11, 1), + MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents, + 0x320, 12, 1), + MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents, + 0x328, 20, 1), DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel", 0x320, 2, 0x324, 8, 0), DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", @@ -1169,10 +1166,7 @@ static int clk_mt8183_top_probe(struct platform_devi= ce *pdev) mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, &mt8183_clk_lock, top_clk_data, &pdev->dev); =20 - mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), - base, &mt8183_clk_lock, top_clk_data, &pdev->dev); - - mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), + mtk_clk_register_composites(top_aud_comp, ARRAY_SIZE(top_aud_comp), base, &mt8183_clk_lock, top_clk_data, &pdev->dev); =20 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0DE9C4332F for ; Fri, 23 Dec 2022 09:45:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236253AbiLWJpe (ORCPT ); Fri, 23 Dec 2022 04:45:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236245AbiLWJo1 (ORCPT ); Fri, 23 Dec 2022 04:44:27 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63856389CD; Fri, 23 Dec 2022 01:43:34 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id F410F6602CE4; Fri, 23 Dec 2022 09:43:31 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788613; bh=TB2QhHFNzebUtVjzF6MRv2ASnqmZ72MkQz0OkWYeXmo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KPC7FPSj9LTlhYFP3851u8fVFh/LHpcxXQVw7iH3OD9wRtOwk0W87cbD9c3Xw+266 /Ch2BsVylfU3wGMS2ENX9wPRRgtQMYRaXROPkfq5QSbxxnzYn9IU2KsVMAxLUmQIMJ ypcd/IojllZzyAuM4lg3PFLzBrpZK3CENa7baO7kltwYiE5cq2azIeoZyAWE3Fo1tm HJbpKo4d01E4fxD/8lwu48c9WihtK0rQ1WXfFHjpVHXhxJIoPUXmBknifX6rKVusRE cJ1m711Cx8XbPWtT2dtVa4kXnyLMb/yHlH+rb5h+cxjzTI0pbH9eLLAD6fEHH2ZcMJ qU7nHjnbt7GAA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 18/23] clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe() Date: Fri, 23 Dec 2022 10:42:54 +0100 Message-Id: <20221223094259.87373-19-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for commonizing topckgen probe on various MediaTek SoCs clock drivers, add the ability to register the MFG MUX notifier in mtk_clk_simple_probe() by passing a custom notifier register function pointer, as this function will be slightly different across different SoCs. Signed-off-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mtk.c | 8 ++++++++ drivers/clk/mediatek/clk-mtk.h | 3 +++ 2 files changed, 11 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b0a6225cd7b2..df6281492fb6 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -533,6 +533,14 @@ int mtk_clk_simple_probe(struct platform_device *pdev) goto unregister_composites; } =20 + if (mcd->clk_notifier_func) { + struct clk *mfg_mux =3D clk_data->hws[mcd->mfg_clk_idx]->clk; + + r =3D mcd->clk_notifier_func(&pdev->dev, mfg_mux); + if (r) + goto unregister_clks; + } + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) goto unregister_clks; diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 1d036ba6ca07..bdbd36e3d794 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -231,6 +231,9 @@ struct mtk_clk_desc { const struct mtk_clk_rst_desc *rst_desc; spinlock_t *clk_lock; bool shared_io; + + int (*clk_notifier_func)(struct device *dev, struct clk *clk); + unsigned int mfg_clk_idx; }; =20 int mtk_clk_simple_probe(struct platform_device *pdev); --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F092C4167B for ; Fri, 23 Dec 2022 09:45:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236272AbiLWJpm (ORCPT ); Fri, 23 Dec 2022 04:45:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236261AbiLWJof (ORCPT ); Fri, 23 Dec 2022 04:44:35 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEC45389E7; Fri, 23 Dec 2022 01:43:35 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 6C23C6602CE5; Fri, 23 Dec 2022 09:43:33 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788614; bh=v4bpRy6DKVod2vAuX1EyO2724COnQa/afh1pvd8ocYY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eEn2dfthjG/4GnGSDwwDlU1QwHAl/XaG219W5YdvJ9oUoM/BtRLNUDmSHeWZyJwtC a7ylDktfreGa2Wmo+DO5FiTX8FnwoE5cONALNnlAdHsDfrkgK/SncW/Q5lv8H9hiWA KforuoSbXMxZiWvhvyrHd15P+96diTK1ptOOWs+8rC41uYWltGpfUN+or3TrcyKh9X DgrJpShBK8/aDEhx42CmIwq3JRPp1sPPEdGsm/nbMtmFjBwHdxmza0DrJSfcsF4YLq 9qIrsw55btGRI0iTFTjw8QzLyd5jkFNpVl0iuDnzqZ9RJKxMDF1BCHmi2YzrXZFo79 3wVgCVDaBtnJQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 19/23] clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe() Date: Fri, 23 Dec 2022 10:42:55 +0100 Message-Id: <20221223094259.87373-20-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the common simple probe function for MediaTek clock drivers can now register the MFG MUX notifier, it's possible to migrate MT8192's topckgen to that, allowing for some code size reduction. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8192.c | 80 +++++++------------------------ 1 file changed, 17 insertions(+), 63 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index 702770326286..adde457e6277 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1064,66 +1064,6 @@ static int clk_mt8192_reg_mfg_mux_notifier(struct de= vice *dev, struct clk *clk) return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); } =20 -static int clk_mt8192_top_probe(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *top_clk_data; - int r; - void __iomem *base; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - top_clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!top_clk_data) - return; - - r =3D mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_cl= ks), top_clk_data); - if (r) - return r; - - r =3D mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_da= ta); - if (r) - goto unregister_fixed_clks; - - r =3D mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), no= de, - &mt8192_clk_lock, top_clk_data, &pdev->dev); - if (r) - goto unregister_factors; - - r =3D mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8192_clk_lock, top_clk_data, &pdev->dev); - if (r) - goto unregister_muxes; - - r =3D mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - top_clk_data, &pdev->dev); - if (r) - goto unregister_top_composites; - - r =3D clk_mt8192_reg_mfg_mux_notifier(&pdev->dev, - top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk); - if (r) - goto unregister_gates; - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - top_clk_data); - -unregister_gates: - mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); -unregister_top_composites: - mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_d= ata); -unregister_muxes: - mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_cl= k_data); -unregister_factors: - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); -unregister_fixed_clks: - mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - top_clk_data); - return r; -} - static int clk_mt8192_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1158,9 +1098,6 @@ static const struct of_device_id of_match_clk_mt8192[= ] =3D { { .compatible =3D "mediatek,mt8192-apmixedsys", .data =3D clk_mt8192_apmixed_probe, - }, { - .compatible =3D "mediatek,mt8192-topckgen", - .data =3D clk_mt8192_top_probe, }, { /* sentinel */ } @@ -1193,9 +1130,26 @@ static const struct mtk_clk_desc peri_desc =3D { .num_clks =3D ARRAY_SIZE(peri_clks), }; =20 +static const struct mtk_clk_desc topck_desc =3D { + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .mux_clks =3D top_mtk_muxes, + .num_mux_clks =3D ARRAY_SIZE(top_mtk_muxes), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .clks =3D top_clks, + .num_clks =3D ARRAY_SIZE(top_clks), + .clk_lock =3D &mt8192_clk_lock, + .clk_notifier_func =3D clk_mt8192_reg_mfg_mux_notifier, + .mfg_clk_idx =3D CLK_TOP_MFG_PLL_SEL, +}; + static const struct of_device_id of_match_clk_mt8192_simple[] =3D { { .compatible =3D "mediatek,mt8192-infracfg", .data =3D &infra_desc }, { .compatible =3D "mediatek,mt8192-pericfg", .data =3D &peri_desc }, + { .compatible =3D "mediatek,mt8192-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; =20 --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFC9EC4332F for ; Fri, 23 Dec 2022 09:45:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236273AbiLWJpr (ORCPT ); Fri, 23 Dec 2022 04:45:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235994AbiLWJo5 (ORCPT ); Fri, 23 Dec 2022 04:44:57 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 624553B406; Fri, 23 Dec 2022 01:43:37 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id DA8EC6602CF1; Fri, 23 Dec 2022 09:43:34 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788616; bh=pTPLqgfggQOJQKnrG05/EFzS5SPhf9tzN93cDLVUrqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X8wy5ovIyLIxIvug3HIY8NistYqDDXZ4DHg4jbmoRV4Dun3JjpUA+f/Zos3gSmO3X iv6/0mAml0nTAvPRue79R1FAmBv6faDpUpynbqg2BIgaiE9uRFrIHNJ3euDL7FCBa3 kKSpxBBc09dZ60aWK6KVbuGKUdeXi259bi3z7NHbViobHYVK89s2dCuYa8apYCwHe3 wMy/U7btGKee5KRV1CgLOs9/H57/pHfqvIdseN511ybXAsgU0esN+zDGUqK5wLaaFY bbJCG6hmrquOFklKM/wPND6dKSmuB7LScx+fERErfT14rtWzhgyrwnMQv0wDGldWWk bAOLHhDjeFu/A== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 20/23] clk: mediatek: clk-mt8186-topckgen: Migrate to mtk_clk_simple_probe() Date: Fri, 23 Dec 2022 10:42:56 +0100 Message-Id: <20221223094259.87373-21-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As done with MT8192, migrate MT8186 topckgen away from a custom probe function and use mtk_clk_simple_{probe, remove}(). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Miles Chen Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt8186-topckgen.c | 101 ++++----------------- 1 file changed, 19 insertions(+), 82 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/media= tek/clk-mt8186-topckgen.c index 63befb1f492d..0fba88adf9fa 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -681,11 +681,6 @@ static struct mtk_composite top_muxes[] =3D { 0x0320, 4, 0x0334, 8, 0), }; =20 -static const struct of_device_id of_match_clk_mt8186_topck[] =3D { - { .compatible =3D "mediatek,mt8186-topckgen", }, - {} -}; - /* Register mux notifier for MFG mux */ static int clk_mt8186_reg_mfg_mux_notifier(struct device *dev, struct clk = *clk) { @@ -708,86 +703,28 @@ static int clk_mt8186_reg_mfg_mux_notifier(struct dev= ice *dev, struct clk *clk) return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); } =20 -static int clk_mt8186_topck_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - void __iomem *base; - - clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!clk_data) - return -ENOMEM; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - r =3D PTR_ERR(base); - goto free_top_data; - } - - r =3D mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_cl= ks), - clk_data); - if (r) - goto free_top_data; - - r =3D mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - if (r) - goto unregister_fixed_clks; - - r =3D mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), no= de, - &mt8186_clk_lock, clk_data, &pdev->dev); - if (r) - goto unregister_factors; - - r =3D mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8186_clk_lock, clk_data, &pdev->dev); - if (r) - goto unregister_muxes; - - r =3D clk_mt8186_reg_mfg_mux_notifier(&pdev->dev, - clk_data->hws[CLK_TOP_MFG]->clk); - if (r) - goto unregister_composite_muxes; - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_composite_muxes; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_composite_muxes: - mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data); -unregister_muxes: - mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_da= ta); -unregister_factors: - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -unregister_fixed_clks: - mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),= clk_data); -free_top_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8186_topck_remove(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - struct device_node *node =3D pdev->dev.of_node; - - of_clk_del_provider(node); - mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), clk= _data); - mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_da= ta); - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),= clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc topck_desc =3D { + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .mux_clks =3D top_mtk_muxes, + .num_mux_clks =3D ARRAY_SIZE(top_mtk_muxes), + .composite_clks =3D top_muxes, + .num_composite_clks =3D ARRAY_SIZE(top_muxes), + .clk_lock =3D &mt8186_clk_lock, + .clk_notifier_func =3D clk_mt8186_reg_mfg_mux_notifier, + .mfg_clk_idx =3D CLK_TOP_MFG, +}; =20 - return 0; -} +static const struct of_device_id of_match_clk_mt8186_topck[] =3D { + { .compatible =3D "mediatek,mt8186-topckgen", .data =3D &topck_desc }, + {} +}; =20 static struct platform_driver clk_mt8186_topck_drv =3D { - .probe =3D clk_mt8186_topck_probe, - .remove =3D clk_mt8186_topck_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt8186-topck", .of_match_table =3D of_match_clk_mt8186_topck, --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2985C4332F for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1671788617; bh=lhAgbGiQssmwHIXm3wihuG8LAzaIdgHauA5m3Nx1Vxg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ok4DPyA9c49wwx71pXS2AcVLjO9GFvxqEkTtRFth6756cQTZnb048PWwJdtJ/JsZv 8bzWpIXuQDB51KkD/ze+IH4x7hOYTvpyPtJxTcbhUC+pHSzuaMmN+YTVWMJHyE/LoT NZz15NkvqVp7L4jpO8eVcoO+B9F8KLU2GNNdi3X6/gYIhbC0IjHPiPHCni83mbRSAW Zguu/Os9hSytlOmCB4DvthMN4qyIgC2CBU/w1i5f47FiJwr2xnD6H00BdrPW3LaI1p BpQQHUySAbUsexW2x+oowzsoSjjOGIZHr8tPGTOeRIYbnrB8am8EzaC5U7DY2xR53B sdPO9YawqS3Ag== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 21/23] clk: mediatek: clk-mt6795-topckgen: Migrate to mtk_clk_simple_probe() Date: Fri, 23 Dec 2022 10:42:57 +0100 Message-Id: <20221223094259.87373-22-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Migrate away from custom probe functions and use the commonized mtk_clk_simple_{probe, remove}(). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Miles Chen Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt6795-topckgen.c | 84 ++++------------------ 1 file changed, 14 insertions(+), 70 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6795-topckgen.c b/drivers/clk/media= tek/clk-mt6795-topckgen.c index 19440fe5460d..e80fa588e309 100644 --- a/drivers/clk/mediatek/clk-mt6795-topckgen.c +++ b/drivers/clk/mediatek/clk-mt6795-topckgen.c @@ -523,86 +523,30 @@ static struct mtk_composite top_aud_divs[] =3D { DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c= , 4, 4), }; =20 +static const struct mtk_clk_desc topck_desc =3D { + .fixed_clks =3D fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .mux_clks =3D top_muxes, + .num_mux_clks =3D ARRAY_SIZE(top_muxes), + .composite_clks =3D top_aud_divs, + .num_composite_clks =3D ARRAY_SIZE(top_aud_divs), + .clk_lock =3D &mt6795_top_clk_lock, +}; =20 static const struct of_device_id of_match_clk_mt6795_topckgen[] =3D { - { .compatible =3D "mediatek,mt6795-topckgen" }, + { .compatible =3D "mediatek,mt6795-topckgen", .data =3D &topck_desc }, { /* sentinel */ } }; =20 -static int clk_mt6795_topckgen_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - void __iomem *base; - int ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - clk_data =3D mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!clk_data) - return -ENOMEM; - - ret =3D mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), c= lk_data); - if (ret) - goto free_clk_data; - - ret =3D mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data= ); - if (ret) - goto unregister_fixed_clks; - - ret =3D mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt6795_top_clk_lock, clk_data, &pdev->dev); - if (ret) - goto unregister_factors; - - ret =3D mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs= ), base, - &mt6795_top_clk_lock, clk_data, &pdev->dev); - if (ret) - goto unregister_muxes; - - ret =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (ret) - goto unregister_composites; - - return 0; - -unregister_composites: - mtk_clk_unregister_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), clk= _data); -unregister_muxes: - mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); -unregister_factors: - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -unregister_fixed_clks: - mtk_clk_unregister_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_dat= a); -free_clk_data: - mtk_free_clk_data(clk_data); - return ret; -} - -static int clk_mt6795_topckgen_remove(struct platform_device *pdev) -{ - struct device_node *node =3D pdev->dev.of_node; - struct clk_hw_onecell_data *clk_data =3D platform_get_drvdata(pdev); - - of_clk_del_provider(node); - mtk_clk_unregister_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), clk= _data); - mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_unregister_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_dat= a); - mtk_free_clk_data(clk_data); - - return 0; -} - static struct platform_driver clk_mt6795_topckgen_drv =3D { .driver =3D { .name =3D "clk-mt6795-topckgen", .of_match_table =3D of_match_clk_mt6795_topckgen, }, - .probe =3D clk_mt6795_topckgen_probe, - .remove =3D clk_mt6795_topckgen_remove, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, }; module_platform_driver(clk_mt6795_topckgen_drv); =20 --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DF5DC4332F for ; Fri, 23 Dec 2022 09:46:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236293AbiLWJqP (ORCPT ); Fri, 23 Dec 2022 04:46:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236094AbiLWJpB (ORCPT ); Fri, 23 Dec 2022 04:45:01 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DF003B422; Fri, 23 Dec 2022 01:43:40 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BAC966602D03; Fri, 23 Dec 2022 09:43:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788619; bh=hfLSNFYO1N3oGbd/PPfAVz7ORJ/6t7ABxEYaZXHA2pw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AzWc8aLUPhPJcSTa9F0o0yw5RCfx2BJtjMg55XZ5roP5O8N6CVWjkXOG9YSmDY3A8 26psj8q1xw6CiI3UCN9N0HhxoWc8fpwSst5ZsjiURSwnYgIa0FS1ZY/GU2eMUfGWiq DLw7twAIOSPwAtaMjMju+gV0aZl5Uf3Q+r3lFC92wNsCPqdZXCJx9kj6oIJ2x6nk14 LS1Gk+nZO+ENZD1FhSvFVwgmgr9o1I8Oyj6Bb91WhCv6UuLY4zkPMbj2WdkUv8TUCb sVxpqks6ahdoqCHBhRNrfodg6WBefBMMIS/iR5CbRtrrkbpSqUdMdO5o4HcY8iSf/N tVp9JfoLTX6xQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 22/23] clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled Date: Fri, 23 Dec 2022 10:42:58 +0100 Message-Id: <20221223094259.87373-23-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of calling clk_prepare_enable() on a bunch of clocks at probe time, set the CLK_IS_CRITICAL flag to the same as these are required to be always on, and this is the right way of achieving that. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Miles Chen Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++----------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/media= tek/clk-mt7986-topckgen.c index d7df9585787f..bf3088e6d9e3 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[] =3D { MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, 0x1C0, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, - 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", + f_26m_adc_parents, 0x020, 0x024, 0x028, + 24, 1, 31, 0x1C0, 11, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), /* CLK_CFG_3 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", - dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, - 0x1C0, 12), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, - 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, - 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", + dramc_md32_parents, 0x030, 0x034, 0x038, + 0, 1, 7, 0x1C0, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", + sysaxi_parents, 0x030, 0x034, 0x038, + 8, 2, 15, 0x1C0, 13, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", + sysapb_parents, 0x030, 0x034, 0x038, + 16, 2, 23, 0x1C0, 14, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15), @@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[] =3D { MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", - sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, - 0x1C0, 22), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", + sgm_reg_parents, 0x050, 0x054, 0x058, + 16, 1, 23, 0x1C0, 22, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), /* CLK_CFG_6 */ @@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[] =3D { f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, 0x1C0, 27), /* CLK_CFG_7 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", - f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, - 0x1C0, 28), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", + f_26m_adc_parents, 0x070, 0x074, 0x078, + 0, 1, 7, 0x1C0, 28, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", @@ -306,13 +315,6 @@ static int clk_mt7986_topckgen_probe(struct platform_d= evice *pdev) mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, &mt7986_clk_lock, clk_data, &pdev->dev); =20 - clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk); - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); =20 if (r) { --=20 2.39.0 From nobody Thu Nov 14 07:34:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39163C4332F for ; Fri, 23 Dec 2022 09:46:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236349AbiLWJqZ (ORCPT ); Fri, 23 Dec 2022 04:46:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236292AbiLWJpD (ORCPT ); Fri, 23 Dec 2022 04:45:03 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 908B63B430; Fri, 23 Dec 2022 01:43:41 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 2CEDF6602D23; Fri, 23 Dec 2022 09:43:39 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671788620; bh=PXg/FppXIPAwQaA1oQS+Wf5hDsh7ZOHb0BNVjLOTW5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GyCKHsYiwTJfdyb3tvjNEKRy9srzOulk2Ya2MQx/rDCK3OE5uc+cBwsh93H/RW/Nh S3lKvRxus8aICClNWQ2ZmgBMk4Z4bnuku9jB/WTulPVZCkDJTjoqP3RlMysZVaIf1g 0F4ha/KiKMLidSJRb28cfjaXcxo1ZkdE5NioJxeTeRZXV6QwQthoIWpcQpvrskgwl/ gyfXdje9yNZYqE4juN/dCQFoFEXHBQ1qJmk3Lh2LpQ/11G1XQnaehn/mtw+Mmgl+NE M2zOt9WpwgxElRPdvIAPwYHte89xuHCum3hLilf5io2BSkGGLJwhzPuAoj9ETOKQVp tr5uUzfwS/Q9A== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 23/23] clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() Date: Fri, 23 Dec 2022 10:42:59 +0100 Message-Id: <20221223094259.87373-24-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> References: <20221223094259.87373-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are no more non-common calls in clk_mt7986_topckgen_probe(): migrate this driver to mtk_clk_simple_probe(). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Reviewed-by: Miles Chen Tested-by: Chen-Yu Tsai Tested-by: Miles Chen --- drivers/clk/mediatek/clk-mt7986-topckgen.c | 52 +++++----------------- 1 file changed, 12 insertions(+), 40 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/media= tek/clk-mt7986-topckgen.c index bf3088e6d9e3..286418aa00a0 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -290,52 +290,24 @@ static const struct mtk_mux top_muxes[] =3D { 0x1C4, 5), }; =20 -static int clk_mt7986_topckgen_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node =3D pdev->dev.of_node; - int r; - void __iomem *base; - int nr =3D ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + - ARRAY_SIZE(top_muxes); - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data =3D mtk_alloc_clk_data(nr); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt7986_clk_lock, clk_data, &pdev->dev); - - r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_topckgen_data; - } - return r; - -free_topckgen_data: - mtk_free_clk_data(clk_data); - return r; -} +static const struct mtk_clk_desc topck_desc =3D { + .fixed_clks =3D top_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(top_fixed_clks), + .factor_clks =3D top_divs, + .num_factor_clks =3D ARRAY_SIZE(top_divs), + .mux_clks =3D top_muxes, + .num_mux_clks =3D ARRAY_SIZE(top_muxes), + .clk_lock =3D &mt7986_clk_lock, +}; =20 static const struct of_device_id of_match_clk_mt7986_topckgen[] =3D { - { .compatible =3D "mediatek,mt7986-topckgen", }, + { .compatible =3D "mediatek,mt7986-topckgen", .data =3D &topck_desc }, {} }; =20 static struct platform_driver clk_mt7986_topckgen_drv =3D { - .probe =3D clk_mt7986_topckgen_probe, + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, .driver =3D { .name =3D "clk-mt7986-topckgen", .of_match_table =3D of_match_clk_mt7986_topckgen, --=20 2.39.0