From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C6E0C4167B for ; Thu, 22 Dec 2022 14:10:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235435AbiLVOKe (ORCPT ); Thu, 22 Dec 2022 09:10:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235408AbiLVOKX (ORCPT ); Thu, 22 Dec 2022 09:10:23 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CC842B257 for ; Thu, 22 Dec 2022 06:10:20 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id u4-20020a17090a518400b00223f7eba2c4so1961355pjh.5 for ; Thu, 22 Dec 2022 06:10:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cc7r9O2TO3pF/bzpTzvG4eE42PWinenWOWxZc+pKlHA=; b=evQOTlT+ScdTzw7R0+cnw30Kh4LVQVb71IGJvJANVBN1kZNocX8LcwnbqIiV/KPTgl Y7gD3vZkqzAtHGfjj306ruMQFxWVMmX++xXspCl9y6sJdNDHKp8PUD9QPVrXN5JhKg6F PKILgrk+0Ux3/NYIGVnceyLfbMaTjp2JzYhEtd1knXZWW0u4F11nahLQKowKzAJM0qqE ZyYkYoBhCEJOH6Rrhqlf53q0KRVT8Mmw/CQOesTDplKV2/v+OZggjH+qlvktQrNi6LVi yJokU9WSql4qWt03hz8YdiLvi5xOPdS/D9Nu/t0sJ/3ChZHge1Px9m0NsQNoc9+p2uTf TM/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cc7r9O2TO3pF/bzpTzvG4eE42PWinenWOWxZc+pKlHA=; b=UDFlTRVq7hAW1rWgtstuyQugxNz3+9VnOl85Z8FImPi53tAxB9BuuFePSU4MXtBhFB 0PXtTVt2SkZXc8pH5IOu9dEhZZkUpVWbe3cM456hyZn+xCZHfYNnRW6XeFyUzQUZd6/1 vnmo7ialQbfNDf/1kUKp7cT79HwJJq3vog1oRL9+6HrHJcf+b4HPPlGLvrUQnm4pi3KG oidJNkR2fgq/uxd/PTuww1uviZwZ+TjVRzKB3/tNLeFMk80/RAoCQ05gY/HDo37HkhFW 80zwjN51xwrfTUuAgKaR+HcwX9VXX5BIe6cCp0eCyVfiqJtMblOAbFENn7UHO2Nb4tz9 Xq8A== X-Gm-Message-State: AFqh2kqOGHVU5bLcaGDPApZdcOECBXuUo5CMIvtWLtBrCAWamC3W3F9u HQ466uVgB8uyDGghtSsvJkRq X-Google-Smtp-Source: AMrXdXtc4PCcTsoEdGQ+r4p32wV7MJDvmK01njLPLzq3o3houTlMXljlyqQ2qxrApPwC8d8CcROeCA== X-Received: by 2002:a05:6a20:a88a:b0:b2:75d0:b702 with SMTP id ca10-20020a056a20a88a00b000b275d0b702mr5911195pzb.18.1671718220019; Thu, 22 Dec 2022 06:10:20 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:10:19 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 01/23] phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitions Date: Thu, 22 Dec 2022 19:39:39 +0530 Message-Id: <20221222141001.54849-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Following the other QMP PHY drivers like PCIe, let's remove the "_tbl" suffix from the qmp_phy_init_tbl definitions. This helps in maintaining the uniformity across all of the QMP PHY drivers. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 146 ++++++++++++------------ 1 file changed, 73 insertions(+), 73 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 318eea35b972..20fcdbef8c77 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -94,7 +94,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_= LAYOUT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -143,12 +143,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufs_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -162,7 +162,7 @@ static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl= [] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -218,12 +218,12 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_se= rdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), @@ -241,7 +241,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), }; =20 -static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15), QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f), @@ -253,7 +253,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), @@ -295,13 +295,13 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_se= rdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -320,7 +320,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), }; =20 -static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -331,7 +331,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -361,7 +361,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -370,7 +370,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -408,7 +408,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_t= bl[] =3D { =20 }; =20 -static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -418,7 +418,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -448,7 +448,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serd= es_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -460,7 +460,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -500,7 +500,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_t= bl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), }; =20 -static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] =3D { +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -632,12 +632,12 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v= 5 =3D { static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufs_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes_tbl), - .tx_tbl =3D msm8996_ufs_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx_tbl), - .rx_tbl =3D msm8996_ufs_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx_tbl), + .serdes_tbl =3D msm8996_ufs_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes), + .tx_tbl =3D msm8996_ufs_tx, + .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx), + .rx_tbl =3D msm8996_ufs_rx, + .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx), =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -655,14 +655,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { =20 .offsets =3D &qmp_ufs_offsets_v5, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -673,14 +673,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sdm845_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), - .tx_tbl =3D sdm845_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx_tbl), - .rx_tbl =3D sdm845_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx_tbl), - .pcs_tbl =3D sdm845_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), + .serdes_tbl =3D sdm845_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx_tbl =3D sdm845_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), + .rx_tbl =3D sdm845_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs_tbl =3D sdm845_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -693,14 +693,14 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D sm6115_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), - .tx_tbl =3D sm6115_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx_tbl), - .rx_tbl =3D sm6115_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx_tbl), - .pcs_tbl =3D sm6115_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), + .serdes_tbl =3D sm6115_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx_tbl =3D sm6115_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), + .rx_tbl =3D sm6115_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs_tbl =3D sm6115_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -713,14 +713,14 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8150_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), - .tx_tbl =3D sm8150_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx_tbl), - .rx_tbl =3D sm8150_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx_tbl), - .pcs_tbl =3D sm8150_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8150_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx_tbl =3D sm8150_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx_tbl =3D sm8150_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs_tbl =3D sm8150_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -731,14 +731,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -749,14 +749,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl =3D sm8350_ufsphy_tx_tbl, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl =3D sm8350_ufsphy_rx_tbl, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl =3D sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl =3D sm8350_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl =3D sm8350_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl =3D sm8350_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl =3D sm8350_ufsphy_pcs, + .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BAB4C001B2 for ; Thu, 22 Dec 2022 14:10:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235029AbiLVOKq (ORCPT ); Thu, 22 Dec 2022 09:10:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235427AbiLVOK2 (ORCPT ); Thu, 22 Dec 2022 09:10:28 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F02DB2B270 for ; Thu, 22 Dec 2022 06:10:26 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id t11-20020a17090a024b00b0021932afece4so5805283pje.5 for ; Thu, 22 Dec 2022 06:10:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yi1xWbOnxDxmF2vwvRCU/qhn/CNj2iY0yGv5yr0ER9k=; b=YmB8el9LZlKSw4a8VTVN6bvVCWLPsOXIkdinnFmr+DNu96BSrf0r0BOASpEwJUFoZE kVY/WdCAtwXAJPgkWgDMFI3u8IhbSxxIGZWOxXYqPDDayGQsfnTdvTquIK46/SzjIN+w 5aR6QPBNLy4dmF/yw7z5FjsaVHt+PQIorRQCpqQh1XRqM9pIZKTTJzfjr/YdqGZrc8wY x2wwom+E5iDGjhDrcBwWnwkYWrvI/qQ7Si+KGqvt3B1O0xsqJDT1a4IPnVafHIfpBMAP xYS0eD6ZRQcdUmkv+4iQcsKZAcaxyqGWUnj23mSXkMcUFGLBl2XpplIluRJAhoIX6867 YdYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yi1xWbOnxDxmF2vwvRCU/qhn/CNj2iY0yGv5yr0ER9k=; b=HCOYd85xoe3jPBSj8s8Xx2gd91Jqor+X0cNpUBtebwD73mSl4PktyEnR60fKuFXTU9 9DvFik1bzPV+7riqZDlPdbJ2LK2j5cWyTtSL/IMFqbzszcCt8Hn2o6uCtvdZGn5FmAbZ ywAFB6l/4X9FKs8afYnyytNcfm17q/U92Q6/P3zZ9mtsiUeX2uvqzM+wH4p47yseLYLu ZIaFfTNsjobjGOVYh/6QE3RziEtbUH5uD3Qh2tgs35UyslHKgjFtuR19/LplE9ICb7Qn dCeE3z6tEzJJg02WtrNRzuPvGQWmKhYkN2aWEgDk5nbEbB9iyNgJqWY4z4e36GfCAhcu YKhA== X-Gm-Message-State: AFqh2kpHOdG2mHQN4BohRsjgRPBg0/npi1fNPi37W0I1X4l2Ah2XWfc6 Zdn8ZiUiMdKb9nmfT1oGEHiE X-Google-Smtp-Source: AMrXdXs8M4YAIoWZxk5G4JFxjgergMFIppviTQ3Yd7nKf5vN97zHwQi/ETGWhzd1U/jE7H+Yv6t6kw== X-Received: by 2002:a05:6a21:c011:b0:af:fcb6:2ee2 with SMTP id bm17-20020a056a21c01100b000affcb62ee2mr8091773pzc.47.1671718226315; Thu, 22 Dec 2022 06:10:26 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.10.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:10:25 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 02/23] phy: qcom-qmp-ufs: Rename MSM8996 PHY definitions Date: Thu, 22 Dec 2022 19:39:40 +0530 Message-Id: <20221222141001.54849-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's rename all of the definitions to use "_ufsphy_". Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 20fcdbef8c77..35b77cd79e57 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -94,7 +94,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_= LAYOUT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -143,12 +143,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_tx[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] =3D { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; =20 -static const struct qmp_phy_init_tbl msm8996_ufs_rx[] =3D { +static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -629,15 +629,15 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v= 5 =3D { .rx2 =3D 0xa00, }; =20 -static const struct qmp_phy_cfg msm8996_ufs_cfg =3D { +static const struct qmp_phy_cfg msm8996_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufs_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufs_serdes), - .tx_tbl =3D msm8996_ufs_tx, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_tx), - .rx_tbl =3D msm8996_ufs_rx, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufs_rx), + .serdes_tbl =3D msm8996_ufsphy_serdes, + .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx_tbl =3D msm8996_ufsphy_tx, + .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), + .rx_tbl =3D msm8996_ufsphy_rx, + .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -1156,7 +1156,7 @@ static int qmp_ufs_probe(struct platform_device *pdev) static const struct of_device_id qmp_ufs_of_match_table[] =3D { { .compatible =3D "qcom,msm8996-qmp-ufs-phy", - .data =3D &msm8996_ufs_cfg, + .data =3D &msm8996_ufsphy_cfg, }, { .compatible =3D "qcom,msm8998-qmp-ufs-phy", .data =3D &sdm845_ufsphy_cfg, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F04F7C4167B for ; Thu, 22 Dec 2022 14:10:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235469AbiLVOKw (ORCPT ); Thu, 22 Dec 2022 09:10:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235408AbiLVOKl (ORCPT ); Thu, 22 Dec 2022 09:10:41 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0101A2B264 for ; Thu, 22 Dec 2022 06:10:32 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id o8-20020a17090a9f8800b00223de0364beso5812316pjp.4 for ; Thu, 22 Dec 2022 06:10:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hSdeYPXBZcLgtJpfdwsHsq49aCAnxIPn+ssC5xgP++w=; b=OQ4qTfwsaOnG6O+eSZKtRlHUkA53Dmf4ySsl27jGUfvwWLv4RpnT3hIZmVL+7UNf/S nnxuUJnrUHXVKBep+uxXdSwSI9mYGN8wOlk148F33gYqL0rWHJEflpEGHkSn2qC6SC4/ wdQ9jeW/rUWHFfUCQGfL6FhSRRilCYq6sk8fxxHMpT22IgUxexveh3Df7CDgCTaVtsJy GWnSl6QhX3+4ReqjPW8R9XL1kEwo6TlNdWYU0qz6qapeJdI2bFpPxpwJjx8o6w+da26l MT4Gj1iq9FpksLTcTokVeNv4jo9Nx9YF9MdPEAGEtVhmYFBO6jxbIo5bDt/5MoOAajhs nSPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hSdeYPXBZcLgtJpfdwsHsq49aCAnxIPn+ssC5xgP++w=; b=5mbmcth7nl7kedHmbD1OYBdu76CvcECJfjyG+H61tp6op7XtYB7RM/fVU8vP0uIq3p gRP1RJOxBI2BZF1hil1anR1xQM6mFXMkT3TQw56c1eZp4n0jeqFyOzQKgDVvbphmy8xV U9VatIDzCe9cHVLnjL8YtQVQDkQzGvDMWo39fs97fFRf9wmhUWr0W2dUP+hbMlxFp6yg WTeDZmu7aZUD3xSzuAmFTxOAcjmsa54Ebdosq5HWDBrLKYZbO8ync7RZLic+GRpdMc19 BSHugOXOfOnLUk5HvmA2v9fuCETw2aBLEAmmAlPTOCeL3AKk5+Soi5xh5InV+4+L4C0g w6NA== X-Gm-Message-State: AFqh2kqn0NF5Es8TLGSFe8lPQDLglqc8ipdvTO8Vxc44WslxyE/Xe6Cu o1oL/GmC5z74X42MNLgL5NTi X-Google-Smtp-Source: AMrXdXsncJgqGErka7sTdFIFIY8UVd8h2btWbSv6eSQTZXSBkyl+OrmPScXc3J04eCaJGpH8qWyRWQ== X-Received: by 2002:a05:6a21:3988:b0:ad:a09c:5734 with SMTP id ad8-20020a056a21398800b000ada09c5734mr7991871pzc.44.1671718232612; Thu, 22 Dec 2022 06:10:32 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.10.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:10:31 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 03/23] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct Date: Thu, 22 Dec 2022 19:39:41 +0530 Message-Id: <20221222141001.54849-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tbls. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 196 ++++++++++++++---------- 1 file changed, 113 insertions(+), 83 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 35b77cd79e57..516027e356f0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -527,21 +527,26 @@ struct qmp_ufs_offsets { u16 rx2; }; =20 +struct qmp_phy_cfg_tbls { + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes; + int serdes_num; + const struct qmp_phy_init_tbl *tx; + int tx_num; + const struct qmp_phy_init_tbl *rx; + int rx_num; + const struct qmp_phy_init_tbl *pcs; + int pcs_num; +}; + /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { int lanes; =20 const struct qmp_ufs_offsets *offsets; =20 - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_cfg_tbls tbls; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -632,12 +637,14 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v= 5 =3D { static const struct qmp_phy_cfg msm8996_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D msm8996_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), - .tx_tbl =3D msm8996_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), - .rx_tbl =3D msm8996_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), + .tbls =3D { + .serdes =3D msm8996_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx =3D msm8996_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(msm8996_ufsphy_tx), + .rx =3D msm8996_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(msm8996_ufsphy_rx), + }, =20 .clk_list =3D msm8996_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -655,14 +662,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { =20 .offsets =3D &qmp_ufs_offsets_v5, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -673,14 +682,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sdm845_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), - .tx_tbl =3D sdm845_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), - .rx_tbl =3D sdm845_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), - .pcs_tbl =3D sdm845_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), + .tbls =3D { + .serdes =3D sdm845_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx =3D sdm845_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sdm845_ufsphy_tx), + .rx =3D sdm845_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs =3D sdm845_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -693,14 +704,16 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .lanes =3D 1, =20 - .serdes_tbl =3D sm6115_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), - .tx_tbl =3D sm6115_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), - .rx_tbl =3D sm6115_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), - .pcs_tbl =3D sm6115_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm6115_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx =3D sm6115_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm6115_ufsphy_tx), + .rx =3D sm6115_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs =3D sm6115_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -713,14 +726,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8150_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), - .tx_tbl =3D sm8150_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), - .rx_tbl =3D sm8150_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), - .pcs_tbl =3D sm8150_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8150_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx =3D sm8150_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx =3D sm8150_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs =3D sm8150_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -731,14 +746,16 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -749,14 +766,16 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D= { static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .lanes =3D 2, =20 - .serdes_tbl =3D sm8350_ufsphy_serdes, - .serdes_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl =3D sm8350_ufsphy_tx, - .tx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl =3D sm8350_ufsphy_rx, - .rx_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl =3D sm8350_ufsphy_pcs, - .pcs_tbl_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls =3D { + .serdes =3D sm8350_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx =3D sm8350_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_tx), + .rx =3D sm8350_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs =3D sm8350_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -790,16 +809,40 @@ static void qmp_ufs_configure(void __iomem *base, qmp_ufs_configure_lane(base, tbl, num, 0xff); } =20 -static int qmp_ufs_serdes_init(struct qmp_ufs *qmp) +static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_= cfg_tbls *tbls) { - const struct qmp_phy_cfg *cfg =3D qmp->cfg; void __iomem *serdes =3D qmp->serdes; - const struct qmp_phy_init_tbl *serdes_tbl =3D cfg->serdes_tbl; - int serdes_tbl_num =3D cfg->serdes_tbl_num; =20 - qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num); + qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num); +} =20 - return 0; +static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_c= fg_tbls *tbls) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + void __iomem *tx =3D qmp->tx; + void __iomem *rx =3D qmp->rx; + + qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1); + qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1); + + if (cfg->lanes >=3D 2) { + qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2); + qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2); + } +} + +static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg= _tbls *tbls) +{ + void __iomem *pcs =3D qmp->pcs; + + qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num); +} + +static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_p= hy_cfg *cfg) +{ + qmp_ufs_serdes_init(qmp, &cfg->tbls); + qmp_ufs_lanes_init(qmp, &cfg->tbls); + qmp_ufs_pcs_init(qmp, &cfg->tbls); } =20 static int qmp_ufs_com_init(struct qmp_ufs *qmp) @@ -886,25 +929,12 @@ static int qmp_ufs_power_on(struct phy *phy) { struct qmp_ufs *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; - void __iomem *tx =3D qmp->tx; - void __iomem *rx =3D qmp->rx; void __iomem *pcs =3D qmp->pcs; void __iomem *status; unsigned int val; int ret; =20 - qmp_ufs_serdes_init(qmp); - - /* Tx, Rx, and PCS configurations */ - qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); - qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); - - if (cfg->lanes >=3D 2) { - qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); - qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); - } - - qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_ufs_init_registers(qmp, cfg); =20 ret =3D reset_control_deassert(qmp->ufs_reset); if (ret) --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72291C4332F for ; Thu, 22 Dec 2022 14:11:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235483AbiLVOK7 (ORCPT ); Thu, 22 Dec 2022 09:10:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235449AbiLVOKn (ORCPT ); Thu, 22 Dec 2022 09:10:43 -0500 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 780C42B604 for ; Thu, 22 Dec 2022 06:10:39 -0800 (PST) Received: by mail-pg1-x532.google.com with SMTP id f3so1407192pgc.2 for ; Thu, 22 Dec 2022 06:10:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/p+KNgANSr5uBHeX1FzcIMoLA4Ae3aZ8ABPlQd95kGE=; b=kwcMnFApASjLH34+IJRVUZAoeKisxzikTzT6bazUX+C3HMpTaJJoeRjhc83tn1EMlq C9+SN6eWRfRl1vrEDeFbF4HTvJ0PJF5Vx9l5EKv5PxF01+4rQ669wCD7I0Ok1kgVuuqk kWZl9pC28EbwyYF6KKy7k7fzRUQJbLFEJccsF9n6VDX6Hz/RfxpdMJmJ8v3u5+XbSC0R NhJ+8aDU4yOLhEnjlGQgmFpn02msqiWdhqz9pQFRtxgC3YjQjd98gUPdMSIPbwnaL8Lh RUfZM9cyPeL8ucQ4ILThSKAvvEPwtzrK8iLwYlg/7QCM8fBtnwCVNUKTn/6B/K0e4PxZ TIHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/p+KNgANSr5uBHeX1FzcIMoLA4Ae3aZ8ABPlQd95kGE=; b=U+5QzpT9gap/KseP5BYrgdHZ+VYrmZGYqXxj2AJLjSVsuSyaHuMdFLS7SsFzPJF7Hz rGBUhw7aQFRQsEwv0c6I+VLHatvHNiR6Jf/7iPGPxIyaGwAnYR+3IVNpBUcGPnoptnHB HsPXAF7HfS50lZ54o61C2ZADKPe1x6TriEsmYVk4BcmhIPX9vqZbUvnCOU6K4TGTgwwg fAjJB0t4TKzTTNiHNw0DyZbeMagH1mSiTLvzNY4AAeYNPgw1SwZ11k4gp1A4fW5l3SEF r/3lZykTA1MQO0mDk2Y4G9UMs87pZD/H4m2VKmxLN2rMhF/A6Hm3CzrALsu6UKwvbl03 8p3A== X-Gm-Message-State: AFqh2krGDlY3dyvZco9Kye5P2qA31JllgSr6wW02cGJdsh2c4t/LoUMI HfurZ4FclhtT2kxs7SwCLHur X-Google-Smtp-Source: AMrXdXvgrVn02a7jIirzsbGlIVgIxpWXsY5Kg7ocqVjDd6dguplca9rtJdReeG9FNTfJ9ppDQhCxDA== X-Received: by 2002:aa7:9f07:0:b0:575:cce2:cd83 with SMTP id g7-20020aa79f07000000b00575cce2cd83mr6116962pfr.5.1671718238959; Thu, 22 Dec 2022 06:10:38 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:10:38 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 04/23] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Date: Thu, 22 Dec 2022 19:39:42 +0530 Message-Id: <20221222141001.54849-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 516027e356f0..2d5dd336aeb2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -547,6 +547,8 @@ struct qmp_phy_cfg { =20 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_cfg_tbls tbls; + /* Additional sequence for HS Series B */ + const struct qmp_phy_cfg_tbls tbls_hs_b; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -580,6 +582,7 @@ struct qmp_ufs { struct reset_control *ufs_reset; =20 struct phy *phy; + u32 mode; }; =20 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -841,6 +844,8 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const= struct qmp_phy_cfg_tbls static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_p= hy_cfg *cfg) { qmp_ufs_serdes_init(qmp, &cfg->tbls); + if (qmp->mode =3D=3D PHY_MODE_UFS_HS_B) + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qmp, &cfg->tbls); qmp_ufs_pcs_init(qmp, &cfg->tbls); } @@ -1011,9 +1016,19 @@ static int qmp_ufs_disable(struct phy *phy) return qmp_ufs_exit(phy); } =20 +static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submo= de) +{ + struct qmp_ufs *qmp =3D phy_get_drvdata(phy); + + qmp->mode =3D mode; + + return 0; +} + static const struct phy_ops qcom_qmp_ufs_phy_ops =3D { .power_on =3D qmp_ufs_enable, .power_off =3D qmp_ufs_disable, + .set_mode =3D qmp_ufs_set_mode, .owner =3D THIS_MODULE, }; =20 --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17526C001B2 for ; Thu, 22 Dec 2022 14:11:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230267AbiLVOLK (ORCPT ); Thu, 22 Dec 2022 09:11:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235433AbiLVOKr (ORCPT ); Thu, 22 Dec 2022 09:10:47 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1237F2B for ; Thu, 22 Dec 2022 06:10:45 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id fy4so2054786pjb.0 for ; Thu, 22 Dec 2022 06:10:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jJtmctAn+JbZO04zA2NymL/wNMdvFkipKZ36ajZk2HE=; b=LCHG59LxknVI6ftLVZAgsbjGQERawPN5kaQfdYLk5gx6j1xmSgrXT0llnfQeddfjYQ BxLdIqaffhBEQgVtmTJ7hiOmnCDf5Fy7cruF9UDCpg5SJlkwzSizc9qVf4A+O6c6QdbB T26R/zObGbvuC0SzdUMmrcsVtDcvJ/gtRtw8xOB1NkBoouAaHpNdStXHHQBViiY9PhOz KBc9dsmdJbq4tAGLIKOTh2V4KimVCeQliSp8V1L98FmlAAxaMLW+PM22U8aBScaNk/o7 JZpygPeurIuplNzO37DOr37Ayg/IoPs53eb0IMHr5iowSqyLFtwVVeopbqRcNL3Rjs9G /f1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jJtmctAn+JbZO04zA2NymL/wNMdvFkipKZ36ajZk2HE=; b=dIBWKXVBapQyUpE6P3unhLqj0QPY9Cmtwz7wXkB8aHLpdr6V3Bp5hfS4Cg7NU1ULoJ 8FNUNRkL5HhXy/k6XjUWhChXzSjtKsM3rdYdyd+zrLXGhmN1QZmE9YO6GT08ohMdY17r NrNpXAxXMZ3ofQk4pmdPv/6431NLs0SxTjDRMQvmZOWx7RSf+v7rMFkG6bep8xveswfF /rXZs1NCGQpi3hPnLG0wKGigiTBlp0HrbVGrANKctLLHd+tqwbR0cyXXrH+YVEwVffTF AzxBuH6xol8JGjoRJ1Geq38rozE38gNCWf0gpeiFC8VxtNUlYX8NZsWArAUaZ0dIhyDU 5+UQ== X-Gm-Message-State: AFqh2krhHrm9n+M5WPZgl+AjjKryjJJ48MuM9qYHLrlRXhhugc98eATI ssguNGPRJ8nYjTkieZTePIB4 X-Google-Smtp-Source: AMrXdXuODHAKlzm+kUYY5r+nIkAqGSYXk5eu4+HN913mBLF3tfyN+JUHInK99T2mRCH3MoW7a1jVtQ== X-Received: by 2002:a17:90a:c717:b0:219:1338:ab14 with SMTP id o23-20020a17090ac71700b002191338ab14mr6710953pjt.22.1671718245249; Thu, 22 Dec 2022 06:10:45 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.10.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:10:44 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 05/23] phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode Date: Thu, 22 Dec 2022 19:39:43 +0530 Message-Id: <20221222141001.54849-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add separate tables_hs_g4 instance to allow the PHY driver to configure the PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and PCS register setting in tables_hs_g4 and the UFS driver can request the Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 2d5dd336aeb2..82be9b754e8e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -20,6 +20,7 @@ #include #include =20 +#include #include "phy-qcom-qmp.h" =20 /* QPHY_SW_RESET bit */ @@ -549,6 +550,8 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tbls tbls; /* Additional sequence for HS Series B */ const struct qmp_phy_cfg_tbls tbls_hs_b; + /* Additional sequence for HS G4 */ + const struct qmp_phy_cfg_tbls tbls_hs_g4; =20 /* clock ids to be requested */ const char * const *clk_list; @@ -583,6 +586,7 @@ struct qmp_ufs { =20 struct phy *phy; u32 mode; + u32 submode; }; =20 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -847,7 +851,11 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp= , const struct qmp_phy_cfg if (qmp->mode =3D=3D PHY_MODE_UFS_HS_B) qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qmp, &cfg->tbls); + if (qmp->submode =3D=3D UFS_HS_G4) + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4); qmp_ufs_pcs_init(qmp, &cfg->tbls); + if (qmp->submode =3D=3D UFS_HS_G4) + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4); } =20 static int qmp_ufs_com_init(struct qmp_ufs *qmp) @@ -1021,6 +1029,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy= _mode mode, int submode) struct qmp_ufs *qmp =3D phy_get_drvdata(phy); =20 qmp->mode =3D mode; + qmp->submode =3D submode; =20 return 0; } --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72045C4167B for ; Thu, 22 Dec 2022 14:11:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235563AbiLVOLa (ORCPT ); Thu, 22 Dec 2022 09:11:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235432AbiLVOLG (ORCPT ); Thu, 22 Dec 2022 09:11:06 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7E8015F14 for ; Thu, 22 Dec 2022 06:10:52 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id t2so2137209ply.2 for ; Thu, 22 Dec 2022 06:10:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o9omAklrqpfZyxXNjQKLM+f2vR/zFJU262W7A5ZbsSE=; b=eCCA8lwjX28cl1I4YARJYL1q+tmz3d7lBXoRhQ7cEhVX8iCZ3EjFLdnrslqWOrfBC+ mPqqw7e1Ve/o78H70eP7MpJDQOeVDDh+LEOIewasts20W+6k7PEmCI1Mr4jxpk8hCxJr xgOj8oT2Gu6q10xaGQ/jmaAGJ49+lpnPp9gapnGgHE0VB6WwjoVT2eosZktCGkDDl7Gs JpqRK6c9T3IcCW+fUGiUGBjb3k3O3bA3TcBTFlai9OExqY56G8ub0ooRsILiQkr9ogIu jRt97+ICE//Y49WpmB6G5TA5ZZPuA+tyrgn4hMTrPjP4n6w7nEWpLeyB4041Az09mMKj FeHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o9omAklrqpfZyxXNjQKLM+f2vR/zFJU262W7A5ZbsSE=; b=vL4i1fd9Wf5NeWsVaY9CpF67KvhTnWGvGS1xnPDHAcRJvtB0e3ldmBTf4bczLqmD65 ZYf2pki2Cl0C9m0Z/42mhNCG6NeQS/pohhyp3e5L9NobU8yye2/P3K2zCoHE6UCaZcFN ZYItXR9FFxJ64fPQDJ7q4bHmz3HwYEsSWuCes1qhn/EaKK8mYmKQYyIF2i1IoaPdTLXM 5uIQM1qOqBSY/vP7tCwsi8XxgJxFBH2YqpcxuP1uEDj5NnqnYPs9q0wxensAfGXrZcod 6H8U2+TcTOyq/nTo9GwMXEo9zg9gVZIZRmFyG0v5+/Z8ZbB3MA4u+1gJbUYSr3TqBQ5E kFfA== X-Gm-Message-State: AFqh2krTVEv0bvxToBH0qnSQGNgRrtPWucqHhPOJsR4MyvKLGPN5iIz5 69vqLpd5l//oK6+uKEJiINPh X-Google-Smtp-Source: AMrXdXv23qzrMH2l3EtKIYuSKpXlVDuhrUS9Z/YB7DDv3TZCMSCyB5PDKGeOqGybREqtc36YWxi0CQ== X-Received: by 2002:a05:6a20:93a1:b0:a5:cc8f:cd14 with SMTP id x33-20020a056a2093a100b000a5cc8fcd14mr8003394pzh.35.1671718252622; Thu, 22 Dec 2022 06:10:52 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.10.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:10:51 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 06/23] phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b Date: Thu, 22 Dec 2022 19:39:44 +0530 Message-Id: <20221222141001.54849-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since now there is support for configuring the HS Rate B mode properly, let's move the register setting to tbls_hs_b struct for all SoCs. This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 37 +++++++++++++++++++++---- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 82be9b754e8e..97d0baa9bac3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -214,8 +214,9 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; =20 @@ -291,8 +292,9 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; =20 @@ -357,8 +359,9 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; =20 @@ -406,7 +409,6 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[]= =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), - }; =20 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { @@ -444,8 +446,9 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serd= es[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; =20 - /* Rate B */ +static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; =20 @@ -679,6 +682,10 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -699,6 +706,10 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg =3D { .pcs =3D sdm845_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sdm845_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sdm845_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -721,6 +732,10 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg =3D { .pcs =3D sm6115_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm6115_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm6115_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -743,6 +758,10 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .pcs =3D sm8150_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8150_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -763,6 +782,10 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, @@ -783,6 +806,10 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .pcs =3D sm8350_ufsphy_pcs, .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b =3D { + .serdes =3D sm8350_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07E8DC4332F for ; Thu, 22 Dec 2022 14:11:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235586AbiLVOLr (ORCPT ); Thu, 22 Dec 2022 09:11:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235460AbiLVOLX (ORCPT ); Thu, 22 Dec 2022 09:11:23 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01C2C2B627 for ; Thu, 22 Dec 2022 06:11:00 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id fy4so2055399pjb.0 for ; Thu, 22 Dec 2022 06:11:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y1UFhNdO1o0gDS1tF9SgoK3kS5M8eBWT75QUSAO1ZD8=; b=VXRgTMDzptAXmy3p6keS8iCv7K9rStV+RmCHZ6O4p8JEQAyI6UyUk0RcWq26FhkAzn twntzqF5OchG+WwL1iEd4AYmHuIYHOLhiyIUHjdFy3oKzCY9mfGKMe7QVUtAoIrVMiEK gq3L54YZTWCRGdJbtapcQsIq3qqSEqk4EGB6vLt34WDE7ZA/JPp0wyJUJcz5PnsuJkbu jNmC23KIRddiyCcpcg8MbMSdrSD00qKHawmRLr/ALy22s9u7pIm1/WbFL19mAbFae5Ag pG+rRIFD6X9LSBSB4yPw6G8p9ky1SGminnDHqg08ikIOkOdjoVIVmVt9GcMJRdSRZcRo mcvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y1UFhNdO1o0gDS1tF9SgoK3kS5M8eBWT75QUSAO1ZD8=; b=U5OI7qJYJtJS8dBJtA7EZeTQ0eYwlYJGkAK1nS06BbbX4QSO30AsR4qG321o1Z3N7k 8JR5vMrPmypB/AI7A1ZyC5HgcYxfD040k50+UvYudFAWEwNizZtuauZq8OW1tmJsOPdG JT9O6bkng6s6De5C5nmyGxIYU4ffKPGABEWPS8yWDIg0lMP7n2WcD1lE0Wa+iTzJbel5 yoLL5c6c8uL5BlDJs93LgtcxFm7Re4WF2VEJD2zumd/LllAddFHK/4L4OnDlwoS3x7N0 81V/w7vBWFjr9h1cfhGdmGY2S+nnjewfGlgOWRKaTxHQm+LbsmSExAXfArtiukgjOtSP HRYg== X-Gm-Message-State: AFqh2kqeLlVHVM6ZYTZZUiWXOQeeDKXRJ+4ja41SQtBBK2A51RHGXP+/ NXO6icE1WK/dBoZYUz8a/mwd X-Google-Smtp-Source: AMrXdXtVSmwopXhBNErDAIBHL9PIZQQbI6ebbTSOyOk3c7y1Bth0/u5wG0sqe6cXDniS93SBsy62sg== X-Received: by 2002:a05:6a20:e187:b0:aa:c42:bab with SMTP id ks7-20020a056a20e18700b000aa0c420babmr7693887pzb.59.1671718260379; Thu, 22 Dec 2022 06:11:00 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:10:59 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 07/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC Date: Thu, 22 Dec 2022 19:39:45 +0530 Message-Id: <20221222141001.54849-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 97d0baa9bac3..269f96a0f752 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -374,6 +374,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[= ] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), @@ -411,6 +415,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[= ] =3D { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), @@ -421,6 +444,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -762,6 +790,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .serdes =3D sm8150_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8150_ufsphy_hs_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), + .rx =3D sm8150_ufsphy_hs_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), + .pcs =3D sm8150_ufsphy_hs_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AEF6C4332F for ; Thu, 22 Dec 2022 14:12:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235615AbiLVOL7 (ORCPT ); Thu, 22 Dec 2022 09:11:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235537AbiLVOL0 (ORCPT ); Thu, 22 Dec 2022 09:11:26 -0500 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C59FD2B63D for ; Thu, 22 Dec 2022 06:11:08 -0800 (PST) Received: by mail-pl1-x629.google.com with SMTP id n4so2142460plp.1 for ; Thu, 22 Dec 2022 06:11:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PjhqEcZi9Td36RUK5eNAZ85GKHfRYtV+dPqbkSJsJUI=; b=h0iHwq+TqY6y0bCUn7TWl0d91/6+m06yVi973wp+qILsZAsWL5EzITF7n5WsEvf2Ez BjK+Ca4wK4bIOTSCmVpCMy1TUUBZU4QwenKSjIXrAPi9R6us/zpftMjYWolbtkdUq7IX QEJNI+03MPc+UaSch/m2u2DQO5005GjMMjjl4UdU6wjb7Y0SAoz3vggWQzrmSkkWxMDc XqMj63nTUkECAqzq8+GnIglfLjwGLh0a8DQ5S+kynuxUC9qJZKF+tT5sQb8Z/xBtu6M7 ljSAsfHg7knLpPQD8y7BbpLNkJllWxaz5w0EIKJVMXoDcq7+l4up9LcbXZnpt+fgnfIA VFJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PjhqEcZi9Td36RUK5eNAZ85GKHfRYtV+dPqbkSJsJUI=; b=E24Qv+MQ7WBYwG4ZbIbIOlLT3pDOlj2T3wMCBa6m7ZbeAnF6WNnbqciSmIOEAHjawN cfFMG9/MgVkRJHli/Y6HlYgkT42bMZgRamkHsDjOgQCquWjchBkM6wcFGs7KzhPim7aL Ja9L6q3jUq+Ep4GUFXabF2naDgUSQe9b/YTmK4NEy/WX36Up3+PAyyD/CdPK8dZmmbAq kRYpIqVZYqKpk45cMjFUe7xFwB/K3hXVqbJP6yrBYbMCBul2rEU4mmLBiMrRUyzQH5zD rC2PgW6WbV1xw1lBibhd3Cbqx7BspdKW+cFf0DXLXtNh9++bYCqIwe+es8uoU2j8Y3oo uG/w== X-Gm-Message-State: AFqh2kpF/UJImjXUaucEnfQgUnkuY6r70N1W9AVxSA2eQuSvmMNBeyMq yAjeNxrhFGit3UVhEwfLANDE X-Google-Smtp-Source: AMrXdXvRZVK96O95OohJLaWDGCtpytRcTiaE0nBK56jaYF7DFH4I6NtmMbZ96ysZGMtOIQNSgwS1Ew== X-Received: by 2002:a05:6a20:94c3:b0:ad:dcdf:aaad with SMTP id ht3-20020a056a2094c300b000addcdfaaadmr7969416pzb.19.1671718268296; Thu, 22 Dec 2022 06:11:08 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:11:06 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 08/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC Date: Thu, 22 Dec 2022 19:39:46 +0530 Message-Id: <20221222141001.54849-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 62 ++++++++++++++++++- 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/q= ualcomm/phy-qcom-qmp-pcs-ufs-v5.h index bcca23493b7e..3aa4232f84a6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -13,6 +13,7 @@ #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 269f96a0f752..d5324c4e8513 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -449,6 +449,34 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_= g4_pcs[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), }; =20 +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -805,6 +833,38 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg =3D { .regs =3D sm8150_ufsphy_regs_layout, }; =20 +static const struct qmp_phy_cfg sm8250_ufsphy_cfg =3D { + .lanes =3D 2, + + .tbls =3D { + .serdes =3D sm8150_ufsphy_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx =3D sm8150_ufsphy_tx, + .tx_num =3D ARRAY_SIZE(sm8150_ufsphy_tx), + .rx =3D sm8150_ufsphy_rx, + .rx_num =3D ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs =3D sm8150_ufsphy_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_pcs), + }, + .tbls_hs_b =3D { + .serdes =3D sm8150_ufsphy_hs_b_serdes, + .serdes_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 =3D { + .tx =3D sm8250_ufsphy_hs_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), + .rx =3D sm8250_ufsphy_hs_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), + .pcs =3D sm8150_ufsphy_hs_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, + .clk_list =3D sdm845_ufs_phy_clk_l, + .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D sm8150_ufsphy_regs_layout, +}; + static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .lanes =3D 2, =20 @@ -1297,7 +1357,7 @@ static const struct of_device_id qmp_ufs_of_match_tab= le[] =3D { .data =3D &sm8150_ufsphy_cfg, }, { .compatible =3D "qcom,sm8250-qmp-ufs-phy", - .data =3D &sm8150_ufsphy_cfg, + .data =3D &sm8250_ufsphy_cfg, }, { .compatible =3D "qcom,sm8350-qmp-ufs-phy", .data =3D &sm8350_ufsphy_cfg, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E2A7C4332F for ; Thu, 22 Dec 2022 14:12:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235537AbiLVOMV (ORCPT ); Thu, 22 Dec 2022 09:12:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235408AbiLVOLo (ORCPT ); Thu, 22 Dec 2022 09:11:44 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C8382CCA7 for ; Thu, 22 Dec 2022 06:11:16 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id t2so2138217ply.2 for ; Thu, 22 Dec 2022 06:11:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YvxrIOSMwPwfBmbLwjUh7RSQgKGQFWcoHbzhG+iF/Ko=; b=WTuaje8tBT2fOIy1a89lMB6i5Ui5tAVSKgOIChDqLuXMxQfla11Z26p3l/4upQXjty hQWeqnUOuLVzQxm/O1+zc9CT1O+4OI5nySj2hdFdrLYHnYTHJoVhQsKKLkD+wvc/dW83 u3derLOcuSM4NHgyZ1D+A5NXU5HpWnDP7XStujDSVyEDXWHbPkrgm5DGI0fx5xyEOcsX wwI9tvGlrHeleujah3LHXJmJO3vehHZh6xYcInFXHu3xjMTkIB0ZIOy8Rx7h1ASPJVlE Ob1CAvP6zGAFCKiupTAcbsYV9foos269qV9m5jKYxNicOVBTd2ElbPW9T5wHcpy8MX5c nkUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YvxrIOSMwPwfBmbLwjUh7RSQgKGQFWcoHbzhG+iF/Ko=; b=xcXp0rgs+jIzpTPROB+6AFTzMHNyj2DKS7E+ljDYnulxTlLvEAFysZ8XlOCPMuTdrE XzGu10jeyhZ51dqwZPw2koclENgM9QNhMmSoLc5fpLG63Yu/nldnm9j4GZUOeXHKJvsn xudp7uu0s4iePmxURU48CsA4q0guFpKGRoPDKuG8xKfpCXllJvT9vP1NfOxXo9y7LTPw TgOHrVz2gny78fepqJFRCY9K7qJsMSA8+74Qsdk5DGoieYfnETFlgJ3mgd6jZwaaj54S Jew++iHU0plE+a9THmc+qoVvuDRhKdvLhtHPriBEIz2H1ZFTreL4dZANNKiFEebbSrM/ fMSQ== X-Gm-Message-State: AFqh2kryYPodIkhEETUNwNmvg+91kU2jTvxFIymG/ayJMRnmpEosigz4 A8WOvlwTz2CgPPmxG7Ukb6+B X-Google-Smtp-Source: AMrXdXuIDJp7seq7NruDAODEgmaT+tpNvsXqsojyyuPeLQ3wM9nFLZgl91mCfYZlnbwQbD/Vfa7yLw== X-Received: by 2002:a17:902:e382:b0:189:db2b:93ad with SMTP id g2-20020a170902e38200b00189db2b93admr5438517ple.2.1671718275957; Thu, 22 Dec 2022 06:11:15 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.11.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:11:15 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 09/23] phy: qcom-qmp-ufs: Avoid setting HS G3 specific registers Date: Thu, 22 Dec 2022 19:39:47 +0530 Message-Id: <20221222141001.54849-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SM8350 default init sequence sets some PCS registers to HS G3, thereby disabling HS G4 mode. This has the effect on MPHY capability negotiation between the host and the device during link startup and causes the PA_MAXHSGEAR to G3 irrespective of device max gear. Due to that, the agreed gear speed determined by the UFS core will become G3 only and the platform won't run at G4. So, let's remove setting these registers for SM8350 as like other G4 compatible platforms. One downside of this is that, when the board design uses non-G4 compatible device, then MPHY will continue to run in the default mode (G4) even if UFSHCD runs in G3. But this is the case for other platforms as well. Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index d5324c4e8513..6c7c6a06fe3b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -567,13 +567,6 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), - QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1DD1C4332F for ; Thu, 22 Dec 2022 14:12:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235441AbiLVOMq (ORCPT ); Thu, 22 Dec 2022 09:12:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230354AbiLVOMN (ORCPT ); Thu, 22 Dec 2022 09:12:13 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20A0B186F8 for ; Thu, 22 Dec 2022 06:11:23 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id 4so2134702plj.3 for ; Thu, 22 Dec 2022 06:11:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mYymTqvoOhBPPOAnLI+KgkyX1Ce28YSkotTXj3/YG7g=; b=YfdUM4XN4Dca6GAaveps63ZT+kNZRziwHJmJw73IfpVn/ZcBd29qI61/vkaB8tAATr deY/j9CXPBC8Rc9hsY7KX6xwt5rHoTeMf3JopW/z02KI+OPjKAU1OdMAHKoJ3Jehoniz SEq+zTqfXtN6ekV+kZVvP+iilGILNUst7ilaOLb0y8eJcTO053U8PmtLv7My9ohBRI/h UN0DpSDaw2uBJHa4P99Srf0HAKnfjlv3TjcGAzk8lalzt66Yn/DoRQiglN4BH9oxDZbV x/5LPVDSkPBQtbWwdvd/06p3zzT/Fn6XroTw0hIkW/F9uF0uIIQsZ2SBBPTo0DFv0ZTb Gn0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mYymTqvoOhBPPOAnLI+KgkyX1Ce28YSkotTXj3/YG7g=; b=EjAD9j27caqXbWqvZ2CFqETsQHWtcicdf2Vq78zA54N3EH67mD86qFhed5PtAggir3 Z5oxX1RNRn+VxG1sT7/vHaYJ5tothK9aMK+gb8MSR9PfYJkej8V2ctN58j88e5rxpxMw LzYCrgayJhTeJ1lsexwVXndOl4XfrbxkreAoGmdE9i23k4n/N07OKYJ3VwYJFnUPzPpj zvIEQya8JO2cGNOGSnavdbyImIIS86h3EfnZJiUCjLzEoPWdkDn2aOIOtm8ysurjUFqO OyBF8lQHGvTvRpgXWh6bQfWXycmXsieH9Xh29SYiU2gNYOBA1KJN+5Py0n7ywXfOA2IA Vtxw== X-Gm-Message-State: AFqh2krOfquHzRu2/SweiXWBwMZlupqGc/8aF5bH5wa66JORRp7NDoQG X5YUv/Vqzg37MpNt49P45xbJ X-Google-Smtp-Source: AMrXdXsnTe44WW6vmHDaoVVzPoWmTokdFFo5J7G0nEoXOVId8npB7GSlAUP6dvBhpCxkLRDtVI89+Q== X-Received: by 2002:a17:90a:410b:b0:221:5596:593b with SMTP id u11-20020a17090a410b00b002215596593bmr6949964pjf.5.1671718283435; Thu, 22 Dec 2022 06:11:23 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:11:22 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 10/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC Date: Thu, 22 Dec 2022 19:39:48 +0530 Message-Id: <20221222141001.54849-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 6c7c6a06fe3b..75e55c4181c9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -571,6 +571,34 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs= [] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; =20 +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] =3D { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + struct qmp_ufs_offsets { u16 serdes; u16 pcs; @@ -875,6 +903,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg =3D { .serdes =3D sm8350_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8350_ufsphy_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx =3D sm8350_ufsphy_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs =3D sm8350_ufsphy_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90ECFC4332F for ; Thu, 22 Dec 2022 14:13:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235521AbiLVONG (ORCPT ); Thu, 22 Dec 2022 09:13:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235520AbiLVOMU (ORCPT ); Thu, 22 Dec 2022 09:12:20 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB545286CF for ; Thu, 22 Dec 2022 06:11:31 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id n65-20020a17090a2cc700b0021bc5ef7a14so2015008pjd.0 for ; Thu, 22 Dec 2022 06:11:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4X1A4TMvEV2bS5ohL9A0SpECVAvBKwWjyx8LJOjuk7U=; b=BxWVBMysDolWbx+Cppe3zn3m/KFARMGNqquNzCFgm75WofleLqYgk94x2rBFTc9Tvl MZBxo2wNJc4SWqNe81JTB57k0Z9JvK4i7vYyp8pREFAEhZvECn0YN+yQpOEEQoAdW96g Ncxo0MsLT3eNWetF7L6BRXvxqUXOLujvVgRPGzz+TfrkDHDGn6HL+Ao4kbaTlgGUaK6I 8s7CDXnQPue+wbvAJXkvx3PqI8LwdJGqisMXJTTxK2jM1BQq3MM2uv7nVXM2+FVDYmWb ELL6DrURh9fTN/RBhRYcl7VaLD2A3s5w4uUj9klBISsKgTNuMTAhE7ydRglDOnG30Hx8 sX8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4X1A4TMvEV2bS5ohL9A0SpECVAvBKwWjyx8LJOjuk7U=; b=CPWLpz9PVRtr9Xj2GnbT0bJwgc+LuCiWef0ZX01fBV2DFrksjIR8ade+dCEXS76qnK GgIR4MtU9tnpFobTDFhNEVYw7/yXrAinQWan0LDI7pDPH4Dgr5vvt/veWGrrrMBe0rGe 3dlCpwjciz8irTi5kAUuC9WeFcEya0BuVO/K9MSJVOiWOgKs64OCTrVx0B3gufuGB20d C0Z48yeiqAAUze4aeHCIGvCjx0cPnwJh28ln41Chl55BA+NAc/h1VGFsbEENZe8JW04e oI+mP6a18pYpg0n080CHpeVGSONGuB2XTjVDZICJCfo+ameOj3pPf8V2e++oQRXA6fUp TBwQ== X-Gm-Message-State: AFqh2krqvIRgmJJm8ZgVM1Zteb09+VwoeM4kcP6H8uwgt4OqlZT9ZhuE 7/gvvix6b6PnW3D5xcvi2f/l X-Google-Smtp-Source: AMrXdXuZk/NEnRPNupNCna4VffVs4EjjF+9WNS/4kFEQ/Zy/NZFN/ZFkZIxohRNAc1flJSboQdPzHg== X-Received: by 2002:a05:6a20:d80a:b0:ad:f82d:78ad with SMTP id iv10-20020a056a20d80a00b000adf82d78admr7597717pzb.46.1671718291165; Thu, 22 Dec 2022 06:11:31 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:11:30 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 11/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC Date: Thu, 22 Dec 2022 19:39:49 +0530 Message-Id: <20221222141001.54849-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 75e55c4181c9..96e03d4249da 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -935,6 +935,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg =3D { .serdes =3D sm8350_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8350_ufsphy_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx =3D sm8350_ufsphy_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs =3D sm8350_ufsphy_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list =3D sm8450_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0E22C4332F for ; Thu, 22 Dec 2022 14:13:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235582AbiLVONa (ORCPT ); Thu, 22 Dec 2022 09:13:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235564AbiLVOMf (ORCPT ); Thu, 22 Dec 2022 09:12:35 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DE1730559 for ; Thu, 22 Dec 2022 06:11:39 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id n65-20020a17090a2cc700b0021bc5ef7a14so2015387pjd.0 for ; Thu, 22 Dec 2022 06:11:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9LXdGVP9dxpaOugOFMrnDCyUZiHcY/u5VEvcCrjnpKE=; b=sEAZuCy9o1mSeZ+mOAF+2MpfasokgDnmXc8LSn05lHnTxhCmTkhTVkPygFTTLKDhiZ nixCIHoQz4+ceVMPOV8l6CPCGmNL/nQjE9wXY0f8N/Q+1xbJBuaj9EvBybl6jYyWiAan 5fTz+ssWMIA3tVSpty3OIwg8gkvJeC8aonGebs/3otg1iGl50Ji8OhiTV8RXiKqD/feM ywqCABVk3r5mwBOVSldMLZp+krnjPcA50oIL3rr6aAMp9BZ2KcgPsj1oWVAj/bUP4RYZ FXX/RgA1P5h3cIVDjosBxIxNQqMJnztYhdcW/7dU/63ub1u9hqkA8c4B6Wq7g6lN2lvd lLIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9LXdGVP9dxpaOugOFMrnDCyUZiHcY/u5VEvcCrjnpKE=; b=ukEmwh25vk0XEcckhAsIXlJYEZn5BjBnwO6oMQgimGouALgGqtCqp7dvFztCYHlyvN +OmG5Q+g1b9JuKJh+7q7FjoI1x3aKHuMtRFXS79Fm/tl3gxR4IRLwcBWrx613A7i/477 JeVgtpJx1lx7Zve8cLEj8ylqg59sF0gFtsW9LKaXHq3Jd9+6QiJ+FHwUA2GVNO2fILrp xAeoVJZYic/DrXUWlbEHUYt556+A78F1vsEuYfw0fTJbWySINX680gVLpYVOS0i1d3MN 5saoKgZXkCmHuiOWks7HZ1KoVdMpq0ETGZPBZSFkTCk42Nsm4YYgGNC5fiW+1kWDuHLi KoYg== X-Gm-Message-State: AFqh2kr7j7y6tuvfsIMb/CtgCBBYQeaMLGs8KnuABbobSLLFks4/ELXW RxE9HMXvi/Qx7UxvKXR9O3+d X-Google-Smtp-Source: AMrXdXs6kCUEn/CZL/Ia+qJ9szz8RsqG0cT+AqgbrzlUI0r6MdzQNrClwbaz2RWxvRBh3//sVlCyrQ== X-Received: by 2002:a17:902:ef89:b0:189:bcf7:1ec0 with SMTP id iz9-20020a170902ef8900b00189bcf71ec0mr6659380plb.30.1671718298860; Thu, 22 Dec 2022 06:11:38 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.11.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:11:38 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 12/23] phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoC Date: Thu, 22 Dec 2022 19:39:50 +0530 Message-Id: <20221222141001.54849-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm= /phy-qcom-qmp-ufs.c index 96e03d4249da..9f5526758985 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -763,6 +763,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = =3D { .serdes =3D sm8350_ufsphy_hs_b_serdes, .serdes_num =3D ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 =3D { + .tx =3D sm8350_ufsphy_g4_tx, + .tx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx =3D sm8350_ufsphy_g4_rx, + .rx_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs =3D sm8350_ufsphy_g4_pcs, + .pcs_num =3D ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list =3D sdm845_ufs_phy_clk_l, .num_clks =3D ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list =3D qmp_phy_vreg_l, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A234C4332F for ; Thu, 22 Dec 2022 14:13:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235453AbiLVONs (ORCPT ); Thu, 22 Dec 2022 09:13:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235508AbiLVOMt (ORCPT ); Thu, 22 Dec 2022 09:12:49 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06B4C286F6 for ; Thu, 22 Dec 2022 06:11:47 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id x3so2010009pjv.4 for ; Thu, 22 Dec 2022 06:11:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wk23XQcB7rWWaun21vg4rh/lMbr7XJx+tFtAaECKMIs=; b=efdVnc4a1fTjXMefZQ8O6qfQSWgPtr0YgTtbWmujBkgiHB/EmiMdEsMRZS6gTqhAbn N7ftNrg/LxFeeRdH5+0d9ZKrloHtco0KpHDUWXX1wHuyKTKsiXHOn1jCchyoL0lCkRie d+xfCaV4bCpoKPB90ZZ5vewCCOGWXOoI3JRrjpUVRD95+NqIED+ZWrXfm91xmACZb8ul wRtXFW2pdiXSY9Y5GqixUUIRmH0tdzxrD0iro0Rp89DuI6PmzQh29tvrCP5mP+ga1tAg FMcj5xAxKkTYf0Lp18YBj/cd5P23Rfed3JlW9vS42Ggq4tGzdMO5bLLuK8tnx7uccbPJ RgYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wk23XQcB7rWWaun21vg4rh/lMbr7XJx+tFtAaECKMIs=; b=4EEFG2OHszf9Ki53WGrPdPge8Y5uWhM+XTiitERqhQIysnVLSNnuUMvdzIPwI82jiV crt1zk2VNOzfszPUY3ihCzmoEyyVs/tKEE4hLAb138hHRVGavltb0QBZCP3wAp//q43u YU0LxkKBxpw+c5HFS7IYqWzu9IXy3qE7s4TpqEvqRoN6o8ESlqN8np0dNvU2zKVkwlrk sSKitK1+b0TPCk+NZKmDcEa4HKdUl5R5DhExEAHm9Z1H1ExRJwCUKamEfSx7+crzDoLl cYg5oMxMiu6jjV/dYD+IIkGEdHt30cGAPYhU8/yg9tVCLdCNkg9VfAHwkVI2Mz3MIdVw zgqQ== X-Gm-Message-State: AFqh2kqwU8l5datdiV6TujJ8wqfwkYEMatUxsbDN75BL0ArsvmUYhBl5 u00woEHRWbkVx9svOL+wbELR X-Google-Smtp-Source: AMrXdXsxkQDnAnFP3IvqHANLji95yNzDSOs5sq+krGPRDyxbB2a4AzNx33D2wlOGSbwix+zTLRSmxg== X-Received: by 2002:a17:902:7792:b0:189:d0f7:dfbe with SMTP id o18-20020a170902779200b00189d0f7dfbemr22457165pll.30.1671718306431; Thu, 22 Dec 2022 06:11:46 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:11:45 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 13/23] scsi: ufs: ufs-qcom: Remove un-necessary goto statements Date: Thu, 22 Dec 2022 19:39:51 +0530 Message-Id: <20221222141001.54849-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" goto in error path is useful if the function needs to do cleanup other than returning the error code. But in this driver, goto statements are used for just returning the error code in many places. This really makes it hard to read the code. So let's get rid of those goto statements and just return the error code directly. Reviewed-by: Dmitry Baryshkov Reviewed-by: Asutosh Das Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 100 +++++++++++++++--------------------- 1 file changed, 41 insertions(+), 59 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8ad1415e10b6..7cd996ac180b 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -110,7 +110,7 @@ static void ufs_qcom_disable_lane_clks(struct ufs_qcom_= host *host) =20 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) { - int err =3D 0; + int err; struct device *dev =3D host->hba->dev; =20 if (host->is_lane_clks_enabled) @@ -119,7 +119,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) err =3D ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", host->rx_l0_sync_clk); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", host->tx_l0_sync_clk); @@ -137,7 +137,8 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) goto disable_rx_l1; =20 host->is_lane_clks_enabled =3D true; - goto out; + + return 0; =20 disable_rx_l1: clk_disable_unprepare(host->rx_l1_sync_clk); @@ -145,7 +146,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_ho= st *host) clk_disable_unprepare(host->tx_l0_sync_clk); disable_rx_l0: clk_disable_unprepare(host->rx_l0_sync_clk); -out: + return err; } =20 @@ -160,25 +161,25 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_ho= st *host) err =3D ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", &host->rx_l0_sync_clk, false); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", &host->tx_l0_sync_clk, false); if (err) - goto out; + return err; =20 /* In case of single lane per direction, don't read lane1 clocks */ if (host->hba->lanes_per_direction > 1) { err =3D ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", &host->rx_l1_sync_clk, false); if (err) - goto out; + return err; =20 err =3D ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", &host->tx_l1_sync_clk, true); } -out: - return err; + + return 0; } =20 static int ufs_qcom_check_hibern8(struct ufs_hba *hba) @@ -241,7 +242,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) =20 if (!host->core_reset) { dev_warn(hba->dev, "%s: reset control not set\n", __func__); - goto out; + return 0; } =20 reenable_intr =3D hba->is_irq_enabled; @@ -252,7 +253,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) if (ret) { dev_err(hba->dev, "%s: core_reset assert failed, err =3D %d\n", __func__, ret); - goto out; + return ret; } =20 /* @@ -274,15 +275,14 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) hba->is_irq_enabled =3D true; } =20 -out: - return ret; + return 0; } =20 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct phy *phy =3D host->generic_phy; - int ret =3D 0; + int ret; bool is_rate_B =3D UFS_QCOM_LIMIT_HS_RATE =3D=3D PA_HS_MODE_B; =20 /* Reset UFS Host Controller and PHY */ @@ -299,7 +299,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) if (ret) { dev_err(hba->dev, "%s: phy init failed, ret =3D %d\n", __func__, ret); - goto out; + return ret; } =20 /* power on phy - start serdes and phy's power and clocks */ @@ -316,7 +316,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) =20 out_disable_phy: phy_exit(phy); -out: + return ret; } =20 @@ -374,7 +374,6 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *h= ba, static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate, bool update_link_startup_timer) { - int ret =3D 0; struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct ufs_clk_info *clki; u32 core_clk_period_in_ns; @@ -409,11 +408,11 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, * Aggregation logic. */ if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) - goto out; + return 0; =20 if (gear =3D=3D 0) { dev_err(hba->dev, "%s: invalid gear =3D %d\n", __func__, gear); - goto out_error; + return -EINVAL; } =20 list_for_each_entry(clki, &hba->clk_list_head, list) { @@ -436,7 +435,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32= gear, } =20 if (ufs_qcom_cap_qunipro(host)) - goto out; + return 0; =20 core_clk_period_in_ns =3D NSEC_PER_SEC / core_clk_rate; core_clk_period_in_ns <<=3D OFFSET_CLK_NS_REG; @@ -451,7 +450,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32= gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(hs_fr_table_rA)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D hs_fr_table_rA[gear-1][1]; } else if (rate =3D=3D PA_HS_MODE_B) { @@ -460,13 +459,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(hs_fr_table_rB)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D hs_fr_table_rB[gear-1][1]; } else { dev_err(hba->dev, "%s: invalid rate =3D %d\n", __func__, rate); - goto out_error; + return -EINVAL; } break; case SLOWAUTO_MODE: @@ -476,14 +475,14 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u= 32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(pwm_fr_table)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us =3D pwm_fr_table[gear-1][1]; break; case UNCHANGED: default: dev_err(hba->dev, "%s: invalid mode =3D %d\n", __func__, hs); - goto out_error; + return -EINVAL; } =20 if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=3D @@ -507,12 +506,8 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u3= 2 gear, */ mb(); } - goto out; =20 -out_error: - ret =3D -EINVAL; -out: - return ret; + return 0; } =20 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, @@ -527,8 +522,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba = *hba, 0, true)) { dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); - err =3D -EINVAL; - goto out; + return -EINVAL; } =20 if (ufs_qcom_cap_qunipro(host)) @@ -554,7 +548,6 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba = *hba, break; } =20 -out: return err; } =20 @@ -691,8 +684,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, =20 if (!dev_req_params) { pr_err("%s: incoming dev_req_params is NULL\n", __func__); - ret =3D -EINVAL; - goto out; + return -EINVAL; } =20 switch (status) { @@ -720,7 +712,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, if (ret) { pr_err("%s: failed to determine capabilities\n", __func__); - goto out; + return ret; } =20 /* enable the device ref clock before changing to HS mode */ @@ -761,7 +753,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, ret =3D -EINVAL; break; } -out: + return ret; } =20 @@ -773,14 +765,11 @@ static int ufs_qcom_quirk_host_pa_saveconfigtime(stru= ct ufs_hba *hba) err =3D ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), &pa_vs_config_reg1); if (err) - goto out; + return err; =20 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ - err =3D ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), + return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), (pa_vs_config_reg1 | (1 << 12))); - -out: - return err; } =20 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) @@ -957,9 +946,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) =20 host =3D devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); if (!host) { - err =3D -ENOMEM; dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); - goto out; + return -ENOMEM; } =20 /* Make a two way bind between the qcom host and the hba */ @@ -980,10 +968,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->rcdev.owner =3D dev->driver->owner; host->rcdev.nr_resets =3D 1; err =3D devm_reset_controller_register(dev, &host->rcdev); - if (err) { + if (err) dev_warn(dev, "Failed to register reset controller\n"); - err =3D 0; - } =20 if (!has_acpi_companion(dev)) { host->generic_phy =3D devm_phy_get(dev, "ufsphy"); @@ -1049,17 +1035,16 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->dbg_print_en |=3D UFS_QCOM_DEFAULT_DBG_PRINT_EN; ufs_qcom_get_default_testbus_cfg(host); err =3D ufs_qcom_testbus_config(host); - if (err) { + if (err) + /* Failure is non-fatal */ dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); - err =3D 0; - } =20 - goto out; + return 0; =20 out_variant_clear: ufshcd_set_variant(hba, NULL); -out: + return err; } =20 @@ -1085,7 +1070,7 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_di= v(struct ufs_hba *hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), &core_clk_ctrl_reg); if (err) - goto out; + return err; =20 core_clk_ctrl_reg &=3D ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; core_clk_ctrl_reg |=3D clk_cycles; @@ -1093,11 +1078,9 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_d= iv(struct ufs_hba *hba, /* Clear CORE_CLK_DIV_EN */ core_clk_ctrl_reg &=3D ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; =20 - err =3D ufshcd_dme_set(hba, + return ufshcd_dme_set(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), core_clk_ctrl_reg); -out: - return err; } =20 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) @@ -1180,7 +1163,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *= hba, =20 if (err || !dev_req_params) { ufshcd_uic_hibern8_exit(hba); - goto out; + return err; } =20 ufs_qcom_cfg_timers(hba, @@ -1191,8 +1174,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *= hba, ufshcd_uic_hibern8_exit(hba); } =20 -out: - return err; + return 0; } =20 static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80F96C4332F for ; Thu, 22 Dec 2022 14:13:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235650AbiLVONy (ORCPT ); Thu, 22 Dec 2022 09:13:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235541AbiLVONP (ORCPT ); Thu, 22 Dec 2022 09:13:15 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A9312B632 for ; Thu, 22 Dec 2022 06:11:54 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id hd14-20020a17090b458e00b0021909875bccso5707271pjb.1 for ; Thu, 22 Dec 2022 06:11:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xKhZ0e0M8HYKuSmRQjhv72TX3T/LlT9blCNctysBuGQ=; b=nD5egqnYURqthIGOtQB37shl0bPI1H4qqNQn2FwkH4/tQJcvyS0FkDFLD4P9rsE157 04OuUVzrj890GbhpoMxhOAO7rBtss0L25pwB0062QhLxhWZuJrAYIzdNTWHg08QTslSt VlmQ22KCMIFdjETvuBnOz/m+1HE/TxZedKcUB8VM45EdhcRdmzv30GjTtcqnppJhVLFW jr6jEQ4te51NYzN908Cm9KP55tyyK+7udd5+N52kTYF6aKvpeILxL61T4DNFJRvEhTjY oIuCU6TUNeMP/0gIi+pqII+n1PVWPgTN3SgN3nATNUIcF/w8t/xEE2wUNu0sWIOAIu1N cEDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xKhZ0e0M8HYKuSmRQjhv72TX3T/LlT9blCNctysBuGQ=; b=UM5bdz/BbSFLiMEeArItgqYk/VMe7lBqlkXVMqmpjRaFeisVc233Bp3/tNNYpSUs9o lyQ7ensm5YX/4lU6D5rrMj2w4AJ8ndxNEzjFV4Lmb8C+Dws1LTqrMCTesrjBzaVntx6o w2GimEuEwFJDCoBN+a9OSdddD0a203wdyU/ObQv3GurbigAHXvvg2KlZXyw8p43SBWfH DYM/2+lmNS76hs+YM4mDpZWy1XZuhovm74/HMG5P2t3IbdbfK06OOHOLOYK1tXLrxViJ 9umGThOItlMVlveSlNkiXOUYN2fAYs7MQuYr1ZEWZ6UZoqcElwS+pfdQLl3K2J12+R5w emUQ== X-Gm-Message-State: AFqh2kpZ/jqU2a2xZhe+7cLzPMFEU5HksMBlhJsWnWQKu3OA+AbHOadN ZiUkWoq1nRV327HEqPDUR9KH X-Google-Smtp-Source: AMrXdXsFVYG7ivgtchhbVXCprc4JnySWwh9p5ST+pTCanLIJsvhT0b0/4NdZ08dVB+p1cmuKb/NpZQ== X-Received: by 2002:a05:6a21:3988:b0:ad:a09c:5734 with SMTP id ad8-20020a056a21398800b000ada09c5734mr7998451pzc.44.1671718314110; Thu, 22 Dec 2022 06:11:54 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.11.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:11:53 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 14/23] scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON() Date: Thu, 22 Dec 2022 19:39:52 +0530 Message-Id: <20221222141001.54849-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the reset assert and deassert callbacks, the supplied "id" is not used at all and only the hba reset is performed all the time. So there is no reason to use a WARN_ON on the "id". Reviewed-by: Andrew Halaney Reviewed-by: Asutosh Das Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 7cd996ac180b..8bb0f4415f1a 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -895,8 +895,6 @@ ufs_qcom_reset_assert(struct reset_controller_dev *rcde= v, unsigned long id) { struct ufs_qcom_host *host =3D rcdev_to_ufs_host(rcdev); =20 - /* Currently this code only knows about a single reset. */ - WARN_ON(id); ufs_qcom_assert_reset(host->hba); /* provide 1ms delay to let the reset pulse propagate. */ usleep_range(1000, 1100); @@ -908,8 +906,6 @@ ufs_qcom_reset_deassert(struct reset_controller_dev *rc= dev, unsigned long id) { struct ufs_qcom_host *host =3D rcdev_to_ufs_host(rcdev); =20 - /* Currently this code only knows about a single reset. */ - WARN_ON(id); ufs_qcom_deassert_reset(host->hba); =20 /* --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6ADAFC4332F for ; Thu, 22 Dec 2022 14:14:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235475AbiLVOOL (ORCPT ); Thu, 22 Dec 2022 09:14:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235546AbiLVONR (ORCPT ); Thu, 22 Dec 2022 09:13:17 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 399312B633 for ; Thu, 22 Dec 2022 06:12:02 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id gv5-20020a17090b11c500b00223f01c73c3so5536261pjb.0 for ; Thu, 22 Dec 2022 06:12:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MpcXJGSyqRlr7fhEd4gMKWmtvZ0rRDcJZQOouCyYhys=; b=b/Tql6fiOTh5vy5Yb4PGvuY5QhOA1FSNwjLXCBgwpWUQPKRufn0Ll72r/zxUuRsjrx B7vtHaByzg5BLEeksKF3xq06L5Pfa4kYELbcWnfjLxGDBCVgLxqv3GJ924kcE2xzG0V3 G7qEOMYuYBthptLQ/giwibwfo+PKgqw+Pt9UjL1a6ADt02Zq3Sswdnlbs6mn5V4omj2A jhGFPsSAVOCb7VYC0tPTFhNE/+N4Kdo9R/8DSFmUuYQtIVBMdv5lZnJFruZgIuoHrmxS IklVSEa2CLVfJc0+HBp1DTxJ71KzAQxnoghbvBhTEQsN3FkON4s3dxLRc0J922DFtp6h Ck0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MpcXJGSyqRlr7fhEd4gMKWmtvZ0rRDcJZQOouCyYhys=; b=y0TMLsuQeHWtE2BcwKb6v5VfR5H3MyvXl7l84F2cTbalCTRuKvOTN9CONxGpVSWEJz C0DpJltGvITK8mc3oqcEGi4yuC0ZKqShZAcylFf3OmPC/lkQxMklXofGSBfndvAfGhdh JJNiOvD71SqIosawlPxE1gkGHs5UaS6PHsOh9fx+/EQLqkefKsZNwlVfgay3dIJtWrmr MiUQMEbxrL1IZbIYZSpKnVGlNpmkY4WcYzoUpX5AlLDWsDLUT+TBlBELPI4QtIC+tOPK JEQpd55A4gdadiwBk1AWZaYEyEjkg2IS1dxMt0dTSGFcinVcImNz0eIFD29DU2jo9Ish zB0w== X-Gm-Message-State: AFqh2kpZ/mGURvY8ZDNLbRIlSm8aR4Ove7NHIF41VPmbM+oMMFGQLxdu PbZyAN/N03JOgJG81eQZU/S9 X-Google-Smtp-Source: AMrXdXtYaFa5HrouRzcaM3MkDPYWYge7YqZwhmt6PgvcnexDoxXxfI4C0yEZgNoOlYAuBfql1NpjOw== X-Received: by 2002:a05:6a20:4a05:b0:a4:cb40:cf2e with SMTP id fr5-20020a056a204a0500b000a4cb40cf2emr6323560pzb.47.1671718321692; Thu, 22 Dec 2022 06:12:01 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:12:00 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 15/23] scsi: ufs: ufs-qcom: Use bitfields where appropriate Date: Thu, 22 Dec 2022 19:39:53 +0530 Message-Id: <20221222141001.54849-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use bitfield macros where appropriate to simplify the driver. Reviewed-by: Dmitry Baryshkov Reviewed-by: Asutosh Das Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.h | 61 +++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 44466a395bb5..9d96ac71b27f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -17,12 +17,9 @@ #define DEFAULT_CLK_RATE_HZ 1000000 #define BUS_VECTOR_NAME_LEN 32 =20 -#define UFS_HW_VER_MAJOR_SHFT (28) -#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT) -#define UFS_HW_VER_MINOR_SHFT (16) -#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT) -#define UFS_HW_VER_STEP_SHFT (0) -#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT) +#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) +#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) +#define UFS_HW_VER_STEP_MASK GENMASK(15, 0) =20 /* vendor specific pre-defined parameters */ #define SLOW 1 @@ -76,24 +73,28 @@ enum { #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) =20 /* bit definitions for REG_UFS_CFG1 register */ -#define QUNIPRO_SEL 0x1 -#define UTP_DBG_RAMS_EN 0x20000 +#define QUNIPRO_SEL BIT(0) +#define UFS_PHY_SOFT_RESET BIT(1) +#define UTP_DBG_RAMS_EN BIT(17) #define TEST_BUS_EN BIT(18) #define TEST_BUS_SEL GENMASK(22, 19) #define UFS_REG_TEST_BUS_EN BIT(30) =20 +#define UFS_PHY_RESET_ENABLE 1 +#define UFS_PHY_RESET_DISABLE 0 + /* bit definitions for REG_UFS_CFG2 register */ -#define UAWM_HW_CGC_EN (1 << 0) -#define UARM_HW_CGC_EN (1 << 1) -#define TXUC_HW_CGC_EN (1 << 2) -#define RXUC_HW_CGC_EN (1 << 3) -#define DFC_HW_CGC_EN (1 << 4) -#define TRLUT_HW_CGC_EN (1 << 5) -#define TMRLUT_HW_CGC_EN (1 << 6) -#define OCSC_HW_CGC_EN (1 << 7) +#define UAWM_HW_CGC_EN BIT(0) +#define UARM_HW_CGC_EN BIT(1) +#define TXUC_HW_CGC_EN BIT(2) +#define RXUC_HW_CGC_EN BIT(3) +#define DFC_HW_CGC_EN BIT(4) +#define TRLUT_HW_CGC_EN BIT(5) +#define TMRLUT_HW_CGC_EN BIT(6) +#define OCSC_HW_CGC_EN BIT(7) =20 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ -#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide = */ +#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 b= its wide */ =20 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ @@ -101,17 +102,11 @@ enum { TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) =20 /* bit offset */ -enum { - OFFSET_UFS_PHY_SOFT_RESET =3D 1, - OFFSET_CLK_NS_REG =3D 10, -}; +#define OFFSET_CLK_NS_REG 0xa =20 /* bit masks */ -enum { - MASK_UFS_PHY_SOFT_RESET =3D 0x2, - MASK_TX_SYMBOL_CLK_1US_REG =3D 0x3FF, - MASK_CLK_NS_REG =3D 0xFFFC00, -}; +#define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0) +#define MASK_CLK_NS_REG GENMASK(23, 10) =20 /* QCOM UFS debug print bit mask */ #define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0) @@ -135,15 +130,15 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba, { u32 ver =3D ufshcd_readl(hba, REG_UFS_HW_VERSION); =20 - *major =3D (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT; - *minor =3D (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT; - *step =3D (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT; + *major =3D FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); + *minor =3D FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); + *step =3D FIELD_GET(UFS_HW_VER_STEP_MASK, ver); }; =20 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_P= HY_RESET_ENABLE), + REG_UFS_CFG1); =20 /* * Make sure assertion of ufs phy reset is written to @@ -154,8 +149,8 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba= *hba) =20 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_P= HY_RESET_DISABLE), + REG_UFS_CFG1); =20 /* * Make sure de-assertion of ufs phy reset is written to --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3B2EC4332F for ; Thu, 22 Dec 2022 14:14:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235571AbiLVOOY (ORCPT ); Thu, 22 Dec 2022 09:14:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235560AbiLVONZ (ORCPT ); Thu, 22 Dec 2022 09:13:25 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1B192CC8E for ; Thu, 22 Dec 2022 06:12:09 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id o8-20020a17090a9f8800b00223de0364beso5817048pjp.4 for ; Thu, 22 Dec 2022 06:12:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8Umv4TvSxWOIQ+FsO7JFyleWWrH/ciDg2B2wQfJu0u8=; b=lFSSRkVosTBl7NH1CjbznzIGAhg1vr0OY58REMnY5M10cAyYyb2kWljgPPZK+purpL tkoP2lQhnWegg7up4xJ7Glzy1oRsWoz+U4ZzaV2EZylwUbdC59PnTlUSQTVkJ5O99jGM dxwsmXAnqzqkf4CWzclp7h8P0im11vTrb/mwtclro3NVJ2zi6pS2rVWrrXYIzh/dMG4y N8kItD1Dhc0fSBQHdSQ8WUXMgIy2C4HWNoVYUTizsMwgNzJIb1y6buVo1qTzWGJ0FNvq DnKtsXUl341uWX/LhSn8MJZ/hpYKPNR3XRta/FNYJ7+PRgzpJvgucZ1qRmvMqnM9ccts 5o9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8Umv4TvSxWOIQ+FsO7JFyleWWrH/ciDg2B2wQfJu0u8=; b=qn6gwLDIT2n8I188N1F8O9YEBi3KyPfukOZ2w87lx/7nLVk4nOYR+FtRCN0qU5CLmc 85AkvRCSAhZffEh+iOoZwCJOJ4YSpdbqfsJM6TQO9prx4TtBCICTD42iXNDrt1FvyIgG cUsRljCZWFDD1z8qML34unU9eXGE5zFPep6vgmBKoha8wWHaQpbqRiM/onNWiUgHZOjV QkbKUKogpM44ZwNc+jiAnWfoGedswNB4rTD4SaKTT+VEk333/F9ZS+wDl0poEHGx018V oStkJRwCyyJhAIWSQLg6QspzOraZmRKuVPnqbSApvWKabs97vCc+sKaPwJM7pjbrwXki Wl0g== X-Gm-Message-State: AFqh2kp6X1x5PG09+EkM/8UIqqNuo97C4NqRBreuZ099iNq/+lrqWQm1 y0lnX7YgbA00dwN4wYr6shjI X-Google-Smtp-Source: AMrXdXsfA22qTY7Dpuhd3BPItBnKL5MRnihwLcXslA73ddu+1EMjMQTU80L5uyMZTcdu/fyDqeutaQ== X-Received: by 2002:a17:90b:300f:b0:219:823f:7216 with SMTP id hg15-20020a17090b300f00b00219823f7216mr20532049pjb.31.1671718329192; Thu, 22 Dec 2022 06:12:09 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.12.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:12:08 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 16/23] scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error Date: Thu, 22 Dec 2022 19:39:54 +0530 Message-Id: <20221222141001.54849-17-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make use of dev_err_probe() for printing the probe error. Reviewed-by: Andrew Halaney Reviewed-by: Asutosh Das Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8bb0f4415f1a..38e2ed749d75 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1441,9 +1441,9 @@ static int ufs_qcom_probe(struct platform_device *pde= v) /* Perform generic probe */ err =3D ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); if (err) - dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); + return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); =20 - return err; + return 0; } =20 /** --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA364C4332F for ; Thu, 22 Dec 2022 14:14:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235603AbiLVOOh (ORCPT ); Thu, 22 Dec 2022 09:14:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235440AbiLVONn (ORCPT ); Thu, 22 Dec 2022 09:13:43 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 496C32CC9E for ; Thu, 22 Dec 2022 06:12:17 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id 17so2177274pll.0 for ; Thu, 22 Dec 2022 06:12:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6aSBJzo6HdQMf+Z0Vqc/apVYRTuOVSte3r0EnoXQi/4=; b=jTCrpY3DW1MbJPMO0SQIBXcCCkvCD0S+ACDX70kkaK0H0kZEZ6HnREw9vOQda3RT4H H7PGPlkzCC4/6qAAbsMsgFFDFG6kY/W6s2IPlUEflT3ISw3sEXSyLxVP8i8eZw+9M8kS LqI6NLrFaSBezR3F+5/YjXeeelNypntSJwT8yTS59VeDIjqMChORmW+lXY0RwB2pWjy6 6wsmeVWrUlnrCRWVuNO/Qg4L2S8YdEugHJuS5B3YLxDEuF/8KYU6sqznBCUvrcm7KXrF D2xOw4cZO/jEUJiId5VSYHg1tx67U3hLRzF/jq7m7GCEB4D58fEmzKPC9XcLrPqepMzp PKnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6aSBJzo6HdQMf+Z0Vqc/apVYRTuOVSte3r0EnoXQi/4=; b=HKbxraXXVajOxgao3Oe27tbdkJTwKaNcxBAHht/rtF3NK2gKBzUfZzG5hb1wrgnf3/ 1OIdkvDPuor1Ij0Rf8AtBmwl79hJOKwZtXRooYylH+Nt7UM8ocDYhbFV65bYWBwmhRyH qWFomKu2iXbD6jjlleoNpcHDaotQmKsLmtPme/7GdRxqE2Z6KrRho4IDOTrPoM8rMGRY QBsyrXS0O5pvg4ExsvHPugZAXF+fq6lg4we0uUJotnrGr4unKptrmlvoWXrCi5CIODJz pIFkjRrNfKhZyA43T8R6g1+Rvk3ctXNxRK4DeH3Q9bm+e5d2PZMr/g9r1SKrL4FqBn8m 5kGw== X-Gm-Message-State: AFqh2kr5RuQ2WgFKCxTuGDu8bTxiILsIwO/556U165p9SY1tcbc0fN+B G8ycc9Wcbxhb04NLFhnZjJAC X-Google-Smtp-Source: AMrXdXu0QaYyVMCq5rDRmy7qgCFCoYfXWUnAV4G8ELfQikPhojZ5rjvwLv+swmBQzX4x2gPFyXNH6A== X-Received: by 2002:a05:6a20:1455:b0:ad:58d4:2a71 with SMTP id a21-20020a056a20145500b000ad58d42a71mr9202668pzi.4.1671718336761; Thu, 22 Dec 2022 06:12:16 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:12:15 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 17/23] scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0 Date: Thu, 22 Dec 2022 19:39:55 +0530 Message-Id: <20221222141001.54849-18-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On newer UFS revisions, the register at offset 0xD0 is called, REG_UFS_PARAM0. Since the existing register, RETRY_TIMER_REG is not used anywhere, it is safe to use the new name. Reviewed-by: Andrew Halaney Reviewed-by: Asutosh Das Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 9d96ac71b27f..7fe928b82753 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -33,7 +33,8 @@ enum { REG_UFS_TX_SYMBOL_CLK_NS_US =3D 0xC4, REG_UFS_LOCAL_PORT_ID_REG =3D 0xC8, REG_UFS_PA_ERR_CODE =3D 0xCC, - REG_UFS_RETRY_TIMER_REG =3D 0xD0, + /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ + REG_UFS_PARAM0 =3D 0xD0, REG_UFS_PA_LINK_STARTUP_TIMER =3D 0xD8, REG_UFS_CFG1 =3D 0xDC, REG_UFS_CFG2 =3D 0xE0, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44214C4332F for ; Thu, 22 Dec 2022 14:14:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235611AbiLVOOt (ORCPT ); Thu, 22 Dec 2022 09:14:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235504AbiLVONs (ORCPT ); Thu, 22 Dec 2022 09:13:48 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB1402CCBF for ; Thu, 22 Dec 2022 06:12:24 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id m4so2133831pls.4 for ; Thu, 22 Dec 2022 06:12:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mPijPobTcYQaRyLBeRVB3HBZnVNDSDqtRoK4CmiEviM=; b=BA0eDOPbqVVIhhnoX9eUYS0pHxcdGVSvOSEqKJssJmQgmB/zpfNs2ywpseefd9emYh XoqN4fMEHfG2pCF4KZiD2D5/qOOhJbSP8VUw1VfdAzx0eEsQJRZfPNZ1giqckcw6l/0F RY9jGf365mZQMeq8fABGTxuju4LBtSxJVrQVhQSYMynUL2F04SC6OwQb54WMmEL+4MHi nj4OlLmn3jy8CMwICcCtp6czimJzm9ypl8bMFg5PkRnYD7CXnKG/mQwKZnsgSz2ndx0y UIxtddqWDUwypdkhoLzg5pp8bnnjBvmdaWC8ZQ+LmnfdZ565cBWkogTOH/3UPtLm+trg koiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mPijPobTcYQaRyLBeRVB3HBZnVNDSDqtRoK4CmiEviM=; b=X3VZxXI50JUEAKpF0BQP9ScSAcvMFvyv6uMT3jQYx36tv8bQcaLLN7JHPDfZZG/oZV BSi36l1QAoyOIiMil9I3jMiN7q76/yB/mWuTOXfzXuOzxltxDdqyEZeRGmco37DyMNu5 4h5jrN4CL6cwC3V0Zzk22vN1YaHGHztd4941eVNgOhuvMCDGzke45ZIEZwJ6lpvY4xFN 4rX+J1NyAl86ewuCR1OypGMpDam5SqJx2j/V6eWWuwXVjnF3hQRrvK8t3xVLK26ZFkHe FvvLVULajDDbKck/75gFJaAG9FFkKZx12sA7R6wHGtTEIeQKr2OgaPQKNDSXq0XDUNjn 9Mcg== X-Gm-Message-State: AFqh2kqUyWjMl5B2UuSXBuW1ntubaS9WoQdhXdGy7JKXM6JGdZ1c/atH ZXkP028GYH1zDccLrPNZXlls X-Google-Smtp-Source: AMrXdXvWMjrApzmz5yi1BXdIqlRS22IM1TaOp7Xa1o1bPm+EfdAnwO2fH9/w5YnfyLy+cSU+N9cqsQ== X-Received: by 2002:a17:903:28d:b0:191:386:d8f with SMTP id j13-20020a170903028d00b0019103860d8fmr6265636plr.47.1671718344357; Thu, 22 Dec 2022 06:12:24 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:12:23 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 18/23] scsi: ufs: core: Add reinit_notify() callback Date: Thu, 22 Dec 2022 19:39:56 +0530 Message-Id: <20221222141001.54849-19-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" reinit_notify() callback can be used by the UFS controller drivers to perform changes required for UFSHCD reinit that can happen during max gear switch. Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam Reviewed-by: Bart Van Assche --- drivers/ufs/core/ufshcd-priv.h | 6 ++++++ include/ufs/ufshcd.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index a9e8e1f5afe7..2ce3c98e0711 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -226,6 +226,12 @@ static inline void ufshcd_vops_config_scaling_param(st= ruct ufs_hba *hba, hba->vops->config_scaling_param(hba, p, data); } =20 +static inline void ufshcd_vops_reinit_notify(struct ufs_hba *hba) +{ + if (hba->vops && hba->vops->reinit_notify) + hba->vops->reinit_notify(hba); +} + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; =20 /** diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 5cf81dff60aa..0a0b435f5c17 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -297,6 +297,7 @@ struct ufs_pwr_mode_info { * @config_scaling_param: called to configure clock scaling parameters * @program_key: program or evict an inline encryption key * @event_notify: called to notify important events + * @reinit_notify: called to notify reinit of UFSHCD during max gear switch */ struct ufs_hba_variant_ops { const char *name; @@ -335,6 +336,7 @@ struct ufs_hba_variant_ops { const union ufs_crypto_cfg_entry *cfg, int slot); void (*event_notify)(struct ufs_hba *hba, enum ufs_event_type evt, void *data); + void (*reinit_notify)(struct ufs_hba *); }; =20 /* clock gating state */ --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77E31C4167B for ; Thu, 22 Dec 2022 14:15:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235716AbiLVOO7 (ORCPT ); Thu, 22 Dec 2022 09:14:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235552AbiLVOOS (ORCPT ); Thu, 22 Dec 2022 09:14:18 -0500 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81DE130F5A for ; Thu, 22 Dec 2022 06:12:32 -0800 (PST) Received: by mail-pj1-x102a.google.com with SMTP id x3so2011906pjv.4 for ; Thu, 22 Dec 2022 06:12:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UnBUp5WyCz4krAwRvhsnV8wS00kgXpu7vT2PwLsChp8=; b=YdGqbwN+gQqfHCFSWQmyIsywlKkBpIYcrXg3HvTHS9G+mtStS43WruoltROS/uEKmo 5O0zfwcO568bsfeWlPwgJFW0h5+Mevpep4gv/Z4Kd/4G9UwqYB6lGPf9ennfbbO/autt PEFZKjtsvw0sxM5kGviTs1A+k5IR27ckqFWJFoUvTVjANNuoacVT/cHWjAImL+I3Jwxk Gi43pb99ZJveG9SKVWrUxZ3GttulbqQJz2lhDE0sxWzxsV3mXop09VXI3g2Irs0LhP+Z hywLxlVT/J+vhftxL+uOTDwUl/1ORzp+G6AFRdghV/4n8ZOwmFmKY/j8Wi5PAOmrKWi3 GToQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UnBUp5WyCz4krAwRvhsnV8wS00kgXpu7vT2PwLsChp8=; b=Ne1kqfc5CRrbtfCfr/KtSRhrKMsRC4myA+E5Harm4YedUCaT2wyNa0G8XAVTYBvC6r /cFuwqvbuGDASf5wgQ0/0oclMnZy9wDND8B2oRSSHVcyXsmlE/sl8CcOB7GvlKy5u2PN eyd0oQxnArzwkhGLb8xPaGiTM3tHlidpRN8qw7/ni6wmKIavsHmgvRw6bKpHyYgFNRgI tzLL9MHWFzibUcHSdMjov7RV2kTx5ueLtv4BiW4M9VpivHnD/+tTtXx9m4sFlRXX3EHp vPOxBFTfv9/TSFNgGYLmi9vG57McXSOv1RbbIDIcFHrGai79TmJNzzI3YBFptQoPaYkj afKw== X-Gm-Message-State: AFqh2kr15VRhzzuWxpwY9mC6gN/KxwCRqe9TjOcI7oFK5cEmIMrgu2yy 7j6MtB/o+/gW15tIEX8YMbRyay5kZ+BuILs= X-Google-Smtp-Source: AMrXdXvxNWJ3I9wCdsRq+WWRItGU4LaRqqcv3b3NKRJwUI3B0oHtW7J9RE43Xlo2gfcOsBjbHh4h5Q== X-Received: by 2002:a05:6a20:a884:b0:af:9fa8:ce05 with SMTP id ca4-20020a056a20a88400b000af9fa8ce05mr6825267pzb.2.1671718351929; Thu, 22 Dec 2022 06:12:31 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.12.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:12:31 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 19/23] scsi: ufs: core: Add support for reinitializing the UFS device Date: Thu, 22 Dec 2022 19:39:57 +0530 Message-Id: <20221222141001.54849-20-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some platforms like Qcom, requires the UFS device to be reinitialized after switching to maximum gear speed. So add support for that in UFS core by introducing a new quirk (UFSHCD_CAP_REINIT_AFTER_MAX_GEAR_SWITCH) and doing the reinitialization, if the quirk is enabled by the controller driver. Suggested-by: Can Guo Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam Reviewed-by: Bart Van Assche --- drivers/ufs/core/ufshcd.c | 63 +++++++++++++++++++++++++++++---------- include/ufs/ufshcd.h | 6 ++++ 2 files changed, 53 insertions(+), 16 deletions(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index bda61be5f035..fe4720bf0d67 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8161,27 +8161,18 @@ static int ufshcd_add_lus(struct ufs_hba *hba) return ret; } =20 -/** - * ufshcd_probe_hba - probe hba to detect device and initialize it - * @hba: per-adapter instance - * @init_dev_params: whether or not to call ufshcd_device_params_init(). - * - * Execute link-startup and verify device initialization - */ -static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) +static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) { int ret; - unsigned long flags; - ktime_t start =3D ktime_get(); =20 hba->ufshcd_state =3D UFSHCD_STATE_RESET; =20 ret =3D ufshcd_link_startup(hba); if (ret) - goto out; + return ret; =20 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) - goto out; + return ret; =20 /* Debug counters initialization */ ufshcd_clear_dbg_ufs_stats(hba); @@ -8192,12 +8183,12 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bo= ol init_dev_params) /* Verify device initialization by sending NOP OUT UPIU */ ret =3D ufshcd_verify_dev_init(hba); if (ret) - goto out; + return ret; =20 /* Initiate UFS initialization, and waiting until completion */ ret =3D ufshcd_complete_dev_init(hba); if (ret) - goto out; + return ret; =20 /* * Initialize UFS device parameters used by driver, these @@ -8206,7 +8197,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool= init_dev_params) if (init_dev_params) { ret =3D ufshcd_device_params_init(hba); if (ret) - goto out; + return ret; } =20 ufshcd_tune_unipro_params(hba); @@ -8227,11 +8218,51 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bo= ol init_dev_params) if (ret) { dev_err(hba->dev, "%s: Failed setting power mode, err =3D %d\n", __func__, ret); + return ret; + } + } + + return 0; +} + +/** + * ufshcd_probe_hba - probe hba to detect device and initialize it + * @hba: per-adapter instance + * @init_dev_params: whether or not to call ufshcd_device_params_init(). + * + * Execute link-startup and verify device initialization + */ +static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) +{ + ktime_t start =3D ktime_get(); + unsigned long flags; + int ret; + + ret =3D ufshcd_device_init(hba, init_dev_params); + if (ret) + goto out; + + if (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) { + /* Reset the device and controller before doing reinit */ + ufshcd_device_reset(hba); + ufshcd_hba_stop(hba); + ufshcd_vops_reinit_notify(hba); + ret =3D ufshcd_hba_enable(hba); + if (ret) { + dev_err(hba->dev, "Host controller enable failed\n"); + ufshcd_print_evt_hist(hba); + ufshcd_print_host_state(hba); goto out; } - ufshcd_print_pwr_info(hba); + + /* Reinit the device */ + ret =3D ufshcd_device_init(hba, init_dev_params); + if (ret) + goto out; } =20 + ufshcd_print_pwr_info(hba); + /* * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) * and for removable UFS card as well, hence always set the parameter. diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 0a0b435f5c17..68bd822b9c22 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -595,6 +595,12 @@ enum ufshcd_quirks { * auto-hibernate capability but it's FASTAUTO only. */ UFSHCD_QUIRK_HIBERN_FASTAUTO =3D 1 << 18, + + /* + * This quirk needs to be enabled if the host controller needs + * to reinit the device after switching to maximum gear. + */ + UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH =3D 1 << 19, }; =20 enum ufshcd_caps { --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0404AC4332F for ; Thu, 22 Dec 2022 14:15:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235494AbiLVOPi (ORCPT ); Thu, 22 Dec 2022 09:15:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235492AbiLVOOf (ORCPT ); Thu, 22 Dec 2022 09:14:35 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 134C531350 for ; Thu, 22 Dec 2022 06:12:40 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id b2so2118608pld.7 for ; Thu, 22 Dec 2022 06:12:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SPN6MvsLleyjqtpg7glkpxk2Wcr9bYRBKaDcXVrkxao=; b=vSlLDPBkg+X0ZBxJOz0DTSh8gbGqwFDw8UyYr/ADDQaA8R0hwaZRRaMpkOy6O4o0sp JGqUgdcaT1m6ws2nPfO2XNoFBQ14GrEDWqdYaVwKauZGyoTePtC/skYEx0T71dwuCFi2 Hnr3gUVFPrG8fdACGv8bvmF3Oap3mjD8CIvt/XZM7TWFXQnszK3IDSrDHj6NIZ7XZDJh +rNo8mmnfwme1AQ+x7iJanAPi2bj/RikfdCgKVauk+geNc3jTLWTfH0Znkhi/yoGkg2K sHahEJ0OTclZuxC6X6J46uAV8ATkrebW6Qw2QQnUFLCWkP+gG8NF4vEtRYtVWNs1UKpK 4DQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SPN6MvsLleyjqtpg7glkpxk2Wcr9bYRBKaDcXVrkxao=; b=vBVlkMb8iXPtb5Cj3qiS3MUap45/Knp1fcw1IgroFfYn6hAPWLqkluj8EJAMfBgtEH 1wme8M4Ff7r2LMWxjvGmfP+2Bx9a5d/aO2wZk02bn7oRytfhNj/bUK8+RUkFtke2c9Uh LEQkDWH110xprni0ct5Xf0+1mEPx9dYcOqmqHRCk7UQh1njNq3mk5ljzRz9uv7eOJhod 0AhuZcq8geJZ7ivbnzPNEpKyvZiZpkLbyZlGf5TFXagV/AYMzLqL4tGZgKfjeejg35AW SHpb4V7PhH9JLOKOSzGtxd12LyygIHLhbnAW7xwht2+cmZQnQkeUwJTVxnICFUx3l/YW o2LA== X-Gm-Message-State: AFqh2kpaWuUKA1CkKkyr/5V/ogvoSXR5u20EpgwZQL/f/GayQNIPL5l5 lozw9HH4vwkWJY3CuT3Tyocy X-Google-Smtp-Source: AMrXdXu/KaxPoteqxf49QCt4/X1HqUCw83tcdIDod5MMlfpjrw38HLDXkcil1XByhafZ+tCJCx8c6Q== X-Received: by 2002:a05:6a20:d695:b0:a2:c1f4:3c70 with SMTP id it21-20020a056a20d69500b000a2c1f43c70mr7254391pzb.8.1671718359483; Thu, 22 Dec 2022 06:12:39 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.12.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:12:38 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 20/23] scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear Date: Thu, 22 Dec 2022 19:39:58 +0530 Message-Id: <20221222141001.54849-21-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the preparation of adding support for new gears, let's move the logic that finds the gear for each platform to a new function. This helps with code readability and also allows the logic to be used in other places of the driver in future. While at it, let's make it clear that this driver only supports symmetric gear setting (hs_tx_gear =3D=3D hs_rx_gear). Reviewed-by: Andrew Halaney Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 38e2ed749d75..919b6eae439d 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -278,6 +278,25 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) return 0; } =20 +static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + + if (host->hw_ver.major =3D=3D 0x1) { + /* + * HS-G3 operations may not reliably work on legacy QCOM + * UFS host controller hardware even though capability + * exchange during link startup phase may end up + * negotiating maximum supported gear as G3. + * Hence downgrade the maximum supported gear to HS-G2. + */ + return UFS_HS_G2; + } + + /* Default is HS-G3 */ + return UFS_HS_G3; +} + static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); @@ -692,19 +711,8 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *= hba, ufshcd_init_pwr_dev_param(&ufs_qcom_cap); ufs_qcom_cap.hs_rate =3D UFS_QCOM_LIMIT_HS_RATE; =20 - if (host->hw_ver.major =3D=3D 0x1) { - /* - * HS-G3 operations may not reliably work on legacy QCOM - * UFS host controller hardware even though capability - * exchange during link startup phase may end up - * negotiating maximum supported gear as G3. - * Hence downgrade the maximum supported gear to HS-G2. - */ - if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2) - ufs_qcom_cap.hs_tx_gear =3D UFS_HS_G2; - if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2) - ufs_qcom_cap.hs_rx_gear =3D UFS_HS_G2; - } + /* This driver only supports symmetic gear setting i.e., hs_tx_gear =3D= =3D hs_rx_gear */ + ufs_qcom_cap.hs_tx_gear =3D ufs_qcom_cap.hs_rx_gear =3D ufs_qcom_get_hs_= gear(hba); =20 ret =3D ufshcd_get_pwr_dev_param(&ufs_qcom_cap, dev_max_params, --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 177BDC4332F for ; Thu, 22 Dec 2022 14:15:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229862AbiLVOPz (ORCPT ); Thu, 22 Dec 2022 09:15:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235690AbiLVOOt (ORCPT ); Thu, 22 Dec 2022 09:14:49 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C90B323E87 for ; Thu, 22 Dec 2022 06:12:47 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id m4so2134789pls.4 for ; Thu, 22 Dec 2022 06:12:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aBn3zEFmIV6MhSJTCqVfJoKippEJn3UVUNP6V0+D++w=; b=wUEp+NmpgcRSpWDAl5gCZLjGhtZOUkb6nH0n9cqBjo1QjAmnGSD7tz6SDlueRbPqU7 Pg58jvzpbEa5o9H4QDHwvb+xubArD7c4VsVqyoewLiLlPIu9zYu8umlPz6bY+qbSBIKB GDEDwBvoMAWXMY87a8AS3OemBzeDMf+zwDx1Ez9qW5ya4vxTB4+8ImILjJyoOxImdKaX BjK//SJQUjz4knoV54gc8pC3pwQlKYSVM6w0uFkWeHnXlNNpRiMIK/JH68QdlKIiUcfp Z1YOqDt8BL4jrYcv6CQNRYAs+VPHtZS4ff9BvD50/froZGoTp+7WhIjv5+U38QLMGbqn 1AkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aBn3zEFmIV6MhSJTCqVfJoKippEJn3UVUNP6V0+D++w=; b=cfJIPNIy3aMqs/uDx33uYVWfAZI0NaUxZDUjpp3z1NDjILmdMqcU5zZ5BydGL58+gG GHmSuH3QiDoWU5VGWXMusr+ZaI2E0YKPiSqfumCmktuya8OkeTJtMkvzxVmmOUSTGyrX phckIjTH8iHEPWf3i5GCOGPYn5gtSRcCEkxWkRi0wsy3LyJqVS8eqhHrJZjqFeAI+Zq0 tAxyRS4xyxyuLh3SoYB2OPQcIzB9fD4OYwxKBmaNArwK0qXmxuMJ5UP+rrg9wy/d/F00 kceWpg/pu/pRjHjXpkrXa91TRC9raC1v/TDchCxPYOIdhTdjtDgKjPp72w5nW0pkZP1H 5CQA== X-Gm-Message-State: AFqh2krosK5ZCQKJ8z2bAFDpB4uFY1DxRfIjC8zyFP5cQ40+0YRwtjjD P1EvZn7moYanf5kW5Osa2DlC X-Google-Smtp-Source: AMrXdXtmutM2RQ/lU4e/I/kqUw5HOoB1HQclleoi8/H3D+yG44Gbrwy7yofMNVMYL9R5pI1N2pY2Nw== X-Received: by 2002:a05:6a20:c112:b0:ad:e904:f247 with SMTP id bh18-20020a056a20c11200b000ade904f247mr6784083pzb.29.1671718367062; Thu, 22 Dec 2022 06:12:47 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:12:46 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 21/23] scsi: ufs: ufs-qcom: Add support for reinitializing the UFS device Date: Thu, 22 Dec 2022 19:39:59 +0530 Message-Id: <20221222141001.54849-22-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Starting from Qualcomm UFS version 4, the UFS device needs to be reinitialized after switching to maximum gear by the UFS core. Hence, add support for it by enabling the UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH quirk, implementing reinit_notify() callback and using the agreed gear speed for setting the PHY mode. Suggested-by: Can Guo Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 26 ++++++++++++++++++++++---- drivers/ufs/host/ufs-qcom.h | 2 ++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 919b6eae439d..3efef2f36e69 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -302,7 +302,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); struct phy *phy =3D host->generic_phy; int ret; - bool is_rate_B =3D UFS_QCOM_LIMIT_HS_RATE =3D=3D PA_HS_MODE_B; =20 /* Reset UFS Host Controller and PHY */ ret =3D ufs_qcom_host_reset(hba); @@ -310,9 +309,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) dev_warn(hba->dev, "%s: host reset returned %d\n", __func__, ret); =20 - if (is_rate_B) - phy_set_mode(phy, PHY_MODE_UFS_HS_B); - /* phy initialization - calibrate the phy */ ret =3D phy_init(phy); if (ret) { @@ -321,6 +317,8 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) return ret; } =20 + phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear); + /* power on phy - start serdes and phy's power and clocks */ ret =3D phy_power_on(phy); if (ret) { @@ -723,6 +721,9 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *h= ba, return ret; } =20 + /* Use the agreed gear */ + host->hs_gear =3D dev_req_params->gear_tx; + /* enable the device ref clock before changing to HS mode */ if (!ufshcd_is_hs_mode(&hba->pwr_info) && ufshcd_is_hs_mode(dev_req_params)) @@ -836,6 +837,9 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *h= ba) | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); } + + if (host->hw_ver.major > 0x3) + hba->quirks |=3D UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; } =20 static void ufs_qcom_set_caps(struct ufs_hba *hba) @@ -1044,6 +1048,12 @@ static int ufs_qcom_init(struct ufs_hba *hba) dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); =20 + /* + * Power up the PHY using the minimum supported gear (UFS_HS_G2). + * Switching to max gear will be performed during reinit if supported. + */ + host->hs_gear =3D UFS_HS_G2; + return 0; =20 out_variant_clear: @@ -1410,6 +1420,13 @@ static void ufs_qcom_config_scaling_param(struct ufs= _hba *hba, } #endif =20 +static void ufs_qcom_reinit_notify(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + + phy_power_off(host->generic_phy); +} + /* * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations * @@ -1433,6 +1450,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_= vops =3D { .device_reset =3D ufs_qcom_device_reset, .config_scaling_param =3D ufs_qcom_config_scaling_param, .program_key =3D ufs_qcom_ice_program_key, + .reinit_notify =3D ufs_qcom_reinit_notify, }; =20 /** diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 7fe928b82753..4b00c67e9d7f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -217,6 +217,8 @@ struct ufs_qcom_host { struct reset_controller_dev rcdev; =20 struct gpio_desc *device_reset; + + u32 hs_gear; }; =20 static inline u32 --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50DEEC4332F for ; Thu, 22 Dec 2022 14:16:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235723AbiLVOQK (ORCPT ); Thu, 22 Dec 2022 09:16:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235702AbiLVOO6 (ORCPT ); Thu, 22 Dec 2022 09:14:58 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00015558B for ; Thu, 22 Dec 2022 06:12:54 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id v23so2015013pju.3 for ; Thu, 22 Dec 2022 06:12:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8r6KWtBC24mvcKhKbi7oMsl/OBPp4xpGlki0s+jabEY=; b=P4YYRDE7eLMbshCu/AHFfq4yO9XLNrx8vkP9s9ulv6mT6xjsgejmF7rZxI3q6MWsSr UcJ/yJdcKMahNPOMOwprplmiNGv11pKw3UvQEFcQzE30vtdW0VhOzTrWNV/1uvEvvluk OKfjfmw9AXCkybIh1bWJ/Q1J7cd6cPuLRqolxmcXGTN08h/p+BEieKI61QV1pHZ9ZKkR BgbFvnOWEgC8craFOZ56y8EqPp3zuw3fmmdf0tkDj+35Ic9zylbaBTXttoxUCBZw8lM7 bSMJXQuRCBYHyGvemSAbZYbbI/xLN0tzsFHPyKRd1xShBmwCEfCM526PNiNxrlL5msmL ukbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8r6KWtBC24mvcKhKbi7oMsl/OBPp4xpGlki0s+jabEY=; b=kb3K88Eq7xSGWpnyySB2p7lKNknvuUxifl8l4WdtUqIOspiqydQmoPjBeQAI2CJOuS jXNVKPTZiJXdyffPoGViQLLVeDwz+N0kobidxriYoHiEj3sLBjkvmX+AHyFeH/OfQ9hG tf/XW+/FwMym7hjqR85tIT8LPZz+ME02G8xmdsU60wtgxF9Z7m/V2wTz54f5ZjQNj/bf 2WGXDGhJZDxVSeRxGxKLW6Gkpsk6X19f8PZnuTWotbYm7pGX3hM6mvmbImA3gVM0wPMJ 9vy+LcXEjVGQghId8MKYHDsYFtyuAdjC+CIGYaQ7AceMfcmIwLeycirGQvg5UrZYdC80 clIw== X-Gm-Message-State: AFqh2kqCcR5sEJ0iSjbfyVDQ9dzFBwFD3DOYJV3Rygh3mFfug6+JBqox MN6Yyd1ZnpN5/fgbcgDPWPVE X-Google-Smtp-Source: AMrXdXt39otDg2GPiuR+A8WWlXVq1iDlfUJ6rH6SVRvyktfugDgqkZ6oq6hotpPIIqAIrKuhLnlHxQ== X-Received: by 2002:a05:6a20:3ca5:b0:af:ae01:54df with SMTP id b37-20020a056a203ca500b000afae0154dfmr9321720pzj.11.1671718374656; Thu, 22 Dec 2022 06:12:54 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:12:53 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 22/23] scsi: ufs: ufs-qcom: Add support for finding max gear on new platforms Date: Thu, 22 Dec 2022 19:40:00 +0530 Message-Id: <20221222141001.54849-23-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Starting from Qcom UFS version 4.0, vendor specific REG_UFS_PARAM0 register can be used to determine the maximum gear supported by the controller. Suggested-by: Can Guo Reviewed-by: Andrew Halaney Tested-by: Andrew Halaney # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 2 ++ drivers/ufs/host/ufs-qcom.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 3efef2f36e69..607fddb7b4c3 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -291,6 +291,8 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) * Hence downgrade the maximum supported gear to HS-G2. */ return UFS_HS_G2; + } else if (host->hw_ver.major >=3D 0x4) { + return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); } =20 /* Default is HS-G3 */ diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 4b00c67e9d7f..dd3abd23ec22 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -94,6 +94,10 @@ enum { #define TMRLUT_HW_CGC_EN BIT(6) #define OCSC_HW_CGC_EN BIT(7) =20 +/* bit definitions for REG_UFS_PARAM0 */ +#define MAX_HS_GEAR_MASK GENMASK(6, 4) +#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) + /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 b= its wide */ =20 --=20 2.25.1 From nobody Wed Sep 17 06:42:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04371C001B2 for ; Thu, 22 Dec 2022 14:16:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235735AbiLVOQP (ORCPT ); Thu, 22 Dec 2022 09:16:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230326AbiLVOPa (ORCPT ); Thu, 22 Dec 2022 09:15:30 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A66F52EF90 for ; Thu, 22 Dec 2022 06:13:02 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id n4so2147298plp.1 for ; Thu, 22 Dec 2022 06:13:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+9vMWr+QReiCFTMChXS+VaiIVai5hcXHpa8PnZ2xGs0=; b=CdISaZLIaDAiejs3ebXWfckHizcdGNVuYMECOILk4yH8xwZVwxG4rqfNknKiQ9bMxv K6t7qbFpxglLraOezwuKyzjqE8CILTiYQ8fqC9spqWBaWJemqGlFl9HcxUr/IKp4GiVs lmvYjvo5Xsua2Dr3Hikt0B9Qgo+BR+9rdhHGiGch3nEldEUjjhkJEPBqpNEJNmNBWlR7 afSp0RPecbEl4ZEjX8yxe7ItSy8y0659l6Vht++AZTi1zjiu/7I/OJvwdg/hfknwmO05 fKeR62Njz+K0Ku39QJtMu4hAR3KOVexrkaHShOcxUgXcwsBT/pNtnOm1BuGm8aBWvH1H 26Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+9vMWr+QReiCFTMChXS+VaiIVai5hcXHpa8PnZ2xGs0=; b=sdllJi0937JMmkmsdJZdTZoy4T40iciyXPicesAPxR7IIKa9KIeRW6KFX0x/uQ/i2p KJZJeUkiCPX740ZnDz8xid8N1HXD2kGu0SCOvSoC51QOovavIcKMMQWQ/0NTgTBY3noQ XX4yZbmbfHoCIjtVVz33UKv8/oVRg6dah77Z27aBbrasfctFdRgTL2IobUK2q302qqm/ J2VG3spnlDLe4n82jCia2odsTMwE347+iBy4TWaai4UVBTZfLEH1JSo7YW4Wd2RVo+sS XJ6t3FP0oZbBitIIs7qTk5hOJIUyzN2GBT3rYWgPBCJD3jtVb3HCBCsT+2e6CJM23CqF FlUQ== X-Gm-Message-State: AFqh2kp7vfwFr3g+1eLvfR9q8Cfis2cgrLQlF5bpbQuajoP4S0XfXCwe ahE5zDTBIgMols5laveS+C6YyxtXEva77C8= X-Google-Smtp-Source: AMrXdXsteySjBHCQNu+U2EA0Z9ki5BDJhCG3tehQDYHTLHrsEX/9rNG3ICW7RmKBQP2Yjf+3ELN7ag== X-Received: by 2002:a17:90b:3712:b0:223:ceed:ef6f with SMTP id mg18-20020a17090b371200b00223ceedef6fmr6803083pjb.10.1671718382131; Thu, 22 Dec 2022 06:13:02 -0800 (PST) Received: from localhost.localdomain ([117.217.177.177]) by smtp.gmail.com with ESMTPSA id f8-20020a655908000000b0047829d1b8eesm832031pgu.31.2022.12.22.06.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 06:13:01 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, Manivannan Sadhasivam Subject: [PATCH v5 23/23] MAINTAINERS: Add myself as the maintainer for Qcom UFS drivers Date: Thu, 22 Dec 2022 19:40:01 +0530 Message-Id: <20221222141001.54849-24-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> References: <20221222141001.54849-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qcom UFS drivers are left un-maintained till now. I'd like to step up to maintain the drivers and the binding. Acked-by: Bjorn Andersson Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7729a30b9609..7638c749a63f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21411,6 +21411,14 @@ L: linux-mediatek@lists.infradead.org (moderated f= or non-subscribers) S: Maintained F: drivers/ufs/host/ufs-mediatek* =20 +UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER QUALCOMM HOOKS +M: Manivannan Sadhasivam +L: linux-arm-msm@vger.kernel.org +L: linux-scsi@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +F: drivers/ufs/host/ufs-qcom* + UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER RENESAS HOOKS M: Yoshihiro Shimoda L: linux-renesas-soc@vger.kernel.org --=20 2.25.1