From nobody Wed Sep 17 10:38:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37EF8C4167B for ; Wed, 21 Dec 2022 20:41:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234917AbiLUUld (ORCPT ); Wed, 21 Dec 2022 15:41:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234606AbiLUUlI (ORCPT ); Wed, 21 Dec 2022 15:41:08 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB34C1D667 for ; Wed, 21 Dec 2022 12:40:50 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id z8-20020a17090abd8800b00219ed30ce47so3594679pjr.3 for ; Wed, 21 Dec 2022 12:40:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DlWUJTvQq+dZLt1EiuVf3fldzhye5smOXD/qjtYfqYw=; b=cnS90yFkMSYqf1fJvDCslqRqWI9XecMY7K+W7HEgUppJd56KXhNrYd/fTP7vHdA8wq v/gTFBNb5//ZkaCm1yJQeiCwdOGrBVbmk1wBE/38SCK1iSWxyHm4T9FpkwES7qKk5y4/ R7avY1YkvmXWqT0M/2e41ih4xHXll/nne6xvkJdUMTnYJ4r4x37dYqVxUe7l/SF+ns0F K7jPEiik5uNjU+qXfnG+k4ycvuxBfXnFd1TAB8lKjzGIJ4O4x0cwIPnq+Vg4K8Waqgbx NrXCxtbTxqVtZn3fbPxKEP4gl87okYXy9QVmHaS+oWh7R+HAB3mKkhV0KK19rI0bgjv+ N13w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DlWUJTvQq+dZLt1EiuVf3fldzhye5smOXD/qjtYfqYw=; b=Gs+7gkPgwYlKe1JmHb2gWloxTcXvrEs4GNvrmHe11C/UFfo3VjDPmhca0zP6Op0qE3 roMn+QP8n5Qanl2lhhNY/tNC8ICTNUIBf7UTvfUxI0JlJpEMlALr5ccT7hwcKSPMj0ge xWb/lzPab8S99NKkD6koRG5EHu/+m3XtVYk3sw5CNBZjxqzdEOii4wZNfQCOB+8v8A4U DMyJg0KnCIyk+qiBrNVSY+v7RpmDylv3Dv2FcJPIN4jbsWHcbm/8PkSTNcocpePx8V9f YhS4r6xF4RMGYltR+dlx6/s2ViRmmu9HVtjN8pyjCMdgX2lTZPRdn+cg19z3kvEIdU9e pwkg== X-Gm-Message-State: AFqh2kphzzJHZp0vuzI42wcoeRs6sCHdaph1IphCV0tH0fPlYSGNnVbA erlXEf3I9VB4hOESThxIdHIAsQ== X-Google-Smtp-Source: AMrXdXsV5Jl32Rh3foVUgXPCsZHnUfIjeIK8Q46LFotcnssb//m4oLdfOaYs086TxCiv8YBDTcpTzw== X-Received: by 2002:a05:6a21:398a:b0:af:8e92:3eeb with SMTP id ad10-20020a056a21398a00b000af8e923eebmr4823145pzc.9.1671655250012; Wed, 21 Dec 2022 12:40:50 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id r4-20020aa79884000000b005763c22ea07sm11017784pfl.74.2022.12.21.12.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 12:40:49 -0800 (PST) From: Akihiko Odaki Cc: Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v4 6/7] KVM: arm64: Mask FEAT_CCIDX Date: Thu, 22 Dec 2022 05:40:15 +0900 Message-Id: <20221221204016.658874-7-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221204016.658874-1-akihiko.odaki@daynix.com> References: <20221221204016.658874-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The CCSIDR access handler masks the associativity bits according to the bit layout for processors without FEAT_CCIDX. KVM also assumes CCSIDR is 32-bit where it will be 64-bit if FEAT_CCIDX is enabled. Mask FEAT_CCIDX so that these assumptions hold. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/sys_regs.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f4a7c5abcbca..aeabf1f3370b 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1124,6 +1124,12 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, = struct sys_reg_desc const *r ID_DFR0_PERFMON_SHIFT, kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); break; + case SYS_ID_AA64MMFR2_EL1: + val &=3D ~ID_AA64MMFR2_EL1_CCIDX_MASK; + break; + case SYS_ID_MMFR4_EL1: + val &=3D ~ARM64_FEATURE_MASK(ID_MMFR4_CCIDX); + break; } =20 return val; @@ -1605,6 +1611,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { =20 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, + { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, { SYS_DESC(SYS_CTR_EL0), access_ctr }, @@ -2106,6 +2113,10 @@ static const struct sys_reg_desc cp15_regs[] =3D { =20 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, + + /* CCSIDR2 */ + { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, + { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, }; =20 --=20 2.38.1