From nobody Wed Sep 17 11:59:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 233A2C4167B for ; Tue, 20 Dec 2022 01:13:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232531AbiLTBNR convert rfc822-to-8bit (ORCPT ); Mon, 19 Dec 2022 20:13:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232877AbiLTBM6 (ORCPT ); Mon, 19 Dec 2022 20:12:58 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5902E11C32; Mon, 19 Dec 2022 17:12:56 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id D814324E06F; Tue, 20 Dec 2022 09:12:54 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 20 Dec 2022 09:12:55 +0800 Received: from ubuntu.localdomain (183.27.97.120) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 20 Dec 2022 09:12:53 +0800 From: Hal Feng To: , CC: Conor Dooley , Palmer Dabbelt , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Ben Dooks , Daniel Lezcano , "Thomas Gleixner" , Marc Zyngier , Stephen Boyd , Michael Turquette , "Philipp Zabel" , Linus Walleij , Emil Renner Berthing , Hal Feng , Subject: [PATCH v3 6/7] riscv: dts: starfive: Add initial StarFive JH7110 device tree Date: Tue, 20 Dec 2022 09:12:46 +0800 Message-ID: <20221220011247.35560-7-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221220011247.35560-1-hal.feng@starfivetech.com> References: <20221220011247.35560-1-hal.feng@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.97.120] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Emil Renner Berthing Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd. Signed-off-by: Emil Renner Berthing Co-developed-by: Jianlong Huang Signed-off-by: Jianlong Huang Co-developed-by: Hal Feng Signed-off-by: Hal Feng --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++ 1 file changed, 411 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi new file mode 100644 index 000000000000..64d260ea1f29 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing + */ + +/dts-v1/; +#include +#include + +/ { + compatible =3D "starfive,jh7110"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + S76_0: cpu@0 { + compatible =3D "sifive,u74-mc", "riscv"; + reg =3D <0>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <8192>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <40>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <16384>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <40>; + mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&ccache>; + riscv,isa =3D "rv64imac"; + tlb-split; + status =3D "disabled"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + U74_1: cpu@1 { + compatible =3D "sifive,u74-mc", "riscv"; + reg =3D <1>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <40>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <40>; + mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&ccache>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + U74_2: cpu@2 { + compatible =3D "sifive,u74-mc", "riscv"; + reg =3D <2>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <40>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <40>; + mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&ccache>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + U74_3: cpu@3 { + compatible =3D "sifive,u74-mc", "riscv"; + reg =3D <3>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <40>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <40>; + mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&ccache>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + U74_4: cpu@4 { + compatible =3D "sifive,u74-mc", "riscv"; + reg =3D <4>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <40>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <40>; + mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&ccache>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&S76_0>; + }; + + core1 { + cpu =3D <&U74_1>; + }; + + core2 { + cpu =3D <&U74_2>; + }; + + core3 { + cpu =3D <&U74_3>; + }; + + core4 { + cpu =3D <&U74_4>; + }; + }; + }; + }; + + osc: osc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + rtc_osc: rtc_osc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + gmac0_rmii_refin: gmac0_rmii_refin { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + gmac0_rgmii_rxin: gmac0_rgmii_rxin { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + gmac1_rmii_refin: gmac1_rmii_refin { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + gmac1_rgmii_rxin: gmac1_rgmii_rxin { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + i2stx_bclk_ext: i2stx_bclk_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + i2stx_lrck_ext: i2stx_lrck_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + i2srx_bclk_ext: i2srx_bclk_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + i2srx_lrck_ext: i2srx_lrck_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + tdm_ext: tdm_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + mclk_ext: mclk_ext { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clint: clint@2000000 { + compatible =3D "starfive,jh7110-clint", "sifive,clint0"; + reg =3D <0x0 0x2000000 0x0 0x10000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; + }; + + plic: plic@c000000 { + compatible =3D "starfive,jh7110-plic", "sifive,plic-1.0.0"; + reg =3D <0x0 0xc000000 0x0 0x4000000>; + interrupts-extended =3D <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; + interrupt-controller; + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + riscv,ndev =3D <136>; + }; + + ccache: cache-controller@2010000 { + compatible =3D "starfive,jh7110-ccache", "sifive,ccache0", "cache"; + reg =3D <0x0 0x2010000 0x0 0x4000>; + interrupts =3D <1>, <3>, <4>, <2>; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <2097152>; + cache-unified; + }; + + uart0: serial@10000000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x10000000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_UART0_CORE>, + <&syscrg JH7110_SYSCLK_UART0_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&syscrg JH7110_SYSRST_UART0_APB>; + interrupts =3D <32>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart1: serial@10010000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x10010000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_UART1_CORE>, + <&syscrg JH7110_SYSCLK_UART1_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&syscrg JH7110_SYSRST_UART1_APB>; + interrupts =3D <33>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart2: serial@10020000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x10020000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_UART2_CORE>, + <&syscrg JH7110_SYSCLK_UART2_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&syscrg JH7110_SYSRST_UART2_APB>; + interrupts =3D <34>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart3: serial@12000000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x12000000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_UART3_CORE>, + <&syscrg JH7110_SYSCLK_UART3_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&syscrg JH7110_SYSRST_UART3_APB>; + interrupts =3D <45>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart4: serial@12010000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x12010000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_UART4_CORE>, + <&syscrg JH7110_SYSCLK_UART4_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&syscrg JH7110_SYSRST_UART4_APB>; + interrupts =3D <46>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + uart5: serial@12020000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x0 0x12020000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_UART5_CORE>, + <&syscrg JH7110_SYSCLK_UART5_APB>; + clock-names =3D "baudclk", "apb_pclk"; + resets =3D <&syscrg JH7110_SYSRST_UART5_APB>; + interrupts =3D <47>; + reg-io-width =3D <4>; + reg-shift =3D <2>; + status =3D "disabled"; + }; + + syscrg: clock-controller@13020000 { + compatible =3D "starfive,jh7110-syscrg"; + reg =3D <0x0 0x13020000 0x0 0x10000>; + clocks =3D <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>; + clock-names =3D "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + gpio: gpio@13040000 { + compatible =3D "starfive,jh7110-sys-pinctrl"; + reg =3D <0x0 0x13040000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_IOMUX_APB>; + resets =3D <&syscrg JH7110_SYSRST_IOMUX_APB>; + interrupts =3D <86>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + aoncrg: clock-controller@17000000 { + compatible =3D "starfive,jh7110-aoncrg"; + reg =3D <0x0 0x17000000 0x0 0x10000>; + clocks =3D <&osc>, <&rtc_osc>, + <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; + clock-names =3D "osc", "rtc_osc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus", "gmac0_gtxclk"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + gpioa: gpio@17020000 { + compatible =3D "starfive,jh7110-aon-pinctrl"; + reg =3D <0x0 0x17020000 0x0 0x10000>; + resets =3D <&aoncrg JH7110_AONRST_IOMUX>; + interrupts =3D <85>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + }; + }; +}; --=20 2.38.1