From nobody Sun Apr 12 21:48:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18590C4332F for ; Mon, 19 Dec 2022 18:34:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232396AbiLSSec (ORCPT ); Mon, 19 Dec 2022 13:34:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232562AbiLSSdq (ORCPT ); Mon, 19 Dec 2022 13:33:46 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C2BE14D32 for ; Mon, 19 Dec 2022 10:31:53 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id gt4so9986251pjb.1 for ; Mon, 19 Dec 2022 10:31:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tAhD4QYewlPD8zViG7wcd+O4QOzC8E05GpctTZjGEWs=; b=DQENHD3a54VmP805WbROmXJdgPwrUvjbNGaqG9P7zCIZ2AxPxNw1qsI9bmp7ZEiJWq EyRFXmkbmGHIKu/2MklMP0Z0rrZXksYozWsPTzB4ve6WN56unZDfWdASgsodZ8lqp5Lc lmTx6dUCYzbUWmyp2m5mmInCF9+9bvp+37ou7LvOgAnp+GY6KuGwgNN+BIEb19doaNQC 8SMI5Jy+5b80XpjGTVojROIyUE/KmVCeR9VajCVPaNZUhd4pPERbhgqdHW7ruuIkJIyW 8soZ9c9h13fJSt+kVck33CDGGG/sHcZuA9JsvCnsQ8XAQnZauxSrTZcvodT+uqDZADeh IZBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tAhD4QYewlPD8zViG7wcd+O4QOzC8E05GpctTZjGEWs=; b=RZJVl/UxWoU4Vqqz9Q9O9cUiTgwGTk6TwVLBdR8AbdhQ3MZ/LLIq9ZOYuYu/mm0UOK QpDrynimNwd7kH2M9vpVp10GB0hhNX2PF5JKjkS7pGZEZXdfvf5+xuuqviaAiGua8eWj tZEVeEiHGc9WPLgLwMsfFtMlHwZYYbx6eJpLYnSumsbVv5NCV6MuR3PmB3bWQiuvY6uT Kqjcsn+/JWYuvb5IXap/Yc4WyNIKyy3DN670I6itaTCVE9PK5R5qgaZHZM3TybJ5nASt 2iI1zdsrC3RvDSjVIY+2VPYVd8/kBNV6cKc9RzO48DMVpD6KDzLYGxW9HNMSt0HQDI99 Rd2A== X-Gm-Message-State: AFqh2krezgC8zNZ+o6wZoMuxIm8MfyE3CYgOUEUt6TvmC0KdF8NRrIDi ARfd0SPPCGexQbvnAWpz6EgG X-Google-Smtp-Source: AMrXdXsJ3fbsg8BfmB6PDsoehMnfBnm2358uyS0Atl35IannK5L2b3OWfsHA+zQkhglyOv6lMqZ3Cw== X-Received: by 2002:a17:903:48c:b0:189:6c9a:7d8b with SMTP id jj12-20020a170903048c00b001896c9a7d8bmr10162628plb.32.1671474712975; Mon, 19 Dec 2022 10:31:52 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:31:52 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 15/15] qcom: llcc/edac: Support polling mode for ECC handling Date: Mon, 19 Dec 2022 23:59:58 +0530 Message-Id: <20221219182958.476231-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosen based on Qcom downstream/vendor driver. Reported-by: Luca Weiss Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 37 +++++++++++++++++++++++++----------- drivers/soc/qcom/llcc-qcom.c | 13 ++++++------- 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index f40bb49bccd4..672a09f3b4cb 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -76,6 +76,8 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 =20 +#define ECC_POLL_MSEC 5000 + enum { LLCC_DRAM_CE =3D 0, LLCC_DRAM_UE, @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int= err_type, u32 bank) return ret; } =20 -static irqreturn_t -llcc_ecc_irq_handler(int irq, void *edev_ctl) +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl =3D edev_ctl; struct llcc_drv_data *drv =3D edac_dev_ctl->pvt_info; @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) return irq_rc; } =20 +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) +{ + llcc_ecc_irq_handler(0, edev_ctl); +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data =3D pdev->dev.platform_data; @@ -356,22 +362,31 @@ static int qcom_llcc_edac_probe(struct platform_devic= e *pdev) edev_ctl->panic_on_ue =3D LLCC_ERP_PANIC_ON_UE; edev_ctl->pvt_info =3D llcc_driv_data; =20 + /* Check if LLCC driver has passed ECC IRQ */ + ecc_irq =3D llcc_driv_data->ecc_irq; + if (ecc_irq > 0) { + /* Use interrupt mode if IRQ is available */ + edac_op_state =3D EDAC_OPSTATE_INT; + } else { + /* Fall back to polling mode otherwise */ + edac_op_state =3D EDAC_OPSTATE_POLL; + edev_ctl->poll_msec =3D ECC_POLL_MSEC; + edev_ctl->edac_check =3D llcc_ecc_check; + } + rc =3D edac_device_add_device(edev_ctl); if (rc) goto out_mem; =20 platform_set_drvdata(pdev, edev_ctl); =20 - /* Request for ecc irq */ - ecc_irq =3D llcc_driv_data->ecc_irq; - if (ecc_irq < 0) { - rc =3D -ENODEV; - goto out_dev; - } - rc =3D devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + /* Request ECC IRQ if available */ + if (ecc_irq > 0) { + rc =3D devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); - if (rc) - goto out_dev; + if (rc) + goto out_dev; + } =20 return rc; =20 diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 72f3f2a9aaa0..7b7c5a38bac6 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *= pdev) goto err; =20 drv_data->ecc_irq =3D platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >=3D 0) { - llcc_edac =3D platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); - } + + llcc_edac =3D platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); =20 return 0; err: --=20 2.25.1