From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44C33C10F1B for ; Mon, 19 Dec 2022 18:30:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232360AbiLSSae (ORCPT ); Mon, 19 Dec 2022 13:30:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232334AbiLSSaY (ORCPT ); Mon, 19 Dec 2022 13:30:24 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60F6813E1B for ; Mon, 19 Dec 2022 10:30:22 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id o8-20020a17090a9f8800b00223de0364beso1188268pjp.4 for ; Mon, 19 Dec 2022 10:30:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=USFa3vv6r3M6at72+GYbrAEuQqTIcmw3cLL2W4/Vhuk=; b=mxs/QURMh4Fchj/EQo9a4AGEN62JMD4qI4PsAb5DECS/FWcz6SEegn5LTPabE2SnAZ aqr/d+Vl/CV7+kvD/6L9Qlxo7EEAx6k7r0k+HTS+WCSHrb6dea46bmVMgZtpfXDOgjRR rJqcMYrrmHivbMDQ38bYFhbgngB04BRMW8rStF0cx+U9BW2wSrkLFNENNdtdQ7fpQMvd nNcznUgwpLBV6h8sajGjHUKbf+hliLlOKuLcQMeBsCoWBJ9Lr1xFYW+fqT+z/lqSwAPp SSxwJuPPX/LzqswbbKl5Q2GLkosy/nb9FHL79u/8IEOTDSs9oIBkhHsxr099vmFW8/B6 +VHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=USFa3vv6r3M6at72+GYbrAEuQqTIcmw3cLL2W4/Vhuk=; b=yXBvWPWPSpnwSZHXc7kcm72r0zEwnO+bID6hKWMcIomBAOqvfMtSyU8n7TiYjX0bNU jcVcWrJ+TRT9bNkNT5LiAqKARUwpSo7Iw+nYedzbhG946vqQqBAKjvXR8Ex2ixmy6ao+ Mx00y32ZHQnZE6s8KFTpwm5sJ98vF6IWTtZiaYRV4hBeSFA8KSFrdVlm2fcE//inRUu7 palXlDccgQNYftEr49TgVu3P5YlGfz5rCSyAs6w2USuLmwZvmiyDoHuJbM92fVOuoWT3 NMsb+s9Y10/9wkAoxAcAMHWubkqFL6on3hfDuKygQiRANTfz4OpAp7sA+5CfygQEA2Mv WJ7A== X-Gm-Message-State: ANoB5pn6p6N3Od2JcQ58pdsehizZq0fA5vuqNjBygXP9FUvldG4tDboC 089gwzN8UTyaRn5zVu4BLpkp X-Google-Smtp-Source: AA0mqf5v+vtHo5VuKIcrEBj8EX9SIFPOt/nqRBd8N/jVTS5jLillcOEfaAPUTVUM87uT3teTCIhpCw== X-Received: by 2002:a17:902:6bcc:b0:188:5256:bf60 with SMTP id m12-20020a1709026bcc00b001885256bf60mr42148384plt.25.1671474621807; Mon, 19 Dec 2022 10:30:21 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.30.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:30:20 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v3 01/15] dt-bindings: arm: msm: Update the maintainers for LLCC Date: Mon, 19 Dec 2022 23:59:44 +0530 Message-Id: <20221219182958.476231-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rishabh Bhatnagar has left Qualcomm, and there is no evidence of him maintaining with a new identity. So his entry needs to be removed. Also, Sai Prakash Ranjan's email address should be updated to use quicinc domain. Cc: Sai Prakash Ranjan Acked-by: Sai Prakash Ranjan Acked-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Doc= umentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..d1df49ffcc1b 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller =20 maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Sai Prakash Ranjan =20 description: | LLCC (Last Level Cache Controller) provides last level of cache memory i= n SoC, --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3277C4332F for ; Mon, 19 Dec 2022 18:30:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232391AbiLSSam (ORCPT ); Mon, 19 Dec 2022 13:30:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232387AbiLSSab (ORCPT ); Mon, 19 Dec 2022 13:30:31 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD44313F0C for ; Mon, 19 Dec 2022 10:30:29 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id d3so9839649plr.10 for ; Mon, 19 Dec 2022 10:30:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bp5/r4pBB7Qfe42Kb/SOy1gZ4/1fvqqZd0eC3Bvgy/g=; b=yZTc3yPI+5cJbX8k4KaCD8AISoWi4FSH0Y4kwm9FM5ZoS1kqwPN2JLPXjfssYJq44s mSArQUVe8TmJXm6H0Tj03tQZ+qZwpgWVA4TDEOSejmSBR+3HGTfRV9/VtLMW5f11vfre NXC2SSh/F+wa8YoBW+Jg8Zkd6ikqnhTurm2ut1bKirPNzVgToMhVmn5T7aMn0tg2Fn13 LxkEOUjn6ndUDAyM3Z80WPmGYv8JVLPQDSXhvxi0qaXXH4bf67swLhDd4TA6zoZuIv7G A5v7D8TLQFQoQVMOxQvelst004zRhLhb73Z3ttS9mlPIlJG2N27szYXXgFUSAyHJnAi9 hh5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bp5/r4pBB7Qfe42Kb/SOy1gZ4/1fvqqZd0eC3Bvgy/g=; b=FnSYhtvAM09RNtrC6HUzcRAHQI2PsOZJwWCJOcpQN7PjylPTMOp5+YvN06nOFYqdjM Pk3SZq6MfFgs426F9m8cumt6Oh1V30CLLwyUw1707jjfZG9l1iHsxdz5nKI7GiGaT59T YJg09vurEEfPSSsxdS0xe0jCeCi0hChbVDQTnF0iXcjrHYgG+t2US+9Pt36HZzuI2Ws4 31m/liLJl6CYtWJBWgvOpGWklLjaHJkzC4kHKIonGZNUGZUTLL1EcEhRAb4jYeporD0Q V/Z7ghfxF/Y351TK8cz1wjN+BUwydLih7200t3tCw/t9pwXgAN+4XSFXJuUTfwCpLBEP mVNg== X-Gm-Message-State: ANoB5pmNVe+GcrAhe5h/niK43FRoEFYmpFgEn3N6RvRbDNpAWXMuuOAy LTgxOhZhBolRg9VWmXL2tGl+ X-Google-Smtp-Source: AA0mqf5xpwQUoppAS9nUMHRN5yR/fKI3Fcu3wyMLdLyV0I6CP6nPnodkkBh6npJDFQxWZM/AiqS3gA== X-Received: by 2002:a17:902:8ec6:b0:189:ba1f:b168 with SMTP id x6-20020a1709028ec600b00189ba1fb168mr40692944plo.1.1671474629094; Mon, 19 Dec 2022 10:30:29 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:30:28 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 02/15] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Mon, 19 Dec 2022 23:59:45 +0530 Message-Id: <20221219182958.476231-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are splitted and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Doc= umentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index d1df49ffcc1b..050e21d4a03e 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc =20 reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 =20 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 =20 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false =20 examples: - | #include =20 - system-cache-controller@1100000 { - compatible =3D "qcom,sdm845-llcc"; - reg =3D <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names =3D "llcc_base", "llcc_broadcast_base"; - interrupts =3D ; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + system-cache-controller@1100000 { + compatible =3D "qcom,sdm845-llcc"; + reg =3D <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts =3D ; + }; }; --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7BE4C10F1B for ; Mon, 19 Dec 2022 18:31:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232387AbiLSSbE (ORCPT ); Mon, 19 Dec 2022 13:31:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232158AbiLSSaj (ORCPT ); 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Mon, 19 Dec 2022 10:30:35 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 03/15] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks Date: Mon, 19 Dec 2022 23:59:46 +0530 Message-Id: <20221219182958.476231-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 65032b94b46d..e1c0d9faf46e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2132,8 +2132,11 @@ uart15: serial@a9c000 { =20 llcc: system-cache-controller@1100000 { compatible =3D "qcom,sdm845-llcc"; - reg =3D <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57E0FC4332F for ; Mon, 19 Dec 2022 18:31:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232367AbiLSSbM (ORCPT ); Mon, 19 Dec 2022 13:31:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232349AbiLSSaq (ORCPT ); Mon, 19 Dec 2022 13:30:46 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6710B3D for ; Mon, 19 Dec 2022 10:30:43 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id l10so9853927plb.8 for ; Mon, 19 Dec 2022 10:30:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4GFA6I79C1YmmOYQX1BIX7MOGuUjMMgmSjlJ7uhFCjc=; b=Mc7784uK/Dw0M484InJTvQvSUNDaFw8UiRgYeeDdWTnmReOBwnEaenVNCjR/vLX19t hL+mi+n/PMoOVTJH6HRLDr9WvZCR+YWQTJgwpI3DDrZe97EPKHGd3x6XUBSKpP3+hHdu oQPzCTYD7QO01+XhcMitf+V3QpkpCShljaO60sqQ6eJKc0FB/DeZMylhscXOoPz6hRV1 vj9BFl6uQzkRfVSyEI8DN/IyZKx6M1yUOxjYgRUgYiVfNE1CINmMMLweR9viI8KDnzAg o/qwPNuERzjj+AAWmTTS9ndhK1Ub7wIS9cW7NKIt5Il0Wq4qnOgD3cQDKhBvcCkf6as1 Pc0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4GFA6I79C1YmmOYQX1BIX7MOGuUjMMgmSjlJ7uhFCjc=; b=3xxDTYCaMxMxyPuBKyjwvBzQVQstJ2Umy9Sr3/tLv8cMdo23A0TDVfIBRgWlDyj6/f mGjJ8rI0W8ty5L/KHbOG83CVIRdSAhIpc5bqKFAIHaaJLgJDP4ThEu2EKdpw6hM6aI9+ MIxIBN47m9M39vUHWNSR/Hcegjg7nm1nq/tEDsRzkX4e3e4R1BjGkjLEwIICoupflGfo Zp4SpvaA1CzUj9mSbCREcE3+0OERw96SixFlWRrTjHclESrno5pGzncRpclbVovx2nnA DcIXKqUYaRWA8hmMkRNmMwOhxPLdjrk/YFl5r2WOrIX0d/4pBI0RADJZkk5uTEeiwPP6 LD9w== X-Gm-Message-State: ANoB5pnTnTKEH617hYaDbFr8EeekMal13hq6oqAq4zSDPQ4ItA7ThmRe 1wfEZlOp8kl5vu4rGAbZMEP8 X-Google-Smtp-Source: AA0mqf6Y38L5DAw/sVsUjdYt/zYyUfnStsHv/mEzh7Qzg3UzmexrcTOcJFjATaNtynnHB/8hA45R3Q== X-Received: by 2002:a17:902:c1c5:b0:185:441f:709c with SMTP id c5-20020a170902c1c500b00185441f709cmr43485056plc.33.1671474643251; Mon, 19 Dec 2022 10:30:43 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.30.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:30:42 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 04/15] arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks Date: Mon, 19 Dec 2022 23:59:47 +0530 Message-Id: <20221219182958.476231-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index f71cf21a8dd8..f861f692c9b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2759,7 +2759,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible =3D "qcom,sc7180-llcc"; reg =3D <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg-names =3D "llcc0_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1878BC4332F for ; Mon, 19 Dec 2022 18:31:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231689AbiLSSbR (ORCPT ); Mon, 19 Dec 2022 13:31:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232426AbiLSSay (ORCPT ); Mon, 19 Dec 2022 13:30:54 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B65725F5 for ; Mon, 19 Dec 2022 10:30:50 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id o8-20020a17090a9f8800b00223de0364beso1189636pjp.4 for ; Mon, 19 Dec 2022 10:30:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u3b0H9FlwI0cHeu/QvvhJdFruV0iaHa3piiWtATy1Lw=; b=HmzpXW602W74dkB7Kw4cfxsccMJzLWsYo8Dh2GfPNeaWfTmFfA/VPlD9AJ2mbnOz9D B8ugOhfIIoVycjH3TP0GiwYh91lI9gdYIq+fVOA2OuTjBKAWpyEk2uk55/2DZflfLcI9 D5hMSF+sCUrTxoSpOeKD7GxYNCdir7BgGm93wc61Q0DXBBlH2e6cvN2HB8sdj4XuDTWj iBxIxZ7iTB6of8S+tdm4Ki5NlkBSmX+5JWEYumGQPDwv1kHKFpkP/S7jNLrxhyWFSIH8 rZKL028OZRxFW76HoCOtopOvt8KllnDxUqC1XlXDpkSJnuICamZ3epeV1kt3kgc9O0XQ 9+Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u3b0H9FlwI0cHeu/QvvhJdFruV0iaHa3piiWtATy1Lw=; b=vm3jaBY8erIb/kCdLq74J4MxNr6zW8g5/pDxfUnOMBnchtTI/s7+jlKmE9RCgf1Wj1 fSM3sr/VHiDvUB8h+B8qclHvLPz0rNN3SpVOsrjJyjwbdySAdhoqdQaaHsw72evN1wb7 +RMypBI2vjvbGEf5esy12q9gdSKNQz2twESAY3a8ZCltF2wYbNINybhArGmxL7y/L2B8 ToeMTXIxsxJwzFjk3BaHddkoJMkcOxuPAPk0YiKOVTfgsq/J+x9m9U2boXpdWikJttW1 VSGDaaAw9RJhsd/Kb16jAt8Wc3W6vuCbrlGF50yymMMprv0FWEw5u+W4ldYAdyBP+KZ3 8vKw== X-Gm-Message-State: AFqh2kpBQNBlHp4jod7r1CsUFzmJ+q6ORXqI0Rujeu2RIbsXe8Rq66uF 2DXAR1hAGdLhasRzjzanYxTGUAK//hpWGsc= X-Google-Smtp-Source: AMrXdXu9B7+GsS7cm8a52HEusGRsJ2QSXxJZCnq1M/0ZTtl7VF0b7lcxEyGIy+ZPZ8jwLniAONk8YQ== X-Received: by 2002:a17:902:7786:b0:191:2181:d6e0 with SMTP id o6-20020a170902778600b001912181d6e0mr4853807pll.8.1671474649819; Mon, 19 Dec 2022 10:30:49 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.30.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:30:49 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 05/15] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Date: Mon, 19 Dec 2022 23:59:48 +0530 Message-Id: <20221219182958.476231-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 0adf13399e64..6c6eb6f4f650 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3579,8 +3579,9 @@ gem_noc: interconnect@9100000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sc7280-llcc"; - reg =3D <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9134C4332F for ; Mon, 19 Dec 2022 18:31:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232540AbiLSSbc (ORCPT ); Mon, 19 Dec 2022 13:31:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232351AbiLSSa7 (ORCPT ); Mon, 19 Dec 2022 13:30:59 -0500 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9136A13E05 for ; Mon, 19 Dec 2022 10:30:57 -0800 (PST) Received: by mail-pj1-x102a.google.com with SMTP id n65-20020a17090a2cc700b0021bc5ef7a14so9742806pjd.0 for ; Mon, 19 Dec 2022 10:30:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TVKI7LzAkCeTNtN2kaZFbBM4yejfzWbEhk9TFnMYwYw=; b=UxB7+9w6f7UJlhWOpDUyHTNq8ztOUfkD4+3HYjVO91urw/5K7AseDU7s5oKm5RR2lj ZqPrgyJ4RxNuChOHOO5X0e6x9IDhyKcbAXI0NOeWqjorGuGbD1MKFgSqQ19uuNh/z4jE hMGBPhSTZCPu19sx1PZ6mF9dN0JpFJiQVTOxbCnV/8aVi7+hHTbYC5o4zY9wHEbovuE6 98mS6TR7ZUo0WuHmcaECXkctdt/pQKFEhe7rATXihPK3/nk/W1DRmhK2tlSP7AERhBCp 0iqdvOEbTc7sY56kZqnIlHGKG7dFavwOJheArqnJAURhW3UcoDzjoDfSMnaZqoNWcrFW hwiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TVKI7LzAkCeTNtN2kaZFbBM4yejfzWbEhk9TFnMYwYw=; b=gsVEeyMByy7HmCSYw0WJYsKGeKOSsgLHZwOVHzQybah2AH2Wuo6FcAgbFwKr2z72Eb u8Vqwl4AVRVHrqrsdHUJT75nspRy09kt2ZhCpyREISkA4AUfkpIpL5vRhcrTnGYPWhYj awwGadZhGG2zxENwa/bZI184MvPsgnlPl4DH+fEcpYKBPaxGPzi7eDSzcAUzGLPYARiR 8+VcPy/D5FBHnj+bvYGb9Cs8D4gyMAGtoO4ALcVPKL9lIw4JeTR4IGwkFDptRhEU50AC Dc1AU+E5Pr652Xp2qs/tZqFocUR+bYY+opj1fFoQdwJzwW7dLqzszqkw9yBVdtd4V29d qQOQ== X-Gm-Message-State: AFqh2kqugOKVxpwq37bIrdjB6XaVoyu4VvPK8V8qm94aKMGSMOacg3de PBHNgaPb5zLmDncf0COziTxj X-Google-Smtp-Source: AMrXdXvnE4yBEgROtRiLQq8WY6t8lYQnV7qdY3YWNHLdDV/OujYXa4WK8JSfN8dh9VvjBESJzfUnvQ== X-Received: by 2002:a17:903:2404:b0:18d:61f6:e254 with SMTP id e4-20020a170903240400b0018d61f6e254mr10518563plo.33.1671474657058; Mon, 19 Dec 2022 10:30:57 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:30:56 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 06/15] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks Date: Mon, 19 Dec 2022 23:59:49 +0530 Message-Id: <20221219182958.476231-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 109c9d2b684d..0510a5d510e7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1856,8 +1856,14 @@ opp-6 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sc8280xp-llcc"; - reg =3D <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5E46C4332F for ; Mon, 19 Dec 2022 18:31:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232349AbiLSSbq (ORCPT ); Mon, 19 Dec 2022 13:31:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232517AbiLSSbM (ORCPT ); Mon, 19 Dec 2022 13:31:12 -0500 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FE4F13F0C for ; Mon, 19 Dec 2022 10:31:04 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id w20so3275073ply.12 for ; Mon, 19 Dec 2022 10:31:04 -0800 (PST) DKIM-Signature: v=1; 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Mon, 19 Dec 2022 10:31:03 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:31:02 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 07/15] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks Date: Mon, 19 Dec 2022 23:59:50 +0530 Message-Id: <20221219182958.476231-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index a0c57fb798d3..7fd2291b2638 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1762,8 +1762,11 @@ mmss_noc: interconnect@1740000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8150-llcc"; - reg =3D <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0757AC4332F for ; Mon, 19 Dec 2022 18:32:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232486AbiLSScR (ORCPT ); Mon, 19 Dec 2022 13:32:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232355AbiLSSb3 (ORCPT ); Mon, 19 Dec 2022 13:31:29 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE57513F92 for ; Mon, 19 Dec 2022 10:31:10 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id u5so9946950pjy.5 for ; Mon, 19 Dec 2022 10:31:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WYoJy3okzdnngL6TcLmeGykcAQcBXE1fb+mKXu1bB1c=; b=ga502bOhWRtauXqhYFIN4d5IGCYE3moONP/VI56NzvMKYIF1u13sEGcmQtV4EcnIWP vFMkPvBbRcYXSlVUj/dtbcDLd7cUD5MUUMb6qRJBR1wTsmXIGEZw+qLB2LzAx+TX/c3a VxjHJ0dHvClPk4UPqC5o1DG3hhiF9JVxSLJxHCd6l8OK2hG19cynwaw/75T25RgYkRsM Bi6lHWjVheVtUXSlv0bCM1/NZR4AOcgcJoiqz+sgmmuoP6GT9TRzYxCpnx9RQBjQrHuL DZVNk7+yKfg+JVr3gA0/yz3W+5PJDWigUGvAx3Nq5emGjIzGKSpE/rM147wYa/tk4BrN F32Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WYoJy3okzdnngL6TcLmeGykcAQcBXE1fb+mKXu1bB1c=; b=PW7wFyCk9ktKfqfGW1D1/bZ3EQbPMQdJvuigqFJhxBw+f7SwWcHwHf8iW7URhhmR1e 3h/5Y2c7XTSU40u08ahdXNGIG1k+EbWT7JDFgIJ2uHq3RuPzzE9z83kDWL/I+m1BLO7K BEJRmYB9gaLS7HiF6QvRKmQymJBqtMBKDYP3nlhiSi967QlCGbfLiHPTgkHfHZtBqJCO QMDITjupjrbmI2iXGhPv8f7C/fOpSNcE9c98yO2o6TW/yyAemO8yUGjAyJ+JPgb13LsU ymzEi0tICDlTujxu4qpixKTDHY9O7DXFn0EPy/R/s5/77hNv+wA9A/gyWlMDL9s5Neug sBVw== X-Gm-Message-State: ANoB5plLBLVq7QE/nC1oPuwwoG+YMlaVKzXF+efjj5VT+fudsZcOGxXy mQaNtxE5WNMQxdOEBdwAQFFh X-Google-Smtp-Source: AA0mqf51DRME4KIfhB3G27VvO2P1fI6ju/rftgyBR1c1ALoMHerqGxr7crrCwFKiZPlgceg9JCrAYg== X-Received: by 2002:a17:902:bd44:b0:18f:9b12:35b5 with SMTP id b4-20020a170902bd4400b0018f9b1235b5mr32051121plx.13.1671474670268; Mon, 19 Dec 2022 10:31:10 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.31.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:31:09 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 08/15] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks Date: Mon, 19 Dec 2022 23:59:51 +0530 Message-Id: <20221219182958.476231-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index dab5579946f3..d1b65fb3f3f3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3545,8 +3545,11 @@ usb_1_dwc3: usb@a600000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8250-llcc"; - reg =3D <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; =20 usb_2: usb@a8f8800 { --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C06EDC4332F for ; Mon, 19 Dec 2022 18:32:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231739AbiLSSch (ORCPT ); Mon, 19 Dec 2022 13:32:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232547AbiLSSbr (ORCPT ); Mon, 19 Dec 2022 13:31:47 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E428271C for ; Mon, 19 Dec 2022 10:31:17 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id t11-20020a17090a024b00b0021932afece4so13964615pje.5 for ; Mon, 19 Dec 2022 10:31:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sMev9I+ZdryrTBjzJ8tiTgJp1UwzDLK7UbgCFoQvzyA=; b=ISZcvgYc9T6FYAb2s2G8VhkcsIW+gZf6wwrWxwJTuadTmL8/UwfEsuKZXpfLjT+5aS 9pJQGDzTUqhpIvbASUxiNlkCL7gmxXL5k4xgdrMABF84r2Bs2xV5ZimoEX4bU+faWkqv lbilaaI22QvcUgKQDFzzDaZXiUYDpcbVQ7nIILI7SHaIxA/p1RenEKqVDDxJNNQ8KQTR YzZI/R1dEsYcNqM2tMTwUSFyWGt/b7PSNDnS4FCEaOOShqQ13SDxbPNPolH73sjkhUSj B/CN9eEZejSIprUHRBfYV+b6o7gCKfcJ+xd2zea0dUmHnvjz5JjQ4jW0BtTd8OQPuDEo 2OSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sMev9I+ZdryrTBjzJ8tiTgJp1UwzDLK7UbgCFoQvzyA=; b=We2tAu6rfm1uJfVdT4ZbMayeudCRvx0AtjSMZHswwrgO8iEVicbNhGkLNkMsVjVRXK PvdAIw837zjlwo386b7hMEwuKlF6MS3ySAmqXdB+ldOqolIUQckbWmSW1CeqaVU149DZ lETMGzAduOBM3HIlcc/ojyqKqFViAw0dzMwGbpluJHYZfjbJuVNVYpPLO2h0ZOeyS5Ty YUKRPPK+7gU/xF5bEUOiFfeVHPxaCia7po3ELfAev1MVjM6aGnT8feQKffFZiSuwniNB 0nFLHagqNUNGABdwiBiUoFiqWRw/pXEHqESrtfGE4y2THN8TGW6QoPk6lC5HWq0QK4Yh ZrBA== X-Gm-Message-State: ANoB5pnBKaf5BTx2YwWQU6rWAd9bMjXYTF0ncUdXGTAVwIWasRW2pJYo t2PVi0Gqhw46EXH8vAJ/ezNp X-Google-Smtp-Source: AA0mqf7OeNd+vaSQ7kwiTMRnGFUztWZu465KTvzxOsKQ7TuZ4d9JATNY/D5bXSxfHat8beCw82gKFA== X-Received: by 2002:a17:902:c206:b0:18f:6b2b:e88d with SMTP id 6-20020a170902c20600b0018f6b2be88dmr37998172pll.36.1671474676773; Mon, 19 Dec 2022 10:31:16 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:31:15 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 09/15] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks Date: Mon, 19 Dec 2022 23:59:52 +0530 Message-Id: <20221219182958.476231-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 245dce24ec59..836732d16635 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2513,8 +2513,11 @@ gem_noc: interconnect@9100000 { =20 system-cache-controller@9200000 { compatible =3D "qcom,sm8350-llcc"; - reg =3D <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; =20 usb_1: usb@a6f8800 { --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8200C4332F for ; Mon, 19 Dec 2022 18:32:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232475AbiLSSc4 (ORCPT ); Mon, 19 Dec 2022 13:32:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232433AbiLSScH (ORCPT ); Mon, 19 Dec 2022 13:32:07 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 376CB616F for ; Mon, 19 Dec 2022 10:31:23 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id u7so1677413plq.11 for ; Mon, 19 Dec 2022 10:31:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u6zR8ugZMMSbsUYzZxGLGG2mvpL7z7iHt3BZjr/IYFc=; b=LXYA/o0rsUg+vniZbRgR5ToqfadsQ0+SCYz6AzzwsaP86nSrdcNVXG3of0kTsD9kgz KUDlOO8GcUTFdztbIAGOaGIiTmRJsKyzS9RyQiCLaZwJ59/9OI+DqUNRnFUVNru5N2Gk q/h7Y8yg+Yi12/Ky1QVZcDI9dFjS49LiJF9wt2yOHNqW+2v7XtPicZAbHLTkM2PtnuwQ lA7fwwrbhv6rxo4yJi0pGmGJUFdWNTjkpTjx4LDPgGG4IDtM/x0c5okgiH4gVihsitLT wPvEUJuH9p2yK025Yc3VdYJGGugFJDkJLrTOEmkmOHRh/vLqw2WCfus7n1z35TSw2Msu UyyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u6zR8ugZMMSbsUYzZxGLGG2mvpL7z7iHt3BZjr/IYFc=; b=GMoRzjkoGEDSqzMKuxsi2nMYDbeQdXibBM4B59N//yZbRP5ry4liMsKe10o71oJD7U IGtrteTKo83Ck0Uu0Rl4hhW39BhZ6zyoS/KY4wQRQlICP7n8ZTcW2byDKZeQEK/EKYDl U6wgYFUNHK/kRrWx+oY7gt8ClLRuvWCUlsqk4dVucGPVbxpn9/2xdSwqCIjZMxL2HjEN +GMzRogtOqXwsXJ/JfFyHNviqb0SfGgCGQ4pQw9awjrNna13hlbV29O83XbINfHnNy4r 2rRJnOQIbVXnB9OGFELuB4vw9zSQiCPWT28eVcSfKI0I2ROorN+Ek5GM2PJksPVNqYJ7 H05w== X-Gm-Message-State: AFqh2krBT2RJRLvoLqNsfnd1oHWfL6n9Cweg+Wo6/zj1kY7nGVA2W9G7 odPVolEDPDLRjUyzta1Yf6hR X-Google-Smtp-Source: AMrXdXsq68iRq1AJ4pJ1/A/WhCkhwXRxCkZRc3XhJHrLuf95YiOH0btnO3KPBZpAO41hx01UikeGmQ== X-Received: by 2002:a17:902:f689:b0:191:13f2:173a with SMTP id l9-20020a170902f68900b0019113f2173amr10729999plg.36.1671474682712; Mon, 19 Dec 2022 10:31:22 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:31:21 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 10/15] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks Date: Mon, 19 Dec 2022 23:59:53 +0530 Message-Id: <20221219182958.476231-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 570475040d95..12549a2912c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3640,8 +3640,11 @@ gem_noc: interconnect@19100000 { =20 system-cache-controller@19200000 { compatible =3D "qcom,sm8450-llcc"; - reg =3D <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg =3D <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; + reg-names =3D "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts =3D ; }; =20 --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA48AC4332F for ; Mon, 19 Dec 2022 18:33:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232580AbiLSSdI (ORCPT ); Mon, 19 Dec 2022 13:33:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231931AbiLSScN (ORCPT ); Mon, 19 Dec 2022 13:32:13 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C437A140A4 for ; Mon, 19 Dec 2022 10:31:28 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id a9so9855543pld.7 for ; Mon, 19 Dec 2022 10:31:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=znASgBClq0rwhBOl4/Fw1c5T/s1foKbyxf4XPqRiKDI=; b=ZcH4+Fj7XdRiM5/WNqZ4MSezhDedo6LtSkFK/MVe1KCI2fYu1lmKLZYRnPdzEXrbaw IKBmfIwSJgqonEBBQ/oVHF0lnRKw3hPkffybL01gl+f5T4eF2EaTlv6wWovnduWoEDFo pHebHcqk46zQtuWhJom59c2X3EkLupK+qh4Wh3pUX5/dSfKr9X2A/LeNTU8NdbsxQyPm kL4HjU79zRaUfq2L47qEJA4/SElSccv8nFI8MkjLrZxNfXtfYmmyHea5G217gUtvWtNU 9+h3ARHlC9Zgi/j8/sM91gT455506xFLZ68SITuaRPaYYjiJshwOJOLe8z2oFAhu5FMK XpgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=znASgBClq0rwhBOl4/Fw1c5T/s1foKbyxf4XPqRiKDI=; b=hYne4Y6w6HBrAP9znG5nflI30M9CLzC+dKkhn7Rob4roI9RmYp7yNP+eaLF740jFt6 DkAZbkz9QTlgXnXWnBZ8mkUB2QbrqOqGMAZ7qrk7YD+kjD854drTuxyfFsVkpbcy0071 tYjb+yHu3femvnEyffZD5MK/prcZEBvR5KL+XObb931kGJIjtgVF+gZjTdvn8OnlWgKx UVqU7cpdLQYko/7WK52yXO/jueDhfewDXVTuaUPekj0xaFxFr/ZbIgbp8wgFCBvBtZpg vwQCpEyiTNVWEVc2FDLpv935TQWMBNg9tXt5TeUGZF3q1gbv1vzLghXgEK299AD82Cwo kZgA== X-Gm-Message-State: AFqh2krYmgqC6zDy/lUu5wO+OG1X6AbZv+qA1z8R1YKcNY6wKBXtJ5E+ xmbXzr/Rl2Ruv5iPmarWRuIg X-Google-Smtp-Source: AMrXdXtqsUgo7FWaAMNH+5312ZU8Op04PM/Mc9HwDsUnlhNsQzBakGF+NpJR8S2x9DH7ZyYN+JqU5w== X-Received: by 2002:a17:902:e845:b0:188:fc0c:b736 with SMTP id t5-20020a170902e84500b00188fc0cb736mr15763512plg.67.1671474688106; Mon, 19 Dec 2022 10:31:28 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:31:27 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 11/15] arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks Date: Mon, 19 Dec 2022 23:59:54 +0530 Message-Id: <20221219182958.476231-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 43324bf291c3..c7701f5e4af6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1174,7 +1174,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible =3D "qcom,sm6350-llcc"; reg =3D <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names =3D "llcc_base", "llcc_broadcast_base"; + reg-names =3D "llcc0_base", "llcc_broadcast_base"; }; =20 gem_noc: interconnect@9680000 { --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05EFBC10F1B for ; Mon, 19 Dec 2022 18:33:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232370AbiLSSd2 (ORCPT ); Mon, 19 Dec 2022 13:33:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232554AbiLSScU (ORCPT ); Mon, 19 Dec 2022 13:32:20 -0500 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E80B513DF8 for ; Mon, 19 Dec 2022 10:31:33 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id 17so9925743pll.0 for ; Mon, 19 Dec 2022 10:31:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d0mC3YHxzlEQlwMPao/Y7ASve0hKwhscYa/RkKUoFYA=; b=XP3AwAH3vWxz0xfNNFiGJ5EgonMs84vx5Gf0ya1zoxdRXLS4mgG7GJljlIBSp3sWSp pE/P+777utad613pX0v1LpwSeiQaQvT4BLznyztZI4BRxJ5UCdxvQf89huY3c6odg0BZ beom1cAixCxe2nouy47FZellniD8Vj/wWCeqrhrqnkFR5Qq6FVs9El10bowukBUYxbJ0 xPlgcxMmxk4q03q9VnvSF3FMGZEKbhc1dlcU1cDCt9J7ry2zH1y19dccMivVxxN4upEw VJcf3SeWyVV/qqV6sPnsX4Li7PS8XBkntHkOC/PKcKZHZEyaZWDgxxizO3meAyubPNKE VQZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d0mC3YHxzlEQlwMPao/Y7ASve0hKwhscYa/RkKUoFYA=; b=i+p63i7FYYyj1wAitwrlVPjjX1fVxttruEfZtYc03q8ovQS3WBIdNfMSzh58mpECa6 fkQd6HMWnGjYbMcsIzGADVD2//W1wMVALjNmzBLk5w2zh4DDUuwaYnVQSIwfZsKCdO5/ YvJEwH275XygKIo33r9OIyNST9cPBD4Ei5m35+bybu0D70Rr+3DuJvv/xPyHpxNpFTVC EvTWULtNt39dyXC/Pu+Zn4dhJjYVdTUZSVXBf6rN856DLT8i6/XyD+q71rZbakB6I2ij pNUuFPLx06cWNW/LvtGH5qNvxU+e07pj6xRU+PqylCrOHGHqcWR3xv0HXhbaIBs0qWxa Z4Jg== X-Gm-Message-State: ANoB5pkhovVVlPUcy7sj1KNAHAixkmIMiIAgVpVLubafC/gl2dMRQ8Ac 0I8XBw6iMF2l08ymZmSVSl7e X-Google-Smtp-Source: AA0mqf68ucZQ4pkSIP4B+LV1flkcOGQPj3b5PkGW/rCTTB9ay4fMMIaU9BVc6OCx2wDMonxlDiHDWg== X-Received: by 2002:a17:903:251:b0:189:7891:574d with SMTP id j17-20020a170903025100b001897891574dmr50681181plh.47.1671474693614; Mon, 19 Dec 2022 10:31:33 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:31:32 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v3 12/15] EDAC/device: Make use of poll_msec value in edac_device_ctl_info struct Date: Mon, 19 Dec 2022 23:59:55 +0530 Message-Id: <20221219182958.476231-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The EDAC drivers may optionally pass the poll_msec value. Use that value if available, else fall back to 1000ms. Cc: # 4.9 Fixes: e27e3dac6517 ("drivers/edac: add edac_device class") Reported-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- drivers/edac/edac_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/edac_device.c b/drivers/edac/edac_device.c index 19522c568aa5..19c3ab2a434e 100644 --- a/drivers/edac/edac_device.c +++ b/drivers/edac/edac_device.c @@ -447,7 +447,7 @@ int edac_device_add_device(struct edac_device_ctl_info = *edac_dev) * enable workq processing on this instance, * default =3D 1000 msec */ - edac_device_workq_setup(edac_dev, 1000); + edac_device_workq_setup(edac_dev, edac_dev->poll_msec ? edac_dev->poll_m= sec : 1000); } else { edac_dev->op_state =3D OP_RUNNING_INTERRUPT; } --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 002AAC4332F for ; Mon, 19 Dec 2022 18:33:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232346AbiLSSdx (ORCPT ); Mon, 19 Dec 2022 13:33:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232405AbiLSScx (ORCPT ); Mon, 19 Dec 2022 13:32:53 -0500 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD3BD140F4 for ; Mon, 19 Dec 2022 10:31:40 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id t2so9890131ply.2 for ; Mon, 19 Dec 2022 10:31:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/mWLM+xjtkcHtTlHLK0FQlJaaC6ncfnZviWhmaPi0lM=; b=qZ0DvYBLrUPKCItDG/754HTBRDZshK7oQme3AAh5u9MJcyEo9DpFvFWLCor+S5AkX+ OhTdL8gEbszkP7lyRdCbap2/6+1yQrFS3x9xCvH4+RGMPXfFnn1SCf0lv9y/mZ5JsTW4 b8nv6GP929ZKxgu+tEFRKz7wor582zzTRHERLtFa4NSOdFJToPXKQxbmB+Y5o3KXEbfw Zp3TwqN4C22wdmth7phpaCUnjJL89Y/xuiornJ8jZ5J4OfNWZrNZgiQ8Yk2fg+TYVX+X 69f/U1j+SPZJrRLtpaN245C9QOLBdAPE76PCnHA3s73j0fWvewj0XSXW3MVKDxO8tBEs qxLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/mWLM+xjtkcHtTlHLK0FQlJaaC6ncfnZviWhmaPi0lM=; b=6nMmlt0gh+obT759YqDdoipLeclaWwKiBypn7xohEh57CPXVIU5wuADI6KDmgRiw83 2LQogOG/Wa0p1CjIA3tR0Nas0qn6XEAw23IEthP/h+9WMg6zZXQhGR1MxbkbA7uOd2x5 Gr9VNcEjdx7R+Ppn7GHZsLpEmqlcIybgIpcAyur+mHci8zMEJEAhQM80gcaleYx2hmW+ rX/85heM7VWNIiGVG93n0qhW6MMDZMZf9Y0UQ2KE+1f0XOv0SqVwBDM2j1Xm8otw3R09 SFwKCFfHQJjp5WIEUsM2asr1sp2w1i4FDzXb66iMOxITVuoyr9aWncW0IHUCK1kwgjSV YgrA== X-Gm-Message-State: ANoB5pkJob+aIySR4qx3Cy59lsqb+kKLuxrRgkKM5nQ/VGSIGdc5y3Uw 2SwS0AEIEKpg2MUqfVSwGYJS X-Google-Smtp-Source: AA0mqf55NYWXIIemHerLmljoYqXyTYYTKw+2SQmde47ZvnjotMfseOOnCrPdpivq4q+wuMescLn8uQ== X-Received: by 2002:a17:902:9a43:b0:187:16c2:d52c with SMTP id x3-20020a1709029a4300b0018716c2d52cmr40519635plv.50.1671474699946; Mon, 19 Dec 2022 10:31:39 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:31:38 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 13/15] EDAC/qcom: Add platform_device_id table for module autoloading Date: Mon, 19 Dec 2022 23:59:56 +0530 Message-Id: <20221219182958.476231-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" platform_device_id table needs to be added so that the driver can be autoloaded when the associated platform device gets registered. Reported-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..9e77fa84e84f 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -397,12 +397,19 @@ static int qcom_llcc_edac_remove(struct platform_devi= ce *pdev) return 0; } =20 +static const struct platform_device_id qcom_llcc_edac_id_table[] =3D { + { .name =3D "qcom_llcc_edac" }, + {} +}; +MODULE_DEVICE_TABLE(platform, qcom_llcc_edac_id_table); + static struct platform_driver qcom_llcc_edac_driver =3D { .probe =3D qcom_llcc_edac_probe, .remove =3D qcom_llcc_edac_remove, .driver =3D { .name =3D "qcom_llcc_edac", }, + .id_table =3D qcom_llcc_edac_id_table, }; module_platform_driver(qcom_llcc_edac_driver); =20 --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C70CDC4332F for ; Mon, 19 Dec 2022 18:34:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232491AbiLSSeL (ORCPT ); Mon, 19 Dec 2022 13:34:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232609AbiLSSdV (ORCPT ); Mon, 19 Dec 2022 13:33:21 -0500 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73BFB13F3C for ; Mon, 19 Dec 2022 10:31:47 -0800 (PST) Received: by mail-pl1-x635.google.com with SMTP id d3so9843129plr.10 for ; Mon, 19 Dec 2022 10:31:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U0UVprkCJUNnL3nMo7DxPvkgB/NZqmZRp7qZPXJUTiQ=; b=v5Q/tsiTj8CO9hRqpilsQt5aaiHSL8pJaJwb6zanTE3fKoa/ebUg5aUv0PeyWt3Nc/ BwOp2KFZQvmHDB+VERDrQVBZZxm684dQkxm5sZR1DXxjnR4auPtJhDDa/PdF/GHQlUye kk42kz/EUFAH6bSPswPvS1fiLDFopuP9X4zqE82oGqk39UrQ6Vwo769pxNvlKCmWAyFb CQtJzXrST5spINEiLoSz7dIQaE1sI/ytDJqeSKIe4DU/zOIEMa/wVPIpNc0NI5Ak63fn lfX8ccDj3ZkkCV31dmSEtS6El2irbZWXeMnrQs/dD9spiUuM8jA2K6ZCxh9XKPWoQU1K 52XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U0UVprkCJUNnL3nMo7DxPvkgB/NZqmZRp7qZPXJUTiQ=; b=OhlAOst6yhBk/LV7YhSr3k1FO9Pkwh7BTDqTH4EjeQYYuUDOnDaYw8i3+Re16ItB5S 4EUYF2SUsU9RxwhU8LYswAseccZyXHNTP2Pnejce1P6ZMfTy/NerEIjKA42rGqs9YaLE XkQ+e1Qk0DmNZH766wEbIufWBvCH0S4zKf9ZK2LcdsGN9MvrFA0CqEi0L3Zo1mvHEdfC oXI4wBlZuEoVAhmHqOc1k5zJ+/vMJ4edJEi8JkmsHWRkVkdTURK2K6IkiYSvFkEhnOfN qmSlvQkknwoN3hwr/53XHTRN4kbz84CtXGoEKLRnwDFnQnqhAxeIWFIjgiesA/oIJysy nVdQ== X-Gm-Message-State: AFqh2kpog79EyBZENNZZiA9FVIiVvNoXraQl9pS/CAhKm3rYAEAbqnSr 7VdGlPPiB7eqi6qADN7Cp1/N X-Google-Smtp-Source: AMrXdXvvWi5urLOltFHSWO9XTwbdECM7insHBSpYDH1ndNoV8DUX4qdhGv33xv3vkntPREWim1pzAQ== X-Received: by 2002:a17:902:7841:b0:190:fd03:7d3d with SMTP id e1-20020a170902784100b00190fd037d3dmr7851975pln.56.1671474707019; Mon, 19 Dec 2022 10:31:47 -0800 (PST) Received: from localhost.localdomain ([220.158.159.17]) by smtp.gmail.com with ESMTPSA id d2-20020a170903230200b00186e34524e3sm7480979plh.136.2022.12.19.10.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 10:31:46 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, Manivannan Sadhasivam Subject: [PATCH v3 14/15] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Date: Mon, 19 Dec 2022 23:59:57 +0530 Message-Id: <20221219182958.476231-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> References: <20221219182958.476231-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, we no longer need to rely on reg-names property and get the base addresses using index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those needs to be defined in devicetree for index from 1..N-1. Reported-by: Parikshit Pareek Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 14 +++--- drivers/soc/qcom/llcc-qcom.c | 72 +++++++++++++++++------------- include/linux/soc/qcom/llcc-qcom.h | 6 +-- 3 files changed, 48 insertions(+), 44 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 9e77fa84e84f..f40bb49bccd4 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) =20 for (i =3D 0; i < reg_data.reg_cnt; i++) { synd_reg =3D reg_data.synd_reg + (i * 4); - ret =3D regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret =3D regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) reg_data.name, i, synd_val); } =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret =3D regmap_read(drv->regmaps[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret =3D regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) =20 /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i =3D 0; i < drv->num_banks; i++) { - ret =3D regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret =3D regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, &drp_error); =20 if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc =3D IRQ_HANDLED; =20 - ret =3D regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret =3D regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, &trp_error); =20 if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..72f3f2a9aaa0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 =20 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -898,8 +896,8 @@ static int qcom_llcc_remove(struct platform_device *pde= v) return 0; } =20 -static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, - const char *name) +static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8= index, + const char *name) { void __iomem *base; struct regmap_config llcc_regmap_config =3D { @@ -909,7 +907,7 @@ static struct regmap *qcom_llcc_init_mmio(struct platfo= rm_device *pdev, .fast_io =3D true, }; =20 - base =3D devm_platform_ioremap_resource_byname(pdev, name); + base =3D devm_platform_ioremap_resource(pdev, index); if (IS_ERR(base)) return ERR_CAST(base); =20 @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; =20 drv_data =3D devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,21 +933,51 @@ static int qcom_llcc_probe(struct platform_device *pd= ev) goto err; } =20 - drv_data->regmap =3D qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret =3D PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap =3D qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); + if (IS_ERR(regmap)) { + ret =3D PTR_ERR(regmap); goto err; } =20 - drv_data->bcast_regmap =3D - qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); + cfg =3D of_device_get_match_data(&pdev->dev); + + ret =3D regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_ba= nks); + if (ret) + goto err; + + num_banks &=3D LLCC_LB_CNT_MASK; + num_banks >>=3D LLCC_LB_CNT_SHIFT; + drv_data->num_banks =3D num_banks; + + drv_data->regmaps =3D devm_kcalloc(dev, num_banks, sizeof(*drv_data->regm= aps), GFP_KERNEL); + if (!drv_data->regmaps) { + ret =3D -ENOMEM; + goto err; + } + + drv_data->regmaps[0] =3D regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i =3D 1; i < num_banks; i++) { + char *base =3D kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmaps[i] =3D qcom_llcc_init_mmio(pdev, i, base); + if (IS_ERR(drv_data->regmaps[i])) { + ret =3D PTR_ERR(drv_data->regmaps[i]); + kfree(base); + goto err; + } + + kfree(base); + } + + drv_data->bcast_regmap =3D qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_b= ase"); if (IS_ERR(drv_data->bcast_regmap)) { ret =3D PTR_ERR(drv_data->bcast_regmap); goto err; } =20 - cfg =3D of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret =3D regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_H= W_INFO], &version); @@ -957,15 +986,6 @@ static int qcom_llcc_probe(struct platform_device *pde= v) =20 drv_data->version =3D version; =20 - ret =3D regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0= ], - &num_banks); - if (ret) - goto err; - - num_banks &=3D LLCC_LB_CNT_MASK; - num_banks >>=3D LLCC_LB_CNT_SHIFT; - drv_data->num_banks =3D num_banks; - llcc_cfg =3D cfg->sct_data; sz =3D cfg->size; =20 @@ -973,16 +993,6 @@ static int qcom_llcc_probe(struct platform_device *pde= v) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices =3D llcc_cfg[i].slice_id; =20 - drv_data->offsets =3D devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret =3D -ENOMEM; - goto err; - } - - for (i =3D 0; i < num_banks; i++) - drv_data->offsets[i] =3D i * BANK_OFFSET_STRIDE; - drv_data->bitmap =3D devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index ad1fd718169d..423220e66026 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -120,7 +120,7 @@ struct llcc_edac_reg_offset { =20 /** * struct llcc_drv_data - Data associated with the llcc driver - * @regmap: regmap associated with the llcc device + * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmaps; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; --=20 2.25.1 From nobody Sun Apr 12 20:06:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18590C4332F for ; Mon, 19 Dec 2022 18:34:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232396AbiLSSec (ORCPT ); Mon, 19 Dec 2022 13:34:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232562AbiLSSdq (ORCPT ); Mon, 19 Dec 2022 13:33:46 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C2BE14D32 for ; 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charset="utf-8" Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosen based on Qcom downstream/vendor driver. Reported-by: Luca Weiss Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 37 +++++++++++++++++++++++++----------- drivers/soc/qcom/llcc-qcom.c | 13 ++++++------- 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index f40bb49bccd4..672a09f3b4cb 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -76,6 +76,8 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 =20 +#define ECC_POLL_MSEC 5000 + enum { LLCC_DRAM_CE =3D 0, LLCC_DRAM_UE, @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int= err_type, u32 bank) return ret; } =20 -static irqreturn_t -llcc_ecc_irq_handler(int irq, void *edev_ctl) +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl =3D edev_ctl; struct llcc_drv_data *drv =3D edac_dev_ctl->pvt_info; @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) return irq_rc; } =20 +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) +{ + llcc_ecc_irq_handler(0, edev_ctl); +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data =3D pdev->dev.platform_data; @@ -356,22 +362,31 @@ static int qcom_llcc_edac_probe(struct platform_devic= e *pdev) edev_ctl->panic_on_ue =3D LLCC_ERP_PANIC_ON_UE; edev_ctl->pvt_info =3D llcc_driv_data; =20 + /* Check if LLCC driver has passed ECC IRQ */ + ecc_irq =3D llcc_driv_data->ecc_irq; + if (ecc_irq > 0) { + /* Use interrupt mode if IRQ is available */ + edac_op_state =3D EDAC_OPSTATE_INT; + } else { + /* Fall back to polling mode otherwise */ + edac_op_state =3D EDAC_OPSTATE_POLL; + edev_ctl->poll_msec =3D ECC_POLL_MSEC; + edev_ctl->edac_check =3D llcc_ecc_check; + } + rc =3D edac_device_add_device(edev_ctl); if (rc) goto out_mem; =20 platform_set_drvdata(pdev, edev_ctl); =20 - /* Request for ecc irq */ - ecc_irq =3D llcc_driv_data->ecc_irq; - if (ecc_irq < 0) { - rc =3D -ENODEV; - goto out_dev; - } - rc =3D devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + /* Request ECC IRQ if available */ + if (ecc_irq > 0) { + rc =3D devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); - if (rc) - goto out_dev; + if (rc) + goto out_dev; + } =20 return rc; =20 diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 72f3f2a9aaa0..7b7c5a38bac6 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *= pdev) goto err; =20 drv_data->ecc_irq =3D platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >=3D 0) { - llcc_edac =3D platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); - } + + llcc_edac =3D platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); =20 return 0; err: --=20 2.25.1