From nobody Sun Apr 12 21:46:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD719C4332F for ; Sun, 18 Dec 2022 18:10:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230503AbiLRSKa (ORCPT ); Sun, 18 Dec 2022 13:10:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230499AbiLRSKC (ORCPT ); Sun, 18 Dec 2022 13:10:02 -0500 Received: from mail-il1-x134.google.com (mail-il1-x134.google.com [IPv6:2607:f8b0:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFCB6D6526; Sun, 18 Dec 2022 09:05:55 -0800 (PST) Received: by mail-il1-x134.google.com with SMTP id y2so3741429ily.5; Sun, 18 Dec 2022 09:05:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=OgOSUqKhKmN0gkj/ZYhYVdSQNMe/JfU2z8Ox21C/PKc=; b=oSovyA7APlyKf7MOPiKXb/QkUKMc2CL02XPXvn1xFgfpOyBDfJu5uRGwxU68f2qKlh kpSr+9aK2zk3LA+1Avy9stR80djC2M3MmhOCus4tvJPra20BKooLT3SBSiaQnAdDy6N+ XF8nhpWr3877mVxm2SGhZTlQkyGzyo8r3FddCvw4oyXLFQnoRCiEEggPuCId1g9TpJUa /LlTFy9ZeZsEvuuNXP8aeDf+P1JnWopBbL8ColIi0F2bEpro62m6fjCMPeqE7HnsV4J2 mXAWSsSWqHnw2Z1kN0bO6ZPRHkDJ0kn8S3hGqJLNiBs3S6AnC9V3LaEcy+KrgWXODfKV 0nPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=OgOSUqKhKmN0gkj/ZYhYVdSQNMe/JfU2z8Ox21C/PKc=; b=5PQbrAdSoyJOcZJZ7ZLyRxAX3S0UpXV8XSQTZDl7vSzeqWg2HfiQ2eMJKY3FMssMzj XYB3NKn//9jm2qIBB4Wwm/n+CIqRbFsCbAxNUE3X0PvMvO26luKgUIdbkGfiJ1+YwolU I7tbiFB2h96ptHnU1bBQ4gQ2oIuKCN8iZlqNTerpTjhe/qHAxuamEIwd/h9R8p4znimH EL02gGD79sCo6zpfRmaxr1CC3vJwxdOHYBI/hDbGg1aWT9je12jzUiAFuwhXpDv66VC7 JoguAD+Ca1DeZ5T0bAxsTGe6o9EIR169HcLsxwvCQW1zKc5AxydapAgzJL93vE6oiybr 1GHQ== X-Gm-Message-State: AFqh2kqzqARaIcFMAREQsCD810Kg/2XA1pj6Ph0tpqVS7D4EURSXV1kk wUsoid3TdG+xRWO+xTzPCOI= X-Google-Smtp-Source: AMrXdXs6L4V8GTvalb5dTD0ZHa08kBUqeHPwuHOh2OVborwiR2Mlj8A7tn12vGnNWCdM/odmnpVjlg== X-Received: by 2002:a92:c805:0:b0:303:452b:27e1 with SMTP id v5-20020a92c805000000b00303452b27e1mr3749960iln.28.1671383154119; Sun, 18 Dec 2022 09:05:54 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:447:d001:9aea:c8ad:17b9:7862:6614]) by smtp.gmail.com with ESMTPSA id n15-20020a92dd0f000000b003032a97913asm2525296ilm.17.2022.12.18.09.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Dec 2022 09:05:53 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Cc: aford@beaconembedded.com, marex@denx.de, Adam Ford , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: imx8mp: Enable spba-bus on AIPS3 Date: Sun, 18 Dec 2022 11:05:44 -0600 Message-Id: <20221218170545.1472746-1-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is an SPBA bus on AIPS3 which includes ecspi1-3, UART1-3, and Flexcan1-2 according to the TRM. Signed-off-by: Adam Ford diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index 2ce45e7cbbdf..9b0a47e7b8fd 100644 Reviewed-by: Marco Felsch --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -719,121 +719,129 @@ aips3: bus@30800000 { #size-cells =3D <1>; ranges; =20 - ecspi1: spi@30820000 { + spba-bus@30800000 { + compatible =3D "fsl,spba-bus", "simple-bus"; + reg =3D <0x30800000 0x100000>; #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; - reg =3D <0x30820000 0x10000>; - interrupts =3D ; - clocks =3D <&clk IMX8MP_CLK_ECSPI1_ROOT>, - <&clk IMX8MP_CLK_ECSPI1_ROOT>; - clock-names =3D "ipg", "per"; - assigned-clock-rates =3D <80000000>; - assigned-clocks =3D <&clk IMX8MP_CLK_ECSPI1>; - assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_800M>; - dmas =3D <&sdma1 0 7 1>, <&sdma1 1 7 2>; - dma-names =3D "rx", "tx"; - status =3D "disabled"; - }; + #size-cells =3D <1>; + ranges; =20 - ecspi2: spi@30830000 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; - reg =3D <0x30830000 0x10000>; - interrupts =3D ; - clocks =3D <&clk IMX8MP_CLK_ECSPI2_ROOT>, - <&clk IMX8MP_CLK_ECSPI2_ROOT>; - clock-names =3D "ipg", "per"; - assigned-clock-rates =3D <80000000>; - assigned-clocks =3D <&clk IMX8MP_CLK_ECSPI2>; - assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_800M>; - dmas =3D <&sdma1 2 7 1>, <&sdma1 3 7 2>; - dma-names =3D "rx", "tx"; - status =3D "disabled"; - }; + ecspi1: spi@30820000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg =3D <0x30820000 0x10000>; + interrupts =3D ; + clocks =3D <&clk IMX8MP_CLK_ECSPI1_ROOT>, + <&clk IMX8MP_CLK_ECSPI1_ROOT>; + clock-names =3D "ipg", "per"; + assigned-clock-rates =3D <80000000>; + assigned-clocks =3D <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_800M>; + dmas =3D <&sdma1 0 7 1>, <&sdma1 1 7 2>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; =20 - ecspi3: spi@30840000 { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; - reg =3D <0x30840000 0x10000>; - interrupts =3D ; - clocks =3D <&clk IMX8MP_CLK_ECSPI3_ROOT>, - <&clk IMX8MP_CLK_ECSPI3_ROOT>; - clock-names =3D "ipg", "per"; - assigned-clock-rates =3D <80000000>; - assigned-clocks =3D <&clk IMX8MP_CLK_ECSPI3>; - assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_800M>; - dmas =3D <&sdma1 4 7 1>, <&sdma1 5 7 2>; - dma-names =3D "rx", "tx"; - status =3D "disabled"; - }; + ecspi2: spi@30830000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg =3D <0x30830000 0x10000>; + interrupts =3D ; + clocks =3D <&clk IMX8MP_CLK_ECSPI2_ROOT>, + <&clk IMX8MP_CLK_ECSPI2_ROOT>; + clock-names =3D "ipg", "per"; + assigned-clock-rates =3D <80000000>; + assigned-clocks =3D <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_800M>; + dmas =3D <&sdma1 2 7 1>, <&sdma1 3 7 2>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; =20 - uart1: serial@30860000 { - compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg =3D <0x30860000 0x10000>; - interrupts =3D ; - clocks =3D <&clk IMX8MP_CLK_UART1_ROOT>, - <&clk IMX8MP_CLK_UART1_ROOT>; - clock-names =3D "ipg", "per"; - dmas =3D <&sdma1 22 4 0>, <&sdma1 23 4 0>; - dma-names =3D "rx", "tx"; - status =3D "disabled"; - }; + ecspi3: spi@30840000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; + reg =3D <0x30840000 0x10000>; + interrupts =3D ; + clocks =3D <&clk IMX8MP_CLK_ECSPI3_ROOT>, + <&clk IMX8MP_CLK_ECSPI3_ROOT>; + clock-names =3D "ipg", "per"; + assigned-clock-rates =3D <80000000>; + assigned-clocks =3D <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_800M>; + dmas =3D <&sdma1 4 7 1>, <&sdma1 5 7 2>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; =20 - uart3: serial@30880000 { - compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg =3D <0x30880000 0x10000>; - interrupts =3D ; - clocks =3D <&clk IMX8MP_CLK_UART3_ROOT>, - <&clk IMX8MP_CLK_UART3_ROOT>; - clock-names =3D "ipg", "per"; - dmas =3D <&sdma1 26 4 0>, <&sdma1 27 4 0>; - dma-names =3D "rx", "tx"; - status =3D "disabled"; - }; + uart1: serial@30860000 { + compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg =3D <0x30860000 0x10000>; + interrupts =3D ; + clocks =3D <&clk IMX8MP_CLK_UART1_ROOT>, + <&clk IMX8MP_CLK_UART1_ROOT>; + clock-names =3D "ipg", "per"; + dmas =3D <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; =20 - uart2: serial@30890000 { - compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; - reg =3D <0x30890000 0x10000>; - interrupts =3D ; - clocks =3D <&clk IMX8MP_CLK_UART2_ROOT>, - <&clk IMX8MP_CLK_UART2_ROOT>; - clock-names =3D "ipg", "per"; - dmas =3D <&sdma1 24 4 0>, <&sdma1 25 4 0>; - dma-names =3D "rx", "tx"; - status =3D "disabled"; - }; + uart3: serial@30880000 { + compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg =3D <0x30880000 0x10000>; + interrupts =3D ; + clocks =3D <&clk IMX8MP_CLK_UART3_ROOT>, + <&clk IMX8MP_CLK_UART3_ROOT>; + clock-names =3D "ipg", "per"; + dmas =3D <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; =20 - flexcan1: can@308c0000 { - compatible =3D "fsl,imx8mp-flexcan"; - reg =3D <0x308c0000 0x10000>; - interrupts =3D ; - clocks =3D <&clk IMX8MP_CLK_IPG_ROOT>, - <&clk IMX8MP_CLK_CAN1_ROOT>; - clock-names =3D "ipg", "per"; - assigned-clocks =3D <&clk IMX8MP_CLK_CAN1>; - assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_40M>; - assigned-clock-rates =3D <40000000>; - fsl,clk-source =3D /bits/ 8 <0>; - fsl,stop-mode =3D <&gpr 0x10 4>; - status =3D "disabled"; - }; + uart2: serial@30890000 { + compatible =3D "fsl,imx8mp-uart", "fsl,imx6q-uart"; + reg =3D <0x30890000 0x10000>; + interrupts =3D ; + clocks =3D <&clk IMX8MP_CLK_UART2_ROOT>, + <&clk IMX8MP_CLK_UART2_ROOT>; + clock-names =3D "ipg", "per"; + dmas =3D <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; =20 - flexcan2: can@308d0000 { - compatible =3D "fsl,imx8mp-flexcan"; - reg =3D <0x308d0000 0x10000>; - interrupts =3D ; - clocks =3D <&clk IMX8MP_CLK_IPG_ROOT>, - <&clk IMX8MP_CLK_CAN2_ROOT>; - clock-names =3D "ipg", "per"; - assigned-clocks =3D <&clk IMX8MP_CLK_CAN2>; - assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_40M>; - assigned-clock-rates =3D <40000000>; - fsl,clk-source =3D /bits/ 8 <0>; - fsl,stop-mode =3D <&gpr 0x10 5>; - status =3D "disabled"; + flexcan1: can@308c0000 { + compatible =3D "fsl,imx8mp-flexcan"; + reg =3D <0x308c0000 0x10000>; + interrupts =3D ; + clocks =3D <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names =3D "ipg", "per"; + assigned-clocks =3D <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates =3D <40000000>; + fsl,clk-source =3D /bits/ 8 <0>; + fsl,stop-mode =3D <&gpr 0x10 4>; + status =3D "disabled"; + }; + + flexcan2: can@308d0000 { + compatible =3D "fsl,imx8mp-flexcan"; + reg =3D <0x308d0000 0x10000>; + interrupts =3D ; + clocks =3D <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names =3D "ipg", "per"; + assigned-clocks =3D <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates =3D <40000000>; + fsl,clk-source =3D /bits/ 8 <0>; + fsl,stop-mode =3D <&gpr 0x10 5>; + status =3D "disabled"; + }; }; =20 crypto: crypto@30900000 { --=20 2.34.1