From nobody Sun Apr 12 23:10:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33803C4332F for ; Sun, 18 Dec 2022 05:16:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230284AbiLRFQB (ORCPT ); Sun, 18 Dec 2022 00:16:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230225AbiLRFPl (ORCPT ); Sun, 18 Dec 2022 00:15:41 -0500 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0EA065C3 for ; Sat, 17 Dec 2022 21:15:40 -0800 (PST) Received: by mail-pl1-x629.google.com with SMTP id x2so6043089plb.13 for ; Sat, 17 Dec 2022 21:15:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TArwYxCFrSBrMRpJqgmbgk8qp38LFtviL46odPa8HP0=; b=n0GNyffens8/NKaM1FOU4yqHmtgfe1jSd3RsgG9MqBZ4bhFCl8Qx1XifAXmB8kh5dr ir4ZJBpQjcWXbOHjpA+GWcfjFbxEtA5YNbUFIClPc/pAzRUEc1ejows4Flh7FDBZRjGn oyhY76hXzL3BJwpyjLJNK3sg/kEp+PNxsSee5TJItKcQDTUo7JBlOCnOFbLkSAbP3uJT I5jy/EFuFIs+VrEm0qR0GbvwFE4R+Sfbd5UmuDfnKbQm+4criyedNgrtnnMUkV+/PFLi 3UGnehmrTIF0IGjWvFieIsPhig2MUn0U6izUTJSD+hZYu3KwiUC18vOHJYWgQUyt6hZV tung== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TArwYxCFrSBrMRpJqgmbgk8qp38LFtviL46odPa8HP0=; b=oehZKVnnxvdYp6vvz5HEkNQG3ZbYkuGF6eqAC0uL40zGX8zOSAWUdgDCCjtfHZuq+U PUMjCuoZtrthXmGhR9Mplq7VwmTx0SApjS5r4iRImT2cZqhXvi6GaLr51kqHwwh+bMXu As7jHz3QufOO3ATe2W0HWjqtmGfuS58Vf7KO//VNPZXx9cgxQskqSAX4cSPypjK4IOdf NIZ9awZmkDMet5A6SpK5oWIpK9/AUmbQ5SaPfax0pQxQD7oCUXU0EGyAB3LK3hyUAjgU MNj8l5M1yWo7KtnDgNXWJcZrLvzcLve6HcI1QsFygRs7voLxjXvGEcCbuqNFqzUBdpF1 EvlQ== X-Gm-Message-State: AFqh2koysKdMxvT35NqRmHcW/9eIG+Ts6tVXz0lPDIMQ0Zv84ooJ7yTM jz8noaikgDR2IT5bh3maYZ0QIg== X-Google-Smtp-Source: AMrXdXuNVbYLh7TKzoAhPuPhm0MMGvfsIawvYs2+VupqLnEWB3SzvYdF3oVJnrGFYn4tSZQWIed1ng== X-Received: by 2002:a17:90a:840f:b0:223:aa36:9580 with SMTP id j15-20020a17090a840f00b00223aa369580mr4212952pjn.25.1671340540199; Sat, 17 Dec 2022 21:15:40 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:39 -0800 (PST) From: Akihiko Odaki Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 4/7] KVM: arm64: Always set HCR_TID2 Date: Sun, 18 Dec 2022 14:14:09 +0900 Message-Id: <20221218051412.384657-5-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Always set HCR_TID2 to trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1. This saves a few lines of code and allows to employ their access trap handlers for more purposes anticipated by the old condition for setting HCR_TID2. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/kvm_arm.h | 3 ++- arch/arm64/include/asm/kvm_emulate.h | 4 ---- arch/arm64/include/asm/kvm_host.h | 2 -- arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 -- 4 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 8aa8492dafc0..44be46c280c1 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -81,11 +81,12 @@ * SWIO: Turn set/way invalidates into set/way clean+invalidate * PTW: Take a stage2 fault if a stage1 walk steps in device memory * TID3: Trap EL1 reads of group 3 ID registers + * TID2: Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1 */ #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ HCR_BSU_IS | HCR_FB | HCR_TACR | \ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ - HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 ) + HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 | HCR_TID2) #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 9bdba47f7e14..30c4598d643b 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -88,10 +88,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) if (vcpu_el1_is_32bit(vcpu)) vcpu->arch.hcr_el2 &=3D ~HCR_RW; =20 - if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) || - vcpu_el1_is_32bit(vcpu)) - vcpu->arch.hcr_el2 |=3D HCR_TID2; - if (kvm_has_mte(vcpu->kvm)) vcpu->arch.hcr_el2 |=3D HCR_ATA; } diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 45e2136322ba..cc2ede0eaed4 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -621,7 +621,6 @@ static inline bool __vcpu_read_sys_reg_from_cpu(int reg= , u64 *val) return false; =20 switch (reg) { - case CSSELR_EL1: *val =3D read_sysreg_s(SYS_CSSELR_EL1); break; case SCTLR_EL1: *val =3D read_sysreg_s(SYS_SCTLR_EL12); break; case CPACR_EL1: *val =3D read_sysreg_s(SYS_CPACR_EL12); break; case TTBR0_EL1: *val =3D read_sysreg_s(SYS_TTBR0_EL12); break; @@ -666,7 +665,6 @@ static inline bool __vcpu_write_sys_reg_to_cpu(u64 val,= int reg) return false; =20 switch (reg) { - case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index baa5b9b3dde5..147cb4c846c6 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -39,7 +39,6 @@ static inline bool ctxt_has_mte(struct kvm_cpu_context *c= txt) =20 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { - ctxt_sys_reg(ctxt, CSSELR_EL1) =3D read_sysreg(csselr_el1); ctxt_sys_reg(ctxt, SCTLR_EL1) =3D read_sysreg_el1(SYS_SCTLR); ctxt_sys_reg(ctxt, CPACR_EL1) =3D read_sysreg_el1(SYS_CPACR); ctxt_sys_reg(ctxt, TTBR0_EL1) =3D read_sysreg_el1(SYS_TTBR0); @@ -95,7 +94,6 @@ static inline void __sysreg_restore_user_state(struct kvm= _cpu_context *ctxt) static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2); - write_sysreg(ctxt_sys_reg(ctxt, CSSELR_EL1), csselr_el1); =20 if (has_vhe() || !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { --=20 2.38.1