From nobody Sun Apr 12 21:52:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3C91C4167B for ; Sun, 18 Dec 2022 05:15:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230176AbiLRFPe (ORCPT ); Sun, 18 Dec 2022 00:15:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229641AbiLRFPa (ORCPT ); Sun, 18 Dec 2022 00:15:30 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09D25DED7 for ; Sat, 17 Dec 2022 21:15:29 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id d15so6086017pls.6 for ; Sat, 17 Dec 2022 21:15:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fSSvNarkcX8fxYBT0hcpDCN4tMu56rqMEzf7f5+m+DY=; b=iLqdfLkStRaxHz+T3WwGYnUjZRwjQLDIM6smk/z9ggwXePajQv6m0ooG9QKQ0GWRTA wqdAAu0KvXiBq/eKd+yVFjDuOUwe+wF+VD0VTuWUEasfwUtJtRw5ySEbZg7q74TrfE6u MZTYLlVYskcnskHNAw1baY8qVMmQOP3ZU4bmyuRcOtD2UWIC/3lVpWyYigGECtFjYxAA 4CsfHveHyc6NYMba0olefWZFBbCxIl8BjdNDhdpoPfnEtcH1NOAn96086MnE1pOtjZ+n 89ChjXUU7yurmLWae+JylmBuTNf1ZGfFjVRK1xNYBkoPA4KWHOMd3fZEZ+bYF3tYsQeg y1yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fSSvNarkcX8fxYBT0hcpDCN4tMu56rqMEzf7f5+m+DY=; b=NbmHagDkg6HZWG8+p1imQcvRuc08jBYJeBX5VaTCex9Tonar373BkgDzjjqMnYW5YW aUsaMEsJppkoNYS8NIYxJEKtyPJMYBMNQytS+ixmTnUJZsQ1ptAq3bRuRPBnvwDO7lp0 ijREM/SgZ9E4UDia2yVPEUSr4Rr8tKKHnhC6+jr4cEQiKioR3uTQYXNvvckExCLAiLgl pVH3XNFBcTngZxZ6fhM1AJv4a9KHigm9WzgU7ej+dDyO9YzpbSoRhtxtP9nnST6CjLM9 vF6ha4WBpenTl7ipGBLTctgB7zl3rzr0Ue4OJ///sJi3FUDdA6TRoxbHNHnzQLtVrsB6 MfiQ== X-Gm-Message-State: ANoB5pnn7p07NkokOJC1b2HBS18TEAoXaSalXGpwXhvyZYSM3gme5agc 9LjtBAp5Kp6zDGIziDL6pDEKDA== X-Google-Smtp-Source: AA0mqf7vb6+GyWqLL5OnXKgkL1qGpIo5stbUWTmlKYousX0ZRaRgIzvlA59WnLDwjmcjYLYidZRXJA== X-Received: by 2002:a17:90a:b891:b0:21d:5e73:d562 with SMTP id o17-20020a17090ab89100b0021d5e73d562mr37465528pjr.27.1671340528507; Sat, 17 Dec 2022 21:15:28 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:28 -0800 (PST) From: Akihiko Odaki Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 1/7] arm64/sysreg: Convert CCSIDR_EL1 to automatic generation Date: Sun, 18 Dec 2022 14:14:06 +0900 Message-Id: <20221218051412.384657-2-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert CCSIDR_EL1 to automatic generation as per DDI0487I.a. The field definition is for case when FEAT_CCIDX is not implemented. Fields WT, WB, RA and WA are defined as per A.j since they are now reserved and may have UNKNOWN values in I.a, which the file format cannot represent. Signed-off-by: Akihiko Odaki Reviewed-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/tools/sysreg | 11 +++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 7d301700d1a9..910e960661d3 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -425,7 +425,6 @@ =20 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) =20 -#define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) =20 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 384757a7eda9..acc79b5ccf92 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -871,6 +871,17 @@ Sysreg SCXTNUM_EL1 3 0 13 0 7 Field 63:0 SoftwareContextNumber EndSysreg =20 +Sysreg CCSIDR_EL1 3 1 0 0 0 +Res0 63:32 +Field 31:31 WT +Field 30:30 WB +Field 29:29 RA +Field 28:28 WA +Field 27:13 NumSets +Field 12:3 Associavity +Field 2:0 LineSize +EndSysreg + Sysreg CLIDR_EL1 3 1 0 0 1 Res0 63:47 Field 46:33 Ttypen --=20 2.38.1 From nobody Sun Apr 12 21:52:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0C00C10F1E for ; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CCSIDR2_EL1 was added with FEAT_CCIDX. Signed-off-by: Akihiko Odaki Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index acc79b5ccf92..0a302b4e6d7a 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -898,6 +898,11 @@ Field 5:3 Ctype2 Field 2:0 Ctype1 EndSysreg =20 +Sysreg CCSIDR2_EL1 3 1 0 0 2 +Res0 63:24 +Field 23:0 NumSets +EndSysreg + Sysreg GMID_EL1 3 1 0 0 4 Res0 63:4 Field 3:0 BS --=20 2.38.1 From nobody Sun Apr 12 21:52:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42F7CC10F1E for ; Sun, 18 Dec 2022 05:16:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230214AbiLRFPo (ORCPT ); Sun, 18 Dec 2022 00:15:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230203AbiLRFPi (ORCPT ); Sun, 18 Dec 2022 00:15:38 -0500 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3553DF06 for ; Sat, 17 Dec 2022 21:15:36 -0800 (PST) Received: by mail-pl1-x631.google.com with SMTP id 17so6143929pll.0 for ; Sat, 17 Dec 2022 21:15:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4WsGIW0prujF8xnGwWysGoOLhN4qrtpWJqnT9WJSTvs=; b=20KqTZ7p9hZYfryC+Vfixvt3usjH4QB21HhVNGKbyBUuo9FRcdt5pDtUHZ0C4OB00k Pxkb4TBy4j5Ucx4LvEqYvxz/DBSczM93egGac/fvIai58XcwYxQmzbaOaTH5tfndBTxj JRi/iiyrq7N9LEDYbMOd0d/shMofzgLH7ExucYoWaDUQvs4RFnTKTKgOLHcox3BCkcz/ qlDlCjh4+wKxwbqjTtDSlSaAePBt7ceu4mPvnka+GHbiTPbBdhbiA/SQ5rGpvs+PtiGm YBbNd2hkCWttAqwAgUDSjtnqR+YIhmIQXXDUneGSDReHXU81LIFM9OiZ2/6KYcqPMIQp yPwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4WsGIW0prujF8xnGwWysGoOLhN4qrtpWJqnT9WJSTvs=; b=Roz3Lf/hIZmjAXFlfpeOQ+2f0gc4e4GKraXaZfod0DTbhL+5cJU5xkfXY1ZhmfOdvX rAHEM2fuA58x8XqV1PgZsH7d15tLVYvRFADJhtFbMl3DOY7eQ1+xQd3zgqBl6P342NlU 8/nE23pUCIkW+P77evuFOilXUvJXB3a89VqpLEpfeW+Nz+OOPAhV4B5DR7aYoMxCfd9I XyUeFmNoH2rDoDIDB7EFvZQdJ21Eu2CAafvLvSGNk8Zc0CtsVhCkWgasQA3UN5DVWksr wiJT5UBkB+P7xMy0mWUGO8ysBd7mdKHz9szc5IW3sumxhJsIoncXk9AXXorSn+t1tgvx jcXA== X-Gm-Message-State: AFqh2kpHGaO65w7WpeOA/05jZFFaq+5oJrbTLNpPxan3enbyd4eZ6q1B ekdcK3vI8rmGKJDJGSrFSIF0Lw== X-Google-Smtp-Source: AMrXdXtRnhfNE+X0n0H526OoGg60rNUh3zsQ7HI3r0L3dVAMmDfmA+k1y46jlVAC89lTx/mkAJPjBw== X-Received: by 2002:a17:90a:2eca:b0:223:b920:28df with SMTP id h10-20020a17090a2eca00b00223b92028dfmr1736781pjs.29.1671340536313; Sat, 17 Dec 2022 21:15:36 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:35 -0800 (PST) From: Akihiko Odaki Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 3/7] arm64/cache: Move CLIDR macro definitions Date: Sun, 18 Dec 2022 14:14:08 +0900 Message-Id: <20221218051412.384657-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The macros are useful for KVM which needs to manage how CLIDR is exposed to vcpu so move them to include/asm/cache.h, which KVM can refer to. Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/cache.h | 6 ++++++ arch/arm64/kernel/cacheinfo.c | 5 ----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index c0b178d1bb4f..ab7133654a72 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -16,6 +16,12 @@ #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) =20 +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n =3D 1 to 7 */ +#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) +#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) +#define CLIDR_CTYPE(clidr, level) \ + (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) + /* * Memory returned by kmalloc() may be used for DMA, so we must make * sure that all such allocations are cache aligned. Otherwise, diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 97c42be71338..daa7b3f55997 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -11,11 +11,6 @@ #include =20 #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ -/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n =3D 1 to 7 */ -#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) -#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) -#define CLIDR_CTYPE(clidr, level) \ - (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) =20 int cache_line_size(void) { --=20 2.38.1 From nobody Sun Apr 12 21:52:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33803C4332F for ; Sun, 18 Dec 2022 05:16:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230284AbiLRFQB (ORCPT ); Sun, 18 Dec 2022 00:16:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230225AbiLRFPl (ORCPT ); Sun, 18 Dec 2022 00:15:41 -0500 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0EA065C3 for ; Sat, 17 Dec 2022 21:15:40 -0800 (PST) Received: by mail-pl1-x629.google.com with SMTP id x2so6043089plb.13 for ; Sat, 17 Dec 2022 21:15:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TArwYxCFrSBrMRpJqgmbgk8qp38LFtviL46odPa8HP0=; b=n0GNyffens8/NKaM1FOU4yqHmtgfe1jSd3RsgG9MqBZ4bhFCl8Qx1XifAXmB8kh5dr ir4ZJBpQjcWXbOHjpA+GWcfjFbxEtA5YNbUFIClPc/pAzRUEc1ejows4Flh7FDBZRjGn oyhY76hXzL3BJwpyjLJNK3sg/kEp+PNxsSee5TJItKcQDTUo7JBlOCnOFbLkSAbP3uJT I5jy/EFuFIs+VrEm0qR0GbvwFE4R+Sfbd5UmuDfnKbQm+4criyedNgrtnnMUkV+/PFLi 3UGnehmrTIF0IGjWvFieIsPhig2MUn0U6izUTJSD+hZYu3KwiUC18vOHJYWgQUyt6hZV tung== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TArwYxCFrSBrMRpJqgmbgk8qp38LFtviL46odPa8HP0=; b=oehZKVnnxvdYp6vvz5HEkNQG3ZbYkuGF6eqAC0uL40zGX8zOSAWUdgDCCjtfHZuq+U PUMjCuoZtrthXmGhR9Mplq7VwmTx0SApjS5r4iRImT2cZqhXvi6GaLr51kqHwwh+bMXu As7jHz3QufOO3ATe2W0HWjqtmGfuS58Vf7KO//VNPZXx9cgxQskqSAX4cSPypjK4IOdf NIZ9awZmkDMet5A6SpK5oWIpK9/AUmbQ5SaPfax0pQxQD7oCUXU0EGyAB3LK3hyUAjgU MNj8l5M1yWo7KtnDgNXWJcZrLvzcLve6HcI1QsFygRs7voLxjXvGEcCbuqNFqzUBdpF1 EvlQ== X-Gm-Message-State: AFqh2koysKdMxvT35NqRmHcW/9eIG+Ts6tVXz0lPDIMQ0Zv84ooJ7yTM jz8noaikgDR2IT5bh3maYZ0QIg== X-Google-Smtp-Source: AMrXdXuNVbYLh7TKzoAhPuPhm0MMGvfsIawvYs2+VupqLnEWB3SzvYdF3oVJnrGFYn4tSZQWIed1ng== X-Received: by 2002:a17:90a:840f:b0:223:aa36:9580 with SMTP id j15-20020a17090a840f00b00223aa369580mr4212952pjn.25.1671340540199; Sat, 17 Dec 2022 21:15:40 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:39 -0800 (PST) From: Akihiko Odaki Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 4/7] KVM: arm64: Always set HCR_TID2 Date: Sun, 18 Dec 2022 14:14:09 +0900 Message-Id: <20221218051412.384657-5-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Always set HCR_TID2 to trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1. This saves a few lines of code and allows to employ their access trap handlers for more purposes anticipated by the old condition for setting HCR_TID2. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/kvm_arm.h | 3 ++- arch/arm64/include/asm/kvm_emulate.h | 4 ---- arch/arm64/include/asm/kvm_host.h | 2 -- arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 2 -- 4 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_= arm.h index 8aa8492dafc0..44be46c280c1 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -81,11 +81,12 @@ * SWIO: Turn set/way invalidates into set/way clean+invalidate * PTW: Take a stage2 fault if a stage1 walk steps in device memory * TID3: Trap EL1 reads of group 3 ID registers + * TID2: Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1 */ #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ HCR_BSU_IS | HCR_FB | HCR_TACR | \ HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ - HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 ) + HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 | HCR_TID2) #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 9bdba47f7e14..30c4598d643b 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -88,10 +88,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) if (vcpu_el1_is_32bit(vcpu)) vcpu->arch.hcr_el2 &=3D ~HCR_RW; =20 - if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) || - vcpu_el1_is_32bit(vcpu)) - vcpu->arch.hcr_el2 |=3D HCR_TID2; - if (kvm_has_mte(vcpu->kvm)) vcpu->arch.hcr_el2 |=3D HCR_ATA; } diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 45e2136322ba..cc2ede0eaed4 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -621,7 +621,6 @@ static inline bool __vcpu_read_sys_reg_from_cpu(int reg= , u64 *val) return false; =20 switch (reg) { - case CSSELR_EL1: *val =3D read_sysreg_s(SYS_CSSELR_EL1); break; case SCTLR_EL1: *val =3D read_sysreg_s(SYS_SCTLR_EL12); break; case CPACR_EL1: *val =3D read_sysreg_s(SYS_CPACR_EL12); break; case TTBR0_EL1: *val =3D read_sysreg_s(SYS_TTBR0_EL12); break; @@ -666,7 +665,6 @@ static inline bool __vcpu_write_sys_reg_to_cpu(u64 val,= int reg) return false; =20 switch (reg) { - case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index baa5b9b3dde5..147cb4c846c6 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -39,7 +39,6 @@ static inline bool ctxt_has_mte(struct kvm_cpu_context *c= txt) =20 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { - ctxt_sys_reg(ctxt, CSSELR_EL1) =3D read_sysreg(csselr_el1); ctxt_sys_reg(ctxt, SCTLR_EL1) =3D read_sysreg_el1(SYS_SCTLR); ctxt_sys_reg(ctxt, CPACR_EL1) =3D read_sysreg_el1(SYS_CPACR); ctxt_sys_reg(ctxt, TTBR0_EL1) =3D read_sysreg_el1(SYS_TTBR0); @@ -95,7 +94,6 @@ static inline void __sysreg_restore_user_state(struct kvm= _cpu_context *ctxt) static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2); - write_sysreg(ctxt_sys_reg(ctxt, CSSELR_EL1), csselr_el1); =20 if (has_vhe() || !cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { --=20 2.38.1 From nobody Sun Apr 12 21:52:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF4C5C4332F for ; Sun, 18 Dec 2022 05:16:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230258AbiLRFQQ (ORCPT ); Sun, 18 Dec 2022 00:16:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230249AbiLRFPz (ORCPT ); Sun, 18 Dec 2022 00:15:55 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07DF2DC0 for ; Sat, 17 Dec 2022 21:15:44 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id d7so6067496pll.9 for ; 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Sat, 17 Dec 2022 21:15:44 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:43 -0800 (PST) From: Akihiko Odaki Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 5/7] KVM: arm64: Allow user to set CCSIDR_EL1 Date: Sun, 18 Dec 2022 14:14:10 +0900 Message-Id: <20221218051412.384657-6-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allow the userspace to set CCSIDR_EL1 so that if the kernel changes the default values of CCSIDR_EL1, the userspace can restore the old values from an old saved VM context. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/kvm_host.h | 3 + arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/sys_regs.c | 116 ++++++++++++++++++++---------- 3 files changed, 83 insertions(+), 37 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index cc2ede0eaed4..cfc6930efe1b 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -417,6 +417,9 @@ struct kvm_vcpu_arch { u64 last_steal; gpa_t base; } steal; + + /* Per-vcpu CCSIDR override or NULL */ + u32 *ccsidr; }; =20 /* diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 5ae18472205a..7980983dbad7 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -157,6 +157,7 @@ void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) if (sve_state) kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu)); kfree(sve_state); + kfree(vcpu->arch.ccsidr); } =20 static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f4a7c5abcbca..f48a3cc38d24 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -87,11 +87,27 @@ static u32 cache_levels; /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ #define CSSELR_MAX 14 =20 +static u8 get_min_cache_line_size(u32 csselr) +{ + u64 ctr_el0; + int field; + + ctr_el0 =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + field =3D csselr & CSSELR_EL1_InD ? CTR_EL0_IminLine_SHIFT : CTR_EL0_Dmin= Line_SHIFT; + + return cpuid_feature_extract_unsigned_field(ctr_el0, field) - 2; +} + /* Which cache CCSIDR represents depends on CSSELR value. */ -static u32 get_ccsidr(u32 csselr) +static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) { + u32 ccsidr_index =3D csselr & (CSSELR_EL1_Level | CSSELR_EL1_InD); u32 ccsidr; =20 + if (vcpu->arch.ccsidr && is_valid_cache(ccsidr_index) && + !(kvm_has_mte(vcpu->kvm) && (csselr & CSSELR_EL1_TnD))) + return vcpu->arch.ccsidr[ccsidr_index]; + /* Make sure noone else changes CSSELR during this! */ local_irq_disable(); write_sysreg(csselr, csselr_el1); @@ -102,6 +118,61 @@ static u32 get_ccsidr(u32 csselr) return ccsidr; } =20 +static bool is_valid_cache(u32 val) +{ + u32 level, ctype; + + if (val >=3D CSSELR_MAX) + return false; + + /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ + level =3D (val >> 1); + ctype =3D (cache_levels >> (level * 3)) & 7; + + switch (ctype) { + case 0: /* No cache */ + return false; + case 1: /* Instruction cache only */ + return (val & 1); + case 2: /* Data cache only */ + case 4: /* Unified cache */ + return !(val & 1); + case 3: /* Separate instruction and data caches */ + return true; + default: /* Reserved: we can't know instruction or data. */ + return false; + } +} + +static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) +{ + u8 line_size =3D (val & CCSIDR_EL1_LineSize) >> CCSIDR_EL1_LineSize_SHIFT; + u32 *ccsidr =3D vcpu->arch.ccsidr; + u32 i; + + if ((val & CCSIDR_EL1_RES0) || line_size < get_min_cache_line_size(csselr= )) + return -EINVAL; + + if (!ccsidr) { + if (val =3D=3D get_ccsidr(vcpu, csselr)) + return 0; + + ccsidr =3D kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL); + if (!ccsidr) + return -ENOMEM; + + for (i =3D 0; i < CSSELR_MAX; i++) + if (is_valid_cache(i)) + ccsidr[i] =3D get_ccsidr(vcpu, i); + + vcpu->arch.ccsidr =3D ccsidr; + } + + ccsidr[csselr] =3D val; + + return 0; +} + /* * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualize= d). */ @@ -1300,7 +1371,7 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, stru= ct sys_reg_params *p, return write_to_read_only(vcpu, p, r); =20 csselr =3D vcpu_read_sys_reg(vcpu, CSSELR_EL1); - p->regval =3D get_ccsidr(csselr); + p->regval =3D get_ccsidr(vcpu, csselr); =20 /* * Guests should not be doing cache operations by set/way at all, and @@ -2660,33 +2731,7 @@ static int set_invariant_sys_reg(u64 id, u64 __user = *uaddr) return 0; } =20 -static bool is_valid_cache(u32 val) -{ - u32 level, ctype; - - if (val >=3D CSSELR_MAX) - return false; - - /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ - level =3D (val >> 1); - ctype =3D (cache_levels >> (level * 3)) & 7; - - switch (ctype) { - case 0: /* No cache */ - return false; - case 1: /* Instruction cache only */ - return (val & 1); - case 2: /* Data cache only */ - case 4: /* Unified cache */ - return !(val & 1); - case 3: /* Separate instruction and data caches */ - return true; - default: /* Reserved: we can't know instruction or data. */ - return false; - } -} - -static int demux_c15_get(u64 id, void __user *uaddr) +static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) { u32 val; u32 __user *uval =3D uaddr; @@ -2705,13 +2750,13 @@ static int demux_c15_get(u64 id, void __user *uaddr) if (!is_valid_cache(val)) return -ENOENT; =20 - return put_user(get_ccsidr(val), uval); + return put_user(get_ccsidr(vcpu, val), uval); default: return -ENOENT; } } =20 -static int demux_c15_set(u64 id, void __user *uaddr) +static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr) { u32 val, newval; u32 __user *uval =3D uaddr; @@ -2733,10 +2778,7 @@ static int demux_c15_set(u64 id, void __user *uaddr) if (get_user(newval, uval)) return -EFAULT; =20 - /* This is also invariant: you can't change it. */ - if (newval !=3D get_ccsidr(val)) - return -EINVAL; - return 0; + return set_ccsidr(vcpu, val, newval); default: return -ENOENT; } @@ -2773,7 +2815,7 @@ int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, co= nst struct kvm_one_reg *reg int err; =20 if ((reg->id & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_DEMUX) - return demux_c15_get(reg->id, uaddr); + return demux_c15_get(vcpu, reg->id, uaddr); =20 err =3D get_invariant_sys_reg(reg->id, uaddr); if (err !=3D -ENOENT) @@ -2817,7 +2859,7 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, co= nst struct kvm_one_reg *reg int err; =20 if ((reg->id & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_DEMUX) - return demux_c15_set(reg->id, uaddr); + return demux_c15_set(vcpu, reg->id, uaddr); =20 err =3D set_invariant_sys_reg(reg->id, uaddr); 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Sat, 17 Dec 2022 21:15:48 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:47 -0800 (PST) From: Akihiko Odaki Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 6/7] KVM: arm64: Mask FEAT_CCIDX Date: Sun, 18 Dec 2022 14:14:11 +0900 Message-Id: <20221218051412.384657-7-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The CCSIDR access handler masks the associativity bits according to the bit layout for processors without FEAT_CCIDX. KVM also assumes CCSIDR is 32-bit where it will be 64-bit if FEAT_CCIDX is enabled. Mask FEAT_CCIDX so that these assumptions hold. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/sys_regs.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f48a3cc38d24..a7199f34e321 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1195,6 +1195,12 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, = struct sys_reg_desc const *r ID_DFR0_PERFMON_SHIFT, kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); break; + case SYS_ID_AA64MMFR2_EL1: + val &=3D ~ID_AA64MMFR2_EL1_CCIDX_MASK; + break; + case SYS_ID_MMFR4_EL1: + val &=3D ~ARM64_FEATURE_MASK(ID_MMFR4_CCIDX); + break; } =20 return val; @@ -1676,6 +1682,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { =20 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, + { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, { SYS_DESC(SYS_CTR_EL0), access_ctr }, @@ -2177,6 +2184,10 @@ static const struct sys_reg_desc cp15_regs[] =3D { =20 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, + + /* CCSIDR2 */ + { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access }, + { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 }, }; =20 --=20 2.38.1 From nobody Sun Apr 12 21:52:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1996C4332F for ; Sun, 18 Dec 2022 05:16:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230420AbiLRFQr (ORCPT ); Sun, 18 Dec 2022 00:16:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230355AbiLRFQO (ORCPT ); Sun, 18 Dec 2022 00:16:14 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FF772DF9 for ; Sat, 17 Dec 2022 21:15:52 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id z8-20020a17090abd8800b00219ed30ce47so9950217pjr.3 for ; Sat, 17 Dec 2022 21:15:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IJmzgqWbYjXHayt1fVUjbpZdSQg9mlJmebSHfVtOk/w=; b=slrgCkBu4hD5xxrdTty9DB5h0GOnqA6WFBWTs+nuJEmU57fuUCTwWCunetECMIaccs Bvq1JsRDiqX/GAki+Hyvv4/xotRwAKB7Ldb3nL9TT5S9gRI620O+s7OH1gnJUGr3z5dG 1jGY8MpaLCm/x6f52w+ze4oJFZVT6dfqYbTWnO05Li6GrtBVrCCow+A2tXae5yhCxMl1 ybOwwhNTrsq1szvHo7kagpV+MtIvULI8qMf+wLU1zBLe6FlJb/HfxU1e01jyr5AMiBEs cfz04wmEfOjiUXByOIRHAC26OaZJlQzfrZfLT+ZmrA428iX96jPS1h8mMX15uALgbUa2 xV3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IJmzgqWbYjXHayt1fVUjbpZdSQg9mlJmebSHfVtOk/w=; b=dnDy/lCexJYA01lc86mqYHbUJ9+ktEAFVFi0oQ/2dnckaVgNUkZJIULcVa5rqbUF2J 3em0EF4Y+ZsSaPWEhSkuiUPohT2zpKgglDjzFxfESVdKQARYyd6b5yd+usrgHTKnKBAk nAOrOuCDGycLk5vfivJ5Ww3eXtMbGdB/jPGlasOJEJHXyFPhpJn9c3JdO8t3oefKWX06 u6J+sewFWUyr2C2gfnzFUpGwtTES81wpXrZCNMXWhxAncVvCKsfMjlApCTzVbE1MLINu 3rpfH0IH5DEp8paZej88nB3CJ853pCRBcHuzU+p0JL6xvXpxBHxgBHjVMsfQoEm7uEAJ D+Bw== X-Gm-Message-State: ANoB5pluQr/bmiPnSmQBNFrPQ0cpJYLf5MFgFImzQlFkDI5j1m74n9n8 EibHOvUGBUyoI4Mr/Y21wkpiMQ== X-Google-Smtp-Source: AA0mqf4E49x4lUAbvX6a61HO3fXfHcqIeoGOvrf+PT79bhPCUz7EMHic4yOOVOM2Of91ArtZ1uqEPA== X-Received: by 2002:a17:90a:ac07:b0:219:aa58:77ba with SMTP id o7-20020a17090aac0700b00219aa5877bamr39470299pjq.25.1671340551960; Sat, 17 Dec 2022 21:15:51 -0800 (PST) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id b1-20020a17090a6ac100b002139459e121sm7002417pjm.27.2022.12.17.21.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Dec 2022 21:15:51 -0800 (PST) From: Akihiko Odaki Cc: Marc Zyngier , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Mathieu Poirier , Oliver Upton , Suzuki K Poulose , Alexandru Elisei , James Morse , Will Deacon , Catalin Marinas , asahi@lists.linux.dev, Alyssa Rosenzweig , Sven Peter , Hector Martin , Akihiko Odaki Subject: [PATCH v3 7/7] KVM: arm64: Normalize cache configuration Date: Sun, 18 Dec 2022 14:14:12 +0900 Message-Id: <20221218051412.384657-8-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221218051412.384657-1-akihiko.odaki@daynix.com> References: <20221218051412.384657-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Before this change, the cache configuration of the physical CPU was exposed to vcpus. This is problematic because the cache configuration a vcpu sees varies when it migrates between vcpus with different cache configurations. Fabricate cache configuration from the sanitized value, which holds the CTR_EL0 value the userspace sees regardless of which physical CPU it resides on. CLIDR_EL1 is now writable from the userspace so that the VMM can restore the values saved with the old kernel. Suggested-by: Marc Zyngier Signed-off-by: Akihiko Odaki --- arch/arm64/include/asm/cache.h | 3 + arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/sys_regs.c | 183 +++++++++++++++--------------- 3 files changed, 96 insertions(+), 91 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index ab7133654a72..a51e6e8f3171 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -22,6 +22,9 @@ #define CLIDR_CTYPE(clidr, level) \ (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) =20 +/* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n =3D 1 to 7 */ +#define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHI= FT) + /* * Memory returned by kmalloc() may be used for DMA, so we must make * sure that all such allocations are cache aligned. Otherwise, diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index cfc6930efe1b..27abf81c6910 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -178,6 +178,7 @@ struct kvm_vcpu_fault_info { enum vcpu_sysreg { __INVALID_SYSREG__, /* 0 is reserved as an invalid value */ MPIDR_EL1, /* MultiProcessor Affinity Register */ + CLIDR_EL1, /* Cache Level ID Register */ CSSELR_EL1, /* Cache Size Selection Register */ SCTLR_EL1, /* System Control Register */ ACTLR_EL1, /* Auxiliary Control Register */ diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a7199f34e321..9fd0b28e29bd 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -11,6 +11,7 @@ =20 #include #include +#include #include #include #include @@ -81,9 +82,6 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, i= nt reg) __vcpu_sys_reg(vcpu, reg) =3D val; } =20 -/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 = */ -static u32 cache_levels; - /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ #define CSSELR_MAX 14 =20 @@ -101,47 +99,36 @@ static u8 get_min_cache_line_size(u32 csselr) /* Which cache CCSIDR represents depends on CSSELR value. */ static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr) { - u32 ccsidr_index =3D csselr & (CSSELR_EL1_Level | CSSELR_EL1_InD); - u32 ccsidr; - - if (vcpu->arch.ccsidr && is_valid_cache(ccsidr_index) && - !(kvm_has_mte(vcpu->kvm) && (csselr & CSSELR_EL1_TnD))) - return vcpu->arch.ccsidr[ccsidr_index]; - - /* Make sure noone else changes CSSELR during this! */ - local_irq_disable(); - write_sysreg(csselr, csselr_el1); - isb(); - ccsidr =3D read_sysreg(ccsidr_el1); - local_irq_enable(); - - return ccsidr; -} - -static bool is_valid_cache(u32 val) -{ - u32 level, ctype; + u64 ctr_el0; + int field; =20 - if (val >=3D CSSELR_MAX) - return false; + if (vcpu->arch.ccsidr) + return vcpu->arch.ccsidr[csselr]; =20 - /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ - level =3D (val >> 1); - ctype =3D (cache_levels >> (level * 3)) & 7; + ctr_el0 =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + field =3D csselr & CSSELR_EL1_InD ? CTR_EL0_IminLine_SHIFT : CTR_EL0_Dmin= Line_SHIFT; =20 - switch (ctype) { - case 0: /* No cache */ - return false; - case 1: /* Instruction cache only */ - return (val & 1); - case 2: /* Data cache only */ - case 4: /* Unified cache */ - return !(val & 1); - case 3: /* Separate instruction and data caches */ - return true; - default: /* Reserved: we can't know instruction or data. */ - return false; - } + /* + * Fabricate a CCSIDR value as the overriding value does not exist. + * The real CCSIDR value will not be used as it can vary by the + * physical CPU which the vcpu currently resides in. + * + * The line size is determined with arm64_ftr_reg_ctrel0.sys_val, which + * should be valid for all CPUs even if they have different cache + * configuration. + * + * The associativity bits are cleared, meaning the geometry of all data + * and unified caches (which are guaranteed to be PIPT and thus + * non-aliasing) are 1 set and 1 way. + * Guests should not be doing cache operations by set/way at all, and + * for this reason, we trap them and attempt to infer the intent, so + * that we can flush the entire guest's address space at the appropriate + * time. The exposed geometry minimizes the number of the traps. + * [If guests should attempt to infer aliasing properties from the + * geometry (which is not permitted by the architecture), they would + * only do so for virtually indexed caches.] + */ + return get_min_cache_line_size(csselr) << CCSIDR_EL1_LineSize_SHIFT; } =20 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val) @@ -162,8 +149,7 @@ static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr= , u32 val) return -ENOMEM; =20 for (i =3D 0; i < CSSELR_MAX; i++) - if (is_valid_cache(i)) - ccsidr[i] =3D get_ccsidr(vcpu, i); + ccsidr[i] =3D get_ccsidr(vcpu, i); =20 vcpu->arch.ccsidr =3D ccsidr; } @@ -1352,10 +1338,64 @@ static bool access_clidr(struct kvm_vcpu *vcpu, str= uct sys_reg_params *p, if (p->is_write) return write_to_read_only(vcpu, p, r); =20 - p->regval =3D read_sysreg(clidr_el1); + p->regval =3D __vcpu_sys_reg(vcpu, r->reg); return true; } =20 +/* + * Fabricate a CLIDR_EL1 value instead of using the real value, which can = vary + * by the physical CPU which the vcpu currently resides in. + */ +static void reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *= r) +{ + u64 ctr_el0 =3D read_sanitised_ftr_reg(SYS_CTR_EL0); + u64 clidr; + u8 loc; + + if ((ctr_el0 & CTR_EL0_IDC) || cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))= { + /* + * Data cache clean to the PoU is not required so LoUU and LoUIS + * will not be set and a unified cache, which will be marked as + * LoC, will be added. + * + * If not DIC, let the unified cache L2 so that an instruction + * cache can be added as L1 later. + */ + loc =3D (ctr_el0 & CTR_EL0_DIC) ? 1 : 2; + clidr =3D CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); + } else { + /* + * Data cache clean to the PoU is required so let L1 have a data + * cache and mark it as LoUU and LoUIS. As L1 has a data cache, + * it can be marked as LoC too. + */ + loc =3D 1; + clidr =3D 1 << CLIDR_LOUU_SHIFT; + clidr |=3D 1 << CLIDR_LOUIS_SHIFT; + clidr |=3D CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); + } + + /* + * Instruction cache invalidation to the PoU is required so let L1 have + * an instruction cache. If L1 already has a data cache, it will be + * CACHE_TYPE_SEPARATE. + */ + if (!(ctr_el0 & CTR_EL0_DIC)) + clidr |=3D CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); + + clidr |=3D loc << CLIDR_LOC_SHIFT; + + /* + * Add tag cache unified to data cache. Allocation tags and data are + * unified in a cache line so that it looks valid even if there is only + * one cache line. + */ + if (kvm_has_mte(vcpu->kvm)) + clidr |=3D 2 << CLIDR_TTYPE_SHIFT(loc); + + __vcpu_sys_reg(vcpu, r->reg) =3D clidr; +} + static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { @@ -1377,22 +1417,12 @@ static bool access_ccsidr(struct kvm_vcpu *vcpu, st= ruct sys_reg_params *p, return write_to_read_only(vcpu, p, r); =20 csselr =3D vcpu_read_sys_reg(vcpu, CSSELR_EL1); + csselr &=3D CSSELR_EL1_Level | CSSELR_EL1_InD; + if (csselr >=3D CSSELR_MAX) + return undef_access(vcpu, p, r); + p->regval =3D get_ccsidr(vcpu, csselr); =20 - /* - * Guests should not be doing cache operations by set/way at all, and - * for this reason, we trap them and attempt to infer the intent, so - * that we can flush the entire guest's address space at the appropriate - * time. - * To prevent this trapping from causing performance problems, let's - * expose the geometry of all data and unified caches (which are - * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. - * [If guests should attempt to infer aliasing properties from the - * geometry (which is not permitted by the architecture), they would - * only do so for virtually indexed caches.] - */ - if (!(csselr & 1)) // data or unified cache - p->regval &=3D ~GENMASK(27, 3); return true; } =20 @@ -1681,7 +1711,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, =20 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, - { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, + { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1 }, { SYS_DESC(SYS_CCSIDR2_EL1), undef_access }, { SYS_DESC(SYS_SMIDR_EL1), undef_access }, { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, @@ -2693,7 +2723,6 @@ id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id, =20 FUNCTION_INVARIANT(midr_el1) FUNCTION_INVARIANT(revidr_el1) -FUNCTION_INVARIANT(clidr_el1) FUNCTION_INVARIANT(aidr_el1) =20 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) @@ -2705,7 +2734,6 @@ static void get_ctr_el0(struct kvm_vcpu *v, const str= uct sys_reg_desc *r) static struct sys_reg_desc invariant_sys_regs[] =3D { { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, - { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, }; @@ -2758,7 +2786,7 @@ static int demux_c15_get(struct kvm_vcpu *vcpu, u64 i= d, void __user *uaddr) return -ENOENT; val =3D (id & KVM_REG_ARM_DEMUX_VAL_MASK) >> KVM_REG_ARM_DEMUX_VAL_SHIFT; - if (!is_valid_cache(val)) + if (val >=3D CSSELR_MAX) return -ENOENT; =20 return put_user(get_ccsidr(vcpu, val), uval); @@ -2783,7 +2811,7 @@ static int demux_c15_set(struct kvm_vcpu *vcpu, u64 i= d, void __user *uaddr) return -ENOENT; val =3D (id & KVM_REG_ARM_DEMUX_VAL_MASK) >> KVM_REG_ARM_DEMUX_VAL_SHIFT; - if (!is_valid_cache(val)) + if (val >=3D CSSELR_MAX) return -ENOENT; =20 if (get_user(newval, uval)) @@ -2882,13 +2910,7 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, c= onst struct kvm_one_reg *reg =20 static unsigned int num_demux_regs(void) { - unsigned int i, count =3D 0; - - for (i =3D 0; i < CSSELR_MAX; i++) - if (is_valid_cache(i)) - count++; - - return count; + return CSSELR_MAX; } =20 static int write_demux_regids(u64 __user *uindices) @@ -2898,8 +2920,6 @@ static int write_demux_regids(u64 __user *uindices) =20 val |=3D KVM_REG_ARM_DEMUX_ID_CCSIDR; for (i =3D 0; i < CSSELR_MAX; i++) { - if (!is_valid_cache(i)) - continue; if (put_user(val | i, uindices)) return -EFAULT; uindices++; @@ -3001,7 +3021,6 @@ int kvm_sys_reg_table_init(void) { bool valid =3D true; unsigned int i; - struct sys_reg_desc clidr; =20 /* Make sure tables are unique and in order. */ valid &=3D check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), f= alse); @@ -3018,23 +3037,5 @@ int kvm_sys_reg_table_init(void) for (i =3D 0; i < ARRAY_SIZE(invariant_sys_regs); i++) invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); =20 - /* - * CLIDR format is awkward, so clean it up. See ARM B4.1.20: - * - * If software reads the Cache Type fields from Ctype1 - * upwards, once it has seen a value of 0b000, no caches - * exist at further-out levels of the hierarchy. So, for - * example, if Ctype3 is the first Cache Type field with a - * value of 0b000, the values of Ctype4 to Ctype7 must be - * ignored. - */ - get_clidr_el1(NULL, &clidr); /* Ugly... */ - cache_levels =3D clidr.val; - for (i =3D 0; i < 7; i++) - if (((cache_levels >> (i*3)) & 7) =3D=3D 0) - break; - /* Clear all higher bits. */ - cache_levels &=3D (1 << (i*3))-1; - return 0; } --=20 2.38.1