From nobody Mon Apr 13 00:42:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A78ADC25B04 for ; Thu, 15 Dec 2022 17:02:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230435AbiLORCZ (ORCPT ); Thu, 15 Dec 2022 12:02:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230411AbiLORBa (ORCPT ); Thu, 15 Dec 2022 12:01:30 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4DAE27144 for ; Thu, 15 Dec 2022 09:01:19 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id e7-20020a17090a77c700b00216928a3917so3334078pjs.4 for ; Thu, 15 Dec 2022 09:01:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dhs+JrFmy876qsXRL5CBd5BerbPW3etQeVs8SpsZcQw=; b=U6oNR8T4Jsx3E3L822kTsxHd5TEGEsxBn3CCUI2SeekPDUkSTGJ3fOb7abTtiH2h4F LFLmL/RlSDx5Gy7NL57xvVYxQFVz3At/fTJ5lhTAnbcZtYlPv3YqbA8/oF0LW4z1rrLd 2NzR+yITnwiEjMORqQ9wRHog+vOR75SHj03EJOOROKOWaE3zKorgx1eElPSSsd7BZpML t3+2flYfKJ2PRenAgW4s3fOk2QnyIDjhXZ8B7xxbGaydBqH/Z9PJlSz91Pj30V5kediS avY61zS5vHm0YooUmCNwe++UdZaFGHKwFMLtTH+sp3nepkSe07opJjxQVAJJko1VQZXp Vjig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dhs+JrFmy876qsXRL5CBd5BerbPW3etQeVs8SpsZcQw=; b=UD/qPt/YJcOUvC/ozyG5jUqtR30wAsJLfznOSoI8A4vV8mEGMKAFVrrCCcRsE/9kfS FSgfGDJ2UL7p0HB+F6wipjkKu8TWOrKegpEhf+WozbGRoMxCXiVXIqOUF1LtxUV0ZzxI AzRGL3yu8GDibnOXeMyhcCo0HwLLOhd4jTW5YZYfeT+G5AlyC4NScxGYLIq6YqXBlmjD C8OR5Yp/iNyq52qEWd7PxSAmZwxHkcgJniKyfq3+CSVIuHcMb2EsYXQvo+FoejlIYGZj Eez1P43UNgmwpTj0Ajl7WWdV2QklHI+KIc7oIKhoCIoZ+H9IzYO+/KplTP0xexXrEBFZ NSZw== X-Gm-Message-State: ANoB5pmdBBYMRnG8PoeiGD8CWF399IJH+eYHH2U/R8LIalWHPDbRLiA+ 6A3MzOKuDDANVObCiNv7cSisrVePqqnkk/sI X-Google-Smtp-Source: AA0mqf5DHC3LSXbUYgba/exs/9GOB/5X0REqYDp696TBPWA4irASk74J17kx3gV/3kuJxQkkUN+9Gw== X-Received: by 2002:a17:902:8b81:b0:185:441e:2d78 with SMTP id ay1-20020a1709028b8100b00185441e2d78mr27030692plb.15.1671123678696; Thu, 15 Dec 2022 09:01:18 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id p10-20020a170902780a00b001897bfc9800sm4067449pll.53.2022.12.15.09.01.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 09:01:18 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Andrew Jones , Atish Patra , Guo Ren , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Eric Lin , Will Deacon Subject: [PATCH v2 06/11] RISC-V: KVM: Add skeleton support for perf Date: Thu, 15 Dec 2022 09:00:41 -0800 Message-Id: <20221215170046.2010255-7-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215170046.2010255-1-atishp@rivosinc.com> References: <20221215170046.2010255-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch only adds barebore structure of perf implementation. Most of the function returns zero at this point and will be implemented fully in the future. Signed-off-by: Atish Patra --- arch/riscv/include/asm/kvm_host.h | 3 + arch/riscv/include/asm/kvm_vcpu_pmu.h | 76 ++++++++++++++ arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 5 + arch/riscv/kvm/vcpu_insn.c | 2 +- arch/riscv/kvm/vcpu_pmu.c | 142 ++++++++++++++++++++++++++ 6 files changed, 228 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/kvm_vcpu_pmu.h create mode 100644 arch/riscv/kvm/vcpu_pmu.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 93f43a3..f9874b4 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -18,6 +18,7 @@ #include #include #include +#include =20 #define KVM_MAX_VCPUS 1024 =20 @@ -228,6 +229,8 @@ struct kvm_vcpu_arch { =20 /* Don't run the VCPU (blocked) */ bool pause; + + struct kvm_pmu pmu; }; =20 static inline void kvm_arch_hardware_unsetup(void) {} diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm= /kvm_vcpu_pmu.h new file mode 100644 index 0000000..6a8c0f7 --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Rivos Inc + * + * Authors: + * Atish Patra + */ + +#ifndef __KVM_VCPU_RISCV_PMU_H +#define __KVM_VCPU_RISCV_PMU_H + +#include +#include +#include + +#ifdef CONFIG_RISCV_PMU_SBI +#define RISCV_KVM_MAX_FW_CTRS 32 +#define RISCV_MAX_COUNTERS 64 + +/* Per virtual pmu counter data */ +struct kvm_pmc { + u8 idx; + struct perf_event *perf_event; + uint64_t counter_val; + union sbi_pmu_ctr_info cinfo; + /* Event monitoring status */ + bool started; +}; + +/* PMU data structure per vcpu */ +struct kvm_pmu { + struct kvm_pmc pmc[RISCV_MAX_COUNTERS]; + /* Number of the virtual firmware counters available */ + int num_fw_ctrs; + /* Number of the virtual hardware counters available */ + int num_hw_ctrs; + /* A flag to indicate that pmu initialization is done */ + bool init_done; + /* Bit map of all the virtual counter used */ + DECLARE_BITMAP(pmc_in_use, RISCV_MAX_COUNTERS); +}; + +#define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu) +#define pmu_to_vcpu(pmu) (container_of((pmu), struct kvm_vcpu, arch.pmu)) + +int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi= _ext_data *edata); +int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_ext_data *edata); +int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_= base, + unsigned long ctr_mask, unsigned long flag, uint64_t ival, + struct kvm_vcpu_sbi_ext_data *edata); +int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_b= ase, + unsigned long ctr_mask, unsigned long flag, + struct kvm_vcpu_sbi_ext_data *edata); +int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long = ctr_base, + unsigned long ctr_mask, unsigned long flag, + unsigned long eidx, uint64_t edata, + struct kvm_vcpu_sbi_ext_data *extdata); +int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_ext_data *edata); +int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu); + +#else +struct kvm_pmu { +}; + +static inline int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) +{ + return 0; +} +static inline void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) {} +static inline void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) {} +#endif +#endif diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 019df920..5de1053 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -25,3 +25,4 @@ kvm-y +=3D vcpu_sbi_base.o kvm-y +=3D vcpu_sbi_replace.o kvm-y +=3D vcpu_sbi_hsm.o kvm-y +=3D vcpu_timer.o +kvm-$(CONFIG_RISCV_PMU_SBI) +=3D vcpu_pmu.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 7c08567..b746f21 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -137,6 +137,7 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) =20 WRITE_ONCE(vcpu->arch.irqs_pending, 0); WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0); + kvm_riscv_vcpu_pmu_reset(vcpu); =20 vcpu->arch.hfence_head =3D 0; vcpu->arch.hfence_tail =3D 0; @@ -194,6 +195,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) /* Setup VCPU timer */ kvm_riscv_vcpu_timer_init(vcpu); =20 + /* setup performance monitoring */ + kvm_riscv_vcpu_pmu_init(vcpu); + /* Reset VCPU */ kvm_riscv_reset_vcpu(vcpu); =20 @@ -216,6 +220,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) /* Cleanup VCPU timer */ kvm_riscv_vcpu_timer_deinit(vcpu); =20 + kvm_riscv_vcpu_pmu_deinit(vcpu); /* Free unused pages pre-allocated for G-stage page table mappings */ kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); } diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index 0bb5276..1ff2649 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -213,7 +213,7 @@ struct csr_func { unsigned long wr_mask); }; =20 -static const struct csr_func csr_funcs[] =3D { }; +static const struct csr_func csr_funcs[] =3D {}; =20 /** * kvm_riscv_vcpu_csr_return -- Handle CSR read/write after user space diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c new file mode 100644 index 0000000..0f0748f1 --- /dev/null +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Rivos Inc + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define kvm_pmu_num_counters(pmu) ((pmu)->num_hw_ctrs + (pmu)->num_fw_ctrs) + +int kvm_riscv_vcpu_pmu_num_ctrs(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi= _ext_data *edata) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + + edata->out_val =3D kvpmu->num_fw_ctrs + kvpmu->num_hw_ctrs; + + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_info(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_ext_data *edata) +{ + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + + if ((cidx > RISCV_MAX_COUNTERS) || (cidx =3D=3D 1)) { + edata->err_val =3D SBI_ERR_INVALID_PARAM; + return 0; + } + + edata->out_val =3D kvpmu->pmc[cidx].cinfo.value; + + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_start(struct kvm_vcpu *vcpu, unsigned long ctr_= base, + unsigned long ctr_mask, unsigned long flag, uint64_t ival, + struct kvm_vcpu_sbi_ext_data *edata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_b= ase, + unsigned long ctr_mask, unsigned long flag, + struct kvm_vcpu_sbi_ext_data *edata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_cfg_match(struct kvm_vcpu *vcpu, unsigned long = ctr_base, + unsigned long ctr_mask, unsigned long flag, + unsigned long eidx, uint64_t edata, + struct kvm_vcpu_sbi_ext_data *extdata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned long cidx, + struct kvm_vcpu_sbi_ext_data *edata) +{ + /* TODO */ + return 0; +} + +int kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu) +{ + int i =3D 0, num_fw_ctrs, ret, num_hw_ctrs =3D 0, hpm_width =3D 0; + struct kvm_pmu *kvpmu =3D vcpu_to_pmu(vcpu); + + ret =3D riscv_pmu_get_hpm_info(&hpm_width, &num_hw_ctrs); + if (ret < 0) + return ret; + + if (!hpm_width || !num_hw_ctrs) { + pr_err("Can not initialize PMU for vcpu with NULL hpmcounter width/count= \n"); + return -EINVAL; + } + + if ((num_hw_ctrs + RISCV_KVM_MAX_FW_CTRS) > RISCV_MAX_COUNTERS) + num_fw_ctrs =3D RISCV_MAX_COUNTERS - num_hw_ctrs; + else + num_fw_ctrs =3D RISCV_KVM_MAX_FW_CTRS; + + kvpmu->num_hw_ctrs =3D num_hw_ctrs; + kvpmu->num_fw_ctrs =3D num_fw_ctrs; + /* + * There is no corelation betwen the logical hardware counter and virtual= counters. + * However, we need to encode a hpmcounter CSR in the counter info field = so that + * KVM can trap n emulate the read. This works well in the migraiton usec= ase as + * KVM doesn't care if the actual hpmcounter is available in the hardware= or not. + */ + for (i =3D 0; i < kvm_pmu_num_counters(kvpmu); i++) { + /* TIME CSR shouldn't be read from perf interface */ + if (i =3D=3D 1) + continue; + kvpmu->pmc[i].idx =3D i; + if (i < kvpmu->num_hw_ctrs) { + kvpmu->pmc[i].cinfo.type =3D SBI_PMU_CTR_TYPE_HW; + if (i < 3) + /* CY, IR counters */ + kvpmu->pmc[i].cinfo.width =3D 63; + else + kvpmu->pmc[i].cinfo.width =3D hpm_width; + /* + * The CSR number doesn't have any relation with the logical + * hardware counters. The CSR numbers are encoded sequentially + * to avoid maintaining a map between the virtual counter + * and CSR number. + */ + kvpmu->pmc[i].cinfo.csr =3D CSR_CYCLE + i; + } else { + kvpmu->pmc[i].cinfo.type =3D SBI_PMU_CTR_TYPE_FW; + kvpmu->pmc[i].cinfo.width =3D BITS_PER_LONG - 1; + } + } + + kvpmu->init_done =3D true; + + return 0; +} + +void kvm_riscv_vcpu_pmu_reset(struct kvm_vcpu *vcpu) +{ + /* TODO */ +} + +void kvm_riscv_vcpu_pmu_deinit(struct kvm_vcpu *vcpu) +{ + /* TODO */ +} + --=20 2.25.1