From nobody Mon Apr 13 00:39:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1B8CC4332F for ; Thu, 15 Dec 2022 17:02:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230395AbiLORCT (ORCPT ); Thu, 15 Dec 2022 12:02:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230407AbiLORB1 (ORCPT ); Thu, 15 Dec 2022 12:01:27 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D04726A83 for ; Thu, 15 Dec 2022 09:01:18 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id x2so6184341plb.13 for ; Thu, 15 Dec 2022 09:01:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TA398QcoRw04Vi1tCToQyhK2GccVMIkF9itdIbQrjzg=; b=iCBFE98jjH1B+jWMupgkTrrpBiqryRet5vyKfU7xYz2IrRVevL7rN4/R8A1XGxSdrD S7lP75oLwz8r/CmXjPNMEcn116Bp8Pph6YlSIDoJD9xM/0Y5fCGJ7RDpT5PS4h43v3Az sUmCxrLeGrYguKN7cGHsUksEb4w8uhufJikxuzvkuL7Jhdbrlz/I0lAFSnrI5/aNNVF7 tDv74BKoI3m1btLXcPGMdCgjwWFcXVingmbKafWVyv6c4LUftSPSXRnkHh87ucAMEApM ijBLm3eRnw77G8KAHXEW91Fcfhvz+E/HTZKoachHXH/vKtbBaoUYsA3VwkLs26TGRH2j nexw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TA398QcoRw04Vi1tCToQyhK2GccVMIkF9itdIbQrjzg=; b=Mgn6IQ6eo+cVyemOq953OSN1x6i5OH5RcdR2MQOYhgEKSRNUHDpnAM7UZnuzNkqSxB fxNjiSM4y3FCXMYcHwjYpH9dIlF9rEmWO1UrETaTVwPB9nJFOypEjwnqNyfkyXK52Z+F gME2fR5QOMbab48jz2Ckyugm/XyJZ+cnFYCjaitFu9IkVND8bVOQSTPE1XupKLPzPI/a A3RKSVjxPmNSOKgmyED0xp0QnCPdFUzJFfNH5+Vnm0RQ6Wat9oZueWLrfEFg7bRWDKMt ++TsWH5QEroblWu70c3bXFfULDXWC9H8pLvgAX+lJ9biHcd6G2VJ4ym1U2ORl6kByl/s wsFQ== X-Gm-Message-State: ANoB5pklMlQPSGgtC1qBbrLss8JaZ9jnxC2kQRzenDm8yxO7If5mH/qj x5bFL93GlCk0LKl3A3dsJzunnCSjb+3weJ1P X-Google-Smtp-Source: AA0mqf47OVooaAtiLeQdMDJXJiy7Bs5Hr2tNJlG8coYqXqFyYi7GgQGyDqsU+jYbG5rwf3pgYZ6MqQ== X-Received: by 2002:a17:903:2448:b0:189:f277:3830 with SMTP id l8-20020a170903244800b00189f2773830mr43509522pls.68.1671123677816; Thu, 15 Dec 2022 09:01:17 -0800 (PST) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id p10-20020a170902780a00b001897bfc9800sm4067449pll.53.2022.12.15.09.01.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 09:01:17 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Andrew Jones , Anup Patel , Atish Patra , Guo Ren , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Sergey Matyukevich , Eric Lin , Will Deacon Subject: [PATCH v2 05/11] RISC-V: KVM: Improve privilege mode filtering for perf Date: Thu, 15 Dec 2022 09:00:40 -0800 Message-Id: <20221215170046.2010255-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215170046.2010255-1-atishp@rivosinc.com> References: <20221215170046.2010255-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the host driver doesn't have any method to identify if the requested perf event is from kvm or bare metal. As KVM runs in HS mode, there are no separate hypervisor privilege mode to distinguish between the attributes for guest/host. Improve the privilege mode filtering by using the event specific config1 field. Reviewed-by: Andrew Jones Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 27 ++++++++++++++++++++++----- include/linux/perf/riscv_pmu.h | 2 ++ 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 65d4aa4..df795b7 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -298,6 +298,27 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num= _hw_ctr) } EXPORT_SYMBOL(riscv_pmu_get_hpm_info); =20 +static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) +{ + unsigned long cflags =3D 0; + bool guest_events =3D false; + + if (event->attr.config1 & RISCV_KVM_PMU_CONFIG1_GUEST_EVENTS) + guest_events =3D true; + if (event->attr.exclude_kernel) + cflags |=3D guest_events ? SBI_PMU_CFG_FLAG_SET_VSINH : SBI_PMU_CFG_FLAG= _SET_SINH; + if (event->attr.exclude_user) + cflags |=3D guest_events ? SBI_PMU_CFG_FLAG_SET_VUINH : SBI_PMU_CFG_FLAG= _SET_UINH; + if (guest_events && event->attr.exclude_hv) + cflags |=3D SBI_PMU_CFG_FLAG_SET_SINH; + if (event->attr.exclude_host) + cflags |=3D SBI_PMU_CFG_FLAG_SET_UINH | SBI_PMU_CFG_FLAG_SET_SINH; + if (event->attr.exclude_guest) + cflags |=3D SBI_PMU_CFG_FLAG_SET_VSINH | SBI_PMU_CFG_FLAG_SET_VUINH; + + return cflags; +} + static int pmu_sbi_ctr_get_idx(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; @@ -308,11 +329,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *even= t) uint64_t cbase =3D 0; unsigned long cflags =3D 0; =20 - if (event->attr.exclude_kernel) - cflags |=3D SBI_PMU_CFG_FLAG_SET_SINH; - if (event->attr.exclude_user) - cflags |=3D SBI_PMU_CFG_FLAG_SET_UINH; - + cflags =3D pmu_sbi_get_filter_flags(event); /* retrieve the available counter index */ #if defined(CONFIG_32BIT) ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index a1c3f77..1c42146 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -26,6 +26,8 @@ =20 #define RISCV_PMU_STOP_FLAG_RESET 1 =20 +#define RISCV_KVM_PMU_CONFIG1_GUEST_EVENTS 0x1 + struct cpu_hw_events { /* currently enabled events */ int n_events; --=20 2.25.1