From nobody Sat Sep 21 09:28:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 554C0C4332F for ; Thu, 15 Dec 2022 12:00:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230017AbiLOMAr (ORCPT ); Thu, 15 Dec 2022 07:00:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229911AbiLOMAg (ORCPT ); Thu, 15 Dec 2022 07:00:36 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85E202A971; Thu, 15 Dec 2022 04:00:30 -0800 (PST) X-UUID: b29e245b14ed4bf79f1c289646d8140c-20221215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=vpKkQlPxOc+D9lcuAshw5hI22iECWZhtKc+FVAsWhts=; b=VT3JbfMxK3b75yAzLqHOgtpQsUB8hQEuXCnwQrrDjAUVq823jbW6tANMSNsdE5Laq0b2Ym2gVR8f4HbIZmEzg1gbVxiEBD9YW8XdPkse3NU9UIGcHJs3BxWzoNsfXvkViAOjvoKuvIiu7Nna0MuuIFOg5pMGhvaGpxg8iUJvIPM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:62aa2467-c162-43e7-9cf8-0e1f198a5f57,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.14,REQID:62aa2467-c162-43e7-9cf8-0e1f198a5f57,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:dcaaed0,CLOUDID:2cc5b0b4-d2e2-434d-b6d3-aeae88dfcc78,B ulkID:2212152000249XNCI60I,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: b29e245b14ed4bf79f1c289646d8140c-20221215 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 251356229; Thu, 15 Dec 2022 20:00:21 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 15 Dec 2022 20:00:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 15 Dec 2022 20:00:21 +0800 From: Allen-KH Cheng To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Jie Chen , Stephen Boyd , Ikjoon Jang CC: , , , , , , Chen-Yu Tsai , Allen-KH Cheng Subject: [PATCH 4/4] arm64: dts: mediatek: Add the missing ADSP power domains controller for MT8192 Date: Thu, 15 Dec 2022 20:00:16 +0800 Message-ID: <20221215120016.26611-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221215120016.26611-1-allen-kh.cheng@mediatek.com> References: <20221215120016.26611-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the missing ADSP power domains controller for mt8192-scp_adsp clock controllers. Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers") Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 6b20376191a7..6ee60db3ac23 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -511,6 +511,14 @@ }; }; }; + + power-domain@MT8192_POWER_DOMAIN_ADSP { + reg =3D ; + clocks =3D <&topckgen CLK_TOP_ADSP_SEL>; + clock-names =3D "adsp"; + mediatek,infracfg =3D <&infracfg>; + #power-domain-cells =3D <0>; + }; }; }; =20 @@ -574,6 +582,7 @@ scp_adsp: clock-controller@10720000 { compatible =3D "mediatek,mt8192-scp_adsp"; reg =3D <0 0x10720000 0 0x1000>; + power-domains =3D <&spm MT8192_POWER_DOMAIN_ADSP>; #clock-cells =3D <1>; }; =20 --=20 2.18.0