From nobody Mon Feb 9 00:29:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9660C4332F for ; Thu, 15 Dec 2022 07:28:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229755AbiLOH2a (ORCPT ); Thu, 15 Dec 2022 02:28:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229616AbiLOH2X (ORCPT ); Thu, 15 Dec 2022 02:28:23 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A27C205FD for ; Wed, 14 Dec 2022 23:28:18 -0800 (PST) X-UUID: 34dc1c1026254c8b9c8ae3340cca24eb-20221215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; 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charset="utf-8" Use GCE_CTRL_BY_SW definition instead of number Signed-off-by: Yongqiang Niu Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 9465f9081515..c3cb24f51699 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -38,6 +38,7 @@ #define CMDQ_THR_PRIORITY 0x40 =20 #define GCE_GCTL_VALUE 0x48 +#define GCE_CTRL_BY_SW GENMASK(2, 0) =20 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 @@ -129,7 +130,8 @@ static void cmdq_init(struct cmdq *cmdq) =20 WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); if (cmdq->control_by_sw) - writel(0x7, cmdq->base + GCE_GCTL_VALUE); + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i =3D 0; i <=3D CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); --=20 2.25.1 From nobody Mon Feb 9 00:29:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97DADC4332F for ; Thu, 15 Dec 2022 07:28:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229873AbiLOH2h (ORCPT ); Thu, 15 Dec 2022 02:28:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43306 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229683AbiLOH2X (ORCPT ); Thu, 15 Dec 2022 02:28:23 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B951209B0 for ; Wed, 14 Dec 2022 23:28:18 -0800 (PST) X-UUID: c9128817d22c425a8e491a5990120b89-20221215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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Thu, 15 Dec 2022 15:28:12 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 15 Dec 2022 15:28:10 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 15 Dec 2022 15:28:10 +0800 From: Yongqiang Niu To: CK Hu , Chun-Kuang Hu , Jassi Brar , Matthias Brugger CC: , , , , Hsin-Yi Wang , Yongqiang Niu Subject: [PATCH v11, 2/4] mailbox: mtk-cmdq: add gce software ddr enable private data Date: Thu, 15 Dec 2022 15:28:04 +0800 Message-ID: <20221215072806.10224-3-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215072806.10224-1-yongqiang.niu@mediatek.com> References: <20221215072806.10224-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" if gce work control by software, we need set software enable for MT8186 Soc there is a handshake flow between gce and ddr hardware, if not set ddr enable flag of gce, ddr will fall into idle mode, then gce instructions will not process done. we need set this flag of gce to tell ddr when gce is idle or busy controlled by software flow. 0x48[2:0] means control by software 0x48[18:16] means ddr enable 0x48[2:0] is pre-condition of 0x48[18:16]. if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same time. and only these bits is useful, other bits is useless bits Signed-off-by: Yongqiang Niu Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index c3cb24f51699..d2363c6b8b7a 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -39,6 +39,7 @@ =20 #define GCE_GCTL_VALUE 0x48 #define GCE_CTRL_BY_SW GENMASK(2, 0) +#define GCE_DDR_EN GENMASK(18, 16) =20 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 @@ -81,6 +82,7 @@ struct cmdq { bool suspended; u8 shift_pa; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; =20 @@ -88,6 +90,7 @@ struct gce_plat { u32 thread_nr; u8 shift; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; =20 @@ -127,10 +130,16 @@ static void cmdq_thread_resume(struct cmdq_thread *th= read) static void cmdq_init(struct cmdq *cmdq) { int i; + u32 gctl_regval =3D 0; =20 WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); if (cmdq->control_by_sw) - writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + gctl_regval =3D GCE_CTRL_BY_SW; + if (cmdq->sw_ddr_en) + gctl_regval |=3D GCE_DDR_EN; + + if (gctl_regval) + writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE); =20 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i =3D 0; i <=3D CMDQ_MAX_EVENT; i++) @@ -545,6 +554,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr =3D plat_data->thread_nr; cmdq->shift_pa =3D plat_data->shift; cmdq->control_by_sw =3D plat_data->control_by_sw; + cmdq->sw_ddr_en =3D plat_data->sw_ddr_en; cmdq->gce_num =3D plat_data->gce_num; cmdq->irq_mask =3D GENMASK(cmdq->thread_nr - 1, 0); err =3D devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, --=20 2.25.1 From nobody Mon Feb 9 00:29:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1E99C4332F for ; Thu, 15 Dec 2022 07:29:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230048AbiLOH2z (ORCPT ); Thu, 15 Dec 2022 02:28:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229930AbiLOH2q (ORCPT ); Thu, 15 Dec 2022 02:28:46 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E385226A99 for ; Wed, 14 Dec 2022 23:28:37 -0800 (PST) X-UUID: 700275ce7bb34713be59d11de7293f13-20221215 DKIM-Signature: v=1; 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Thu, 15 Dec 2022 15:28:33 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 15 Dec 2022 15:28:11 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 15 Dec 2022 15:28:10 +0800 From: Yongqiang Niu To: CK Hu , Chun-Kuang Hu , Jassi Brar , Matthias Brugger CC: , , , , Hsin-Yi Wang , Yongqiang Niu , AngeloGioacchino Del Regno Subject: [PATCH v11, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow Date: Thu, 15 Dec 2022 15:28:05 +0800 Message-ID: <20221215072806.10224-4-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215072806.10224-1-yongqiang.niu@mediatek.com> References: <20221215072806.10224-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" add gce ddr enable control flow when gce suspend/resume when all cmdq instruction task has been processed done, we need set this gce ddr enable to disable status to tell cmdq hardware gce there is none task need process, and the hardware can go into idle mode and no access ddr anymore, then the spm can go into suspend. the original issue is gce still access ddr when cmdq suspend function call, but there is no task run. so, we need control gce access ddr with this flow. when cmdq suspend function, there is no task need process, we can disable gce access ddr, to make sure system go into suspend success. Signed-off-by: Yongqiang Niu Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index d2363c6b8b7a..53904511598d 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -94,6 +94,18 @@ struct gce_plat { u32 gce_num; }; =20 +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable) +{ + WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); + + if (enable) + writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + else + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); +} + u8 cmdq_get_shift_pa(struct mbox_chan *chan) { struct cmdq *cmdq =3D container_of(chan->mbox, struct cmdq, mbox); @@ -322,6 +334,9 @@ static int cmdq_suspend(struct device *dev) if (task_running) dev_warn(dev, "exist running task(s) in suspend\n"); =20 + if (cmdq->sw_ddr_en) + cmdq_sw_ddr_enable(cmdq, false); + clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); =20 return 0; @@ -333,6 +348,10 @@ static int cmdq_resume(struct device *dev) =20 WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks)); cmdq->suspended =3D false; + + if (cmdq->sw_ddr_en) + cmdq_sw_ddr_enable(cmdq, true); + return 0; } =20 @@ -340,6 +359,9 @@ static int cmdq_remove(struct platform_device *pdev) { struct cmdq *cmdq =3D platform_get_drvdata(pdev); =20 + if (cmdq->sw_ddr_en) + cmdq_sw_ddr_enable(cmdq, false); + clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); return 0; } --=20 2.25.1 From nobody Mon Feb 9 00:29:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3C0EC4332F for ; Thu, 15 Dec 2022 07:28:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229811AbiLOH2d (ORCPT ); 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Thu, 15 Dec 2022 15:28:13 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 15 Dec 2022 15:28:12 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 15 Dec 2022 15:28:11 +0800 From: Yongqiang Niu To: CK Hu , Chun-Kuang Hu , Jassi Brar , Matthias Brugger CC: , , , , Hsin-Yi Wang , Yongqiang Niu , AngeloGioacchino Del Regno Subject: [PATCH v11, 4/4] mailbox: mtk-cmdq: add MT8186 support Date: Thu, 15 Dec 2022 15:28:06 +0800 Message-ID: <20221215072806.10224-5-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221215072806.10224-1-yongqiang.niu@mediatek.com> References: <20221215072806.10224-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" add MT8186 cmdq support Signed-off-by: Yongqiang Niu Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 53904511598d..c5229f377c5e 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -694,9 +694,18 @@ static const struct gce_plat gce_plat_v6 =3D { .gce_num =3D 2 }; =20 +static const struct gce_plat gce_plat_v7 =3D { + .thread_nr =3D 24, + .shift =3D 3, + .control_by_sw =3D true, + .sw_ddr_en =3D true, + .gce_num =3D 1 +}; + static const struct of_device_id cmdq_of_ids[] =3D { {.compatible =3D "mediatek,mt8173-gce", .data =3D (void *)&gce_plat_v2}, {.compatible =3D "mediatek,mt8183-gce", .data =3D (void *)&gce_plat_v3}, + {.compatible =3D "mediatek,mt8186-gce", .data =3D (void *)&gce_plat_v7}, {.compatible =3D "mediatek,mt6779-gce", .data =3D (void *)&gce_plat_v4}, {.compatible =3D "mediatek,mt8192-gce", .data =3D (void *)&gce_plat_v5}, {.compatible =3D "mediatek,mt8195-gce", .data =3D (void *)&gce_plat_v6}, --=20 2.25.1