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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t30-20020a37ea1e000000b006eef13ef4c8sm10305477qkj.94.2022.12.14.09.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 09:12:00 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com Subject: [PATCH v2 3/7] arm64: dts: qcom: sc8280xp: rename qup0_i2c4 to i2c4 Date: Wed, 14 Dec 2022 12:11:41 -0500 Message-Id: <20221214171145.2913557-4-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221214171145.2913557-1-bmasney@redhat.com> References: <20221214171145.2913557-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup0_i2c4 to i2c4. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Signed-off-by: Brian Masney Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.= com/ Reviewed-by: Konrad Dybcio --- This is a new patch that's introduced in v2. arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 58 +++++++++---------- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 58 +++++++++---------- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 3 files changed, 59 insertions(+), 59 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index 0de1bdb68e2c..c37a9d93a2a8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -228,6 +228,27 @@ vreg_l9d: ldo9 { }; }; =20 +&i2c4 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_default>; + + status =3D "okay"; + + touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts0_default>; + }; +}; + &i2c21 { clock-frequency =3D <400000>; =20 @@ -334,27 +355,6 @@ &qup0 { status =3D "okay"; }; =20 -&qup0_i2c4 { - clock-frequency =3D <400000>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qup0_i2c4_default>; - - status =3D "okay"; - - touchscreen@10 { - compatible =3D "hid-over-i2c"; - reg =3D <0x10>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ts0_default>; - }; -}; - &qup1 { status =3D "okay"; }; @@ -494,6 +494,14 @@ hastings_reg_en: hastings-reg-en-state { &tlmm { gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; =20 + i2c4_default: i2c4-default-state { + pins =3D "gpio171", "gpio172"; + function =3D "qup4"; + + bias-disable; + drive-strength =3D <16>; + }; + i2c21_default: i2c21-default-state { pins =3D "gpio81", "gpio82"; function =3D "qup21"; @@ -598,14 +606,6 @@ wake-n-pins { }; }; =20 - qup0_i2c4_default: qup0-i2c4-default-state { - pins =3D "gpio171", "gpio172"; - function =3D "qup4"; - - bias-disable; - drive-strength =3D <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins =3D "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index d7af2040cbcb..ec06b6216408 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -282,6 +282,28 @@ vreg_l9d: ldo9 { }; }; =20 +&i2c4 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_default>; + + status =3D "okay"; + + /* FIXME: verify */ + touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts0_default>; + }; +}; + &i2c21 { clock-frequency =3D <400000>; =20 @@ -554,28 +576,6 @@ &qup0 { status =3D "okay"; }; =20 -&qup0_i2c4 { - clock-frequency =3D <400000>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qup0_i2c4_default>; - - status =3D "okay"; - - /* FIXME: verify */ - touchscreen@10 { - compatible =3D "hid-over-i2c"; - reg =3D <0x10>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ts0_default>; - }; -}; - &qup1 { status =3D "okay"; }; @@ -698,6 +698,13 @@ hall_int_n_default: hall-int-n-state { bias-disable; }; =20 + i2c4_default: i2c4-default-state { + pins =3D "gpio171", "gpio172"; + function =3D "qup4"; + bias-disable; + drive-strength =3D <16>; + }; + i2c21_default: i2c21-default-state { pins =3D "gpio81", "gpio82"; function =3D "qup21"; @@ -801,13 +808,6 @@ wake-n-pins { }; }; =20 - qup0_i2c4_default: qup0-i2c4-default-state { - pins =3D "gpio171", "gpio172"; - function =3D "qup4"; - bias-disable; - drive-strength =3D <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins =3D "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 929365cff555..f1111cd7f679 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -858,7 +858,7 @@ qup0: geniqup@9c0000 { =20 status =3D "disabled"; =20 - qup0_i2c4: i2c@990000 { + i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00990000 0 0x4000>; clock-names =3D "se"; --=20 2.38.1