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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t30-20020a37ea1e000000b006eef13ef4c8sm10305477qkj.94.2022.12.14.09.11.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 09:11:57 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com Subject: [PATCH v2 1/7] arm64: dts: qcom: sc8280xp: rename qup2_uart17 to uart17 Date: Wed, 14 Dec 2022 12:11:39 -0500 Message-Id: <20221214171145.2913557-2-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221214171145.2913557-1-bmasney@redhat.com> References: <20221214171145.2913557-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup2_uart17 to uart17. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Signed-off-by: Brian Masney Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.= com/ Reviewed-by: Konrad Dybcio --- This is a new patch that's introduced in v2. arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 12 ++++++------ arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 12 ++++++------ arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 14 +++++++------- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts= /qcom/sa8295p-adp.dts index 84cb6f3eeb56..61f2e44e70c1 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -17,7 +17,7 @@ / { compatible =3D "qcom,sa8295p-adp", "qcom,sa8540p"; =20 aliases { - serial0 =3D &qup2_uart17; + serial0 =3D &uart17; }; =20 chosen { @@ -240,11 +240,6 @@ &qup2 { status =3D "okay"; }; =20 -&qup2_uart17 { - compatible =3D "qcom,geni-debug-uart"; - status =3D "okay"; -}; - &remoteproc_adsp { firmware-name =3D "qcom/sa8540p/adsp.mbn"; status =3D "okay"; @@ -338,6 +333,11 @@ pm8450g_gpios: gpio@c000 { }; }; =20 +&uart17 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + &ufs_mem_hc { reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; =20 diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8540p-ride.dts index 21f3ff024910..b6e0db5508c7 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -17,7 +17,7 @@ / { compatible =3D "qcom,sa8540p-ride", "qcom,sa8540p"; =20 aliases { - serial0 =3D &qup2_uart17; + serial0 =3D &uart17; }; =20 chosen { @@ -192,11 +192,6 @@ &qup2 { status =3D "okay"; }; =20 -&qup2_uart17 { - compatible =3D "qcom,geni-debug-uart"; - status =3D "okay"; -}; - &remoteproc_nsp0 { firmware-name =3D "qcom/sa8540p/cdsp.mbn"; status =3D "okay"; @@ -207,6 +202,11 @@ &remoteproc_nsp1 { status =3D "okay"; }; =20 +&uart17 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + &ufs_mem_hc { reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; =20 diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index 551768f97729..db273face248 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -17,7 +17,7 @@ / { compatible =3D "qcom,sc8280xp-crd", "qcom,sc8280xp"; =20 aliases { - serial0 =3D &qup2_uart17; + serial0 =3D &uart17; }; =20 backlight { @@ -363,12 +363,6 @@ keyboard@68 { }; }; =20 -&qup2_uart17 { - compatible =3D "qcom,geni-debug-uart"; - - status =3D "okay"; -}; - &remoteproc_adsp { firmware-name =3D "qcom/sc8280xp/qcadsp8280.mbn"; =20 @@ -381,6 +375,12 @@ &remoteproc_nsp0 { status =3D "okay"; }; =20 +&uart17 { + compatible =3D "qcom,geni-debug-uart"; + + status =3D "okay"; +}; + &ufs_mem_hc { reset-gpios =3D <&tlmm 228 GPIO_ACTIVE_LOW>; =20 diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 109c9d2b684d..951cb1b6fcc4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -813,7 +813,7 @@ qup2: geniqup@8c0000 { =20 status =3D "disabled"; =20 - qup2_uart17: serial@884000 { + uart17: serial@884000 { compatible =3D "qcom,geni-uart"; reg =3D <0 0x00884000 0 0x4000>; clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; --=20 2.38.1 From nobody Wed Sep 17 22:18:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBA58C4332F for ; Wed, 14 Dec 2022 17:13:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237947AbiLNRNe (ORCPT ); Wed, 14 Dec 2022 12:13:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230004AbiLNRN3 (ORCPT ); Wed, 14 Dec 2022 12:13:29 -0500 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A28A726573 for ; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t30-20020a37ea1e000000b006eef13ef4c8sm10305477qkj.94.2022.12.14.09.11.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 09:11:59 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com Subject: [PATCH v2 2/7] arm64: dts: qcom: sc8280xp: rename qup2_i2c5 to i2c21 Date: Wed, 14 Dec 2022 12:11:40 -0500 Message-Id: <20221214171145.2913557-3-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221214171145.2913557-1-bmasney@redhat.com> References: <20221214171145.2913557-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup2_i2c5 to i2c21. Under the old name, this was the 5th index under qup2, which starts at index 16. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Signed-off-by: Brian Masney Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.= com/ Reviewed-by: Konrad Dybcio --- This is a new patch that's introduced in v2. arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 90 ++++++------- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 120 +++++++++--------- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 3 files changed, 106 insertions(+), 106 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index db273face248..0de1bdb68e2c 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -228,6 +228,43 @@ vreg_l9d: ldo9 { }; }; =20 +&i2c21 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c21_default>; + + status =3D "okay"; + + touchpad@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tpad_default>; + + wakeup-source; + }; + + keyboard@68 { + compatible =3D "hid-over-i2c"; + reg =3D <0x68>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&kybd_default>; + + wakeup-source; + }; +}; + &pcie2a { perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; @@ -326,43 +363,6 @@ &qup2 { status =3D "okay"; }; =20 -&qup2_i2c5 { - clock-frequency =3D <400000>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qup2_i2c5_default>; - - status =3D "okay"; - - touchpad@15 { - compatible =3D "hid-over-i2c"; - reg =3D <0x15>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&tpad_default>; - - wakeup-source; - }; - - keyboard@68 { - compatible =3D "hid-over-i2c"; - reg =3D <0x68>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&kybd_default>; - - wakeup-source; - }; -}; - &remoteproc_adsp { firmware-name =3D "qcom/sc8280xp/qcadsp8280.mbn"; =20 @@ -494,6 +494,14 @@ hastings_reg_en: hastings-reg-en-state { &tlmm { gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; =20 + i2c21_default: i2c21-default-state { + pins =3D "gpio81", "gpio82"; + function =3D "qup21"; + + bias-disable; + drive-strength =3D <16>; + }; + kybd_default: kybd-default-state { disable-pins { pins =3D "gpio102"; @@ -598,14 +606,6 @@ qup0_i2c4_default: qup0-i2c4-default-state { drive-strength =3D <16>; }; =20 - qup2_i2c5_default: qup2-i2c5-default-state { - pins =3D "gpio81", "gpio82"; - function =3D "qup21"; - - bias-disable; - drive-strength =3D <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins =3D "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 568c6be1ceaa..d7af2040cbcb 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -282,6 +282,59 @@ vreg_l9d: ldo9 { }; }; =20 +&i2c21 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c21_default>; + + status =3D "okay"; + + touchpad@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tpad_default>; + + wakeup-source; + + status =3D "disabled"; + }; + + touchpad@2c { + compatible =3D "hid-over-i2c"; + reg =3D <0x2c>; + + hid-descr-addr =3D <0x20>; + interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tpad_default>; + + wakeup-source; + }; + + keyboard@68 { + compatible =3D "hid-over-i2c"; + reg =3D <0x68>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&kybd_default>; + + wakeup-source; + }; +}; + &pcie2a { perst-gpios =3D <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 145 GPIO_ACTIVE_LOW>; @@ -531,59 +584,6 @@ &qup2 { status =3D "okay"; }; =20 -&qup2_i2c5 { - clock-frequency =3D <400000>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qup2_i2c5_default>; - - status =3D "okay"; - - touchpad@15 { - compatible =3D "hid-over-i2c"; - reg =3D <0x15>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&tpad_default>; - - wakeup-source; - - status =3D "disabled"; - }; - - touchpad@2c { - compatible =3D "hid-over-i2c"; - reg =3D <0x2c>; - - hid-descr-addr =3D <0x20>; - interrupts-extended =3D <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&tpad_default>; - - wakeup-source; - }; - - keyboard@68 { - compatible =3D "hid-over-i2c"; - reg =3D <0x68>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&kybd_default>; - - wakeup-source; - }; -}; - &remoteproc_adsp { firmware-name =3D "qcom/sc8280xp/LENOVO/21BX/qcadsp8280.mbn"; =20 @@ -698,6 +698,13 @@ hall_int_n_default: hall-int-n-state { bias-disable; }; =20 + i2c21_default: i2c21-default-state { + pins =3D "gpio81", "gpio82"; + function =3D "qup21"; + bias-disable; + drive-strength =3D <16>; + }; + kybd_default: kybd-default-state { disable-pins { pins =3D "gpio102"; @@ -801,13 +808,6 @@ qup0_i2c4_default: qup0-i2c4-default-state { drive-strength =3D <16>; }; =20 - qup2_i2c5_default: qup2-i2c5-default-state { - pins =3D "gpio81", "gpio82"; - function =3D "qup21"; - bias-disable; - drive-strength =3D <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins =3D "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 951cb1b6fcc4..929365cff555 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -827,7 +827,7 @@ uart17: serial@884000 { status =3D "disabled"; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t30-20020a37ea1e000000b006eef13ef4c8sm10305477qkj.94.2022.12.14.09.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 09:12:00 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com Subject: [PATCH v2 3/7] arm64: dts: qcom: sc8280xp: rename qup0_i2c4 to i2c4 Date: Wed, 14 Dec 2022 12:11:41 -0500 Message-Id: <20221214171145.2913557-4-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221214171145.2913557-1-bmasney@redhat.com> References: <20221214171145.2913557-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup0_i2c4 to i2c4. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Signed-off-by: Brian Masney Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.= com/ Reviewed-by: Konrad Dybcio --- This is a new patch that's introduced in v2. arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 58 +++++++++---------- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 58 +++++++++---------- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 3 files changed, 59 insertions(+), 59 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dt= s/qcom/sc8280xp-crd.dts index 0de1bdb68e2c..c37a9d93a2a8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -228,6 +228,27 @@ vreg_l9d: ldo9 { }; }; =20 +&i2c4 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_default>; + + status =3D "okay"; + + touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts0_default>; + }; +}; + &i2c21 { clock-frequency =3D <400000>; =20 @@ -334,27 +355,6 @@ &qup0 { status =3D "okay"; }; =20 -&qup0_i2c4 { - clock-frequency =3D <400000>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qup0_i2c4_default>; - - status =3D "okay"; - - touchscreen@10 { - compatible =3D "hid-over-i2c"; - reg =3D <0x10>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ts0_default>; - }; -}; - &qup1 { status =3D "okay"; }; @@ -494,6 +494,14 @@ hastings_reg_en: hastings-reg-en-state { &tlmm { gpio-reserved-ranges =3D <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; =20 + i2c4_default: i2c4-default-state { + pins =3D "gpio171", "gpio172"; + function =3D "qup4"; + + bias-disable; + drive-strength =3D <16>; + }; + i2c21_default: i2c21-default-state { pins =3D "gpio81", "gpio82"; function =3D "qup21"; @@ -598,14 +606,6 @@ wake-n-pins { }; }; =20 - qup0_i2c4_default: qup0-i2c4-default-state { - pins =3D "gpio171", "gpio172"; - function =3D "qup4"; - - bias-disable; - drive-strength =3D <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins =3D "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/a= rch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index d7af2040cbcb..ec06b6216408 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -282,6 +282,28 @@ vreg_l9d: ldo9 { }; }; =20 +&i2c4 { + clock-frequency =3D <400000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_default>; + + status =3D "okay"; + + /* FIXME: verify */ + touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + + hid-descr-addr =3D <0x1>; + interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply =3D <&vreg_misc_3p3>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ts0_default>; + }; +}; + &i2c21 { clock-frequency =3D <400000>; =20 @@ -554,28 +576,6 @@ &qup0 { status =3D "okay"; }; =20 -&qup0_i2c4 { - clock-frequency =3D <400000>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&qup0_i2c4_default>; - - status =3D "okay"; - - /* FIXME: verify */ - touchscreen@10 { - compatible =3D "hid-over-i2c"; - reg =3D <0x10>; - - hid-descr-addr =3D <0x1>; - interrupts-extended =3D <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; - vdd-supply =3D <&vreg_misc_3p3>; - - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ts0_default>; - }; -}; - &qup1 { status =3D "okay"; }; @@ -698,6 +698,13 @@ hall_int_n_default: hall-int-n-state { bias-disable; }; =20 + i2c4_default: i2c4-default-state { + pins =3D "gpio171", "gpio172"; + function =3D "qup4"; + bias-disable; + drive-strength =3D <16>; + }; + i2c21_default: i2c21-default-state { pins =3D "gpio81", "gpio82"; function =3D "qup21"; @@ -801,13 +808,6 @@ wake-n-pins { }; }; =20 - qup0_i2c4_default: qup0-i2c4-default-state { - pins =3D "gpio171", "gpio172"; - function =3D "qup4"; - bias-disable; - drive-strength =3D <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins =3D "gpio182"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 929365cff555..f1111cd7f679 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -858,7 +858,7 @@ qup0: geniqup@9c0000 { =20 status =3D "disabled"; =20 - qup0_i2c4: i2c@990000 { + i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00990000 0 0x4000>; clock-names =3D "se"; --=20 2.38.1 From nobody Wed Sep 17 22:18:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 666C4C4332F for ; Wed, 14 Dec 2022 17:14:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239224AbiLNROF (ORCPT ); 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t30-20020a37ea1e000000b006eef13ef4c8sm10305477qkj.94.2022.12.14.09.12.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 09:12:01 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com Subject: [PATCH v2 4/7] arm64: dts: qcom: sc8280xp: add missing i2c nodes Date: Wed, 14 Dec 2022 12:11:42 -0500 Message-Id: <20221214171145.2913557-5-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221214171145.2913557-1-bmasney@redhat.com> References: <20221214171145.2913557-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the missing nodes for the i2c buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney --- Changes since v1: - Dropped qupX_ prefix from labels. (Johan) arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 352 +++++++++++++++++++++++++ 1 file changed, 352 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index f1111cd7f679..a502d4e19d98 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -813,6 +813,38 @@ qup2: geniqup@8c0000 { =20 status =3D "disabled"; =20 + i2c16: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00880000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c17: i2c@884000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00884000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + uart17: serial@884000 { compatible =3D "qcom,geni-uart"; reg =3D <0 0x00884000 0 0x4000>; @@ -827,6 +859,54 @@ uart17: serial@884000 { status =3D "disabled"; }; =20 + i2c18: i2c@888000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00888000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c19: i2c@88c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0088c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c20: i2c@890000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00890000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c21: i2c@894000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00894000 0 0x4000>; @@ -842,6 +922,38 @@ i2c21: i2c@894000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + i2c22: i2c@898000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00898000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c23: i2c@89c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0089c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 qup0: geniqup@9c0000 { @@ -858,6 +970,70 @@ qup0: geniqup@9c0000 { =20 status =3D "disabled"; =20 + i2c0: i2c@980000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00980000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c1: i2c@984000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00984000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c2: i2c@988000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00988000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c3: i2c@98c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0098c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00990000 0 0x4000>; @@ -873,6 +1049,54 @@ i2c4: i2c@990000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + i2c5: i2c@994000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00994000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c6: i2c@998000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00998000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c7: i2c@99c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x0099c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 qup1: geniqup@ac0000 { @@ -888,6 +1112,134 @@ qup1: geniqup@ac0000 { ranges; =20 status =3D "disabled"; + + i2c8: i2c@a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a80000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c9: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a84000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c10: i2c@a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a88000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a8c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c12: i2c@a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a90000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c13: i2c@a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a94000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c14: i2c@a98000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a98000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0 0x00a9c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&rpmhpd SC8280XP_CX>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 pcie4: pcie@1c00000 { --=20 2.38.1 From nobody Wed Sep 17 22:18:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 505C2C4167B for ; Wed, 14 Dec 2022 17:14:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237354AbiLNROj (ORCPT ); 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t30-20020a37ea1e000000b006eef13ef4c8sm10305477qkj.94.2022.12.14.09.12.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 09:12:03 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com Subject: [PATCH v2 5/7] arm64: dts: qcom: sc8280xp: add missing spi nodes Date: Wed, 14 Dec 2022 12:11:43 -0500 Message-Id: <20221214171145.2913557-6-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221214171145.2913557-1-bmasney@redhat.com> References: <20221214171145.2913557-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the missing nodes for the spi buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney --- Changes since v1: - Dropped qupX_ prefix from labels. (Johan) - Dropped spi-max-frequency property from spi nodes. (Shazad) arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 360 +++++++++++++++++++++++++ 1 file changed, 360 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index a502d4e19d98..4591d411f5fb 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -829,6 +829,21 @@ i2c16: i2c@880000 { status =3D "disabled"; }; =20 + spi16: spi@880000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00880000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c17: i2c@884000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00884000 0 0x4000>; @@ -845,6 +860,21 @@ i2c17: i2c@884000 { status =3D "disabled"; }; =20 + spi17: spi@884000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00884000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + uart17: serial@884000 { compatible =3D "qcom,geni-uart"; reg =3D <0 0x00884000 0 0x4000>; @@ -875,6 +905,21 @@ i2c18: i2c@888000 { status =3D "disabled"; }; =20 + spi18: spi@888000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00888000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c19: i2c@88c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0088c000 0 0x4000>; @@ -891,6 +936,21 @@ i2c19: i2c@88c000 { status =3D "disabled"; }; =20 + spi19: spi@88c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0088c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c20: i2c@890000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00890000 0 0x4000>; @@ -907,6 +967,21 @@ i2c20: i2c@890000 { status =3D "disabled"; }; =20 + spi20: spi@890000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00890000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c21: i2c@894000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00894000 0 0x4000>; @@ -923,6 +998,21 @@ i2c21: i2c@894000 { status =3D "disabled"; }; =20 + spi21: spi@894000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00894000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c22: i2c@898000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00898000 0 0x4000>; @@ -939,6 +1029,21 @@ i2c22: i2c@898000 { status =3D "disabled"; }; =20 + spi22: spi@898000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00898000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c23: i2c@89c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0089c000 0 0x4000>; @@ -954,6 +1059,21 @@ i2c23: i2c@89c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + spi23: spi@89c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0089c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_C= ORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 qup0: geniqup@9c0000 { @@ -986,6 +1106,21 @@ i2c0: i2c@980000 { status =3D "disabled"; }; =20 + spi0: spi@980000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00980000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c1: i2c@984000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00984000 0 0x4000>; @@ -1002,6 +1137,21 @@ i2c1: i2c@984000 { status =3D "disabled"; }; =20 + spi1: spi@984000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00984000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c2: i2c@988000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00988000 0 0x4000>; @@ -1018,6 +1168,21 @@ i2c2: i2c@988000 { status =3D "disabled"; }; =20 + spi2: spi@988000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00988000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c3: i2c@98c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0098c000 0 0x4000>; @@ -1034,6 +1199,21 @@ i2c3: i2c@98c000 { status =3D "disabled"; }; =20 + spi3: spi@98c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0098c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c4: i2c@990000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00990000 0 0x4000>; @@ -1050,6 +1230,21 @@ i2c4: i2c@990000 { status =3D "disabled"; }; =20 + spi4: spi@990000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00990000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c5: i2c@994000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00994000 0 0x4000>; @@ -1066,6 +1261,21 @@ i2c5: i2c@994000 { status =3D "disabled"; }; =20 + spi5: spi@994000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00994000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c6: i2c@998000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00998000 0 0x4000>; @@ -1082,6 +1292,21 @@ i2c6: i2c@998000 { status =3D "disabled"; }; =20 + spi6: spi@998000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00998000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c7: i2c@99c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x0099c000 0 0x4000>; @@ -1097,6 +1322,21 @@ i2c7: i2c@99c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + spi7: spi@99c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x0099c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_C= ORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 qup1: geniqup@ac0000 { @@ -1129,6 +1369,21 @@ i2c8: i2c@a80000 { status =3D "disabled"; }; =20 + spi8: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a80000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c9: i2c@a84000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a84000 0 0x4000>; @@ -1145,6 +1400,21 @@ i2c9: i2c@a84000 { status =3D "disabled"; }; =20 + spi9: spi@a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a84000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c10: i2c@a88000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a88000 0 0x4000>; @@ -1161,6 +1431,21 @@ i2c10: i2c@a88000 { status =3D "disabled"; }; =20 + spi10: spi@a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a88000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c11: i2c@a8c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a8c000 0 0x4000>; @@ -1177,6 +1462,21 @@ i2c11: i2c@a8c000 { status =3D "disabled"; }; =20 + spi11: spi@a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a8c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c12: i2c@a90000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a90000 0 0x4000>; @@ -1193,6 +1493,21 @@ i2c12: i2c@a90000 { status =3D "disabled"; }; =20 + spi12: spi@a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a90000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c13: i2c@a94000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a94000 0 0x4000>; @@ -1209,6 +1524,21 @@ i2c13: i2c@a94000 { status =3D "disabled"; }; =20 + spi13: spi@a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a94000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c14: i2c@a98000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a98000 0 0x4000>; @@ -1225,6 +1555,21 @@ i2c14: i2c@a98000 { status =3D "disabled"; }; =20 + spi14: spi@a98000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a98000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; + i2c15: i2c@a9c000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00a9c000 0 0x4000>; @@ -1240,6 +1585,21 @@ i2c15: i2c@a9c000 { interconnect-names =3D "qup-core", "qup-config", "qup-memory"; status =3D "disabled"; }; + + spi15: spi@a9c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0 0x00a9c000 0 0x4000>; + clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names =3D "se"; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_C= ORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + status =3D "disabled"; + }; }; =20 pcie4: pcie@1c00000 { --=20 2.38.1 From nobody Wed Sep 17 22:18:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1774EC4332F for ; Wed, 14 Dec 2022 17:14:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239258AbiLNROo (ORCPT ); Wed, 14 Dec 2022 12:14:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235762AbiLNROK (ORCPT ); Wed, 14 Dec 2022 12:14:10 -0500 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA6C529361 for ; Wed, 14 Dec 2022 09:12:08 -0800 (PST) DKIM-Signature: v=1; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t30-20020a37ea1e000000b006eef13ef4c8sm10305477qkj.94.2022.12.14.09.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 09:12:05 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com Subject: [PATCH v2 6/7] arm64: dts: qcom: sa8540p-ride: add i2c nodes Date: Wed, 14 Dec 2022 12:11:44 -0500 Message-Id: <20221214171145.2913557-7-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221214171145.2913557-1-bmasney@redhat.com> References: <20221214171145.2913557-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the necessary nodes in order to get i2c0, i2c1, i2c12, i2c15, and i2c18 functioning on the automotive board and exposed to userspace. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. This change was validated by using i2c-tools 4.3.3 on CentOS Stream 9: [root@localhost ~]# i2cdetect -l i2c-0 i2c Geni-I2C I2C adapter i2c-1 i2c Geni-I2C I2C adapter i2c-12 i2c Geni-I2C I2C adapter i2c-15 i2c Geni-I2C I2C adapter i2c-18 i2c Geni-I2C I2C adapter [root@localhost ~]# i2cdetect -a -y 15 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Signed-off-by: Brian Masney Reviewed-by: Konrad Dybcio Tested-by: Shazad Hussain --- Changes since v1: - Dropped qupX_ prefix from labels. (Johan) - Reordered nodes based on new name. - Added i2c buses 0, 1, and 12 (Shazad) - Drop mux/config-pins and have the pin properties live directly under the i2cX-default-state node. (Konrad) - Use decimal notation for drive strength (Johan) A few things to note with this series applied on top of linux-next: - Reading from i2c-0 using 'i2cdetect -y -a 0' gives the following error when reading from the ranges 0x30-0x37 and 0x50-0x5F. geni_i2c 980000.i2c: Timeout abort_m_cmd - i2c-1 and i2c-2 successfully read using i2cdetect, however it takes several seconds. - i2cdetect runs fast within a small fraction of a second for i2c-15 and i2c18. - 'i2cdetect -y -a $BUSNUM' shows the same address ranges 0x30-0x37 and 0x50-0x5F in use on all 5 buses. arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 83 +++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8540p-ride.dts index b6e0db5508c7..ccd2ea3c9d04 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -17,6 +17,11 @@ / { compatible =3D "qcom,sa8540p-ride", "qcom,sa8540p"; =20 aliases { + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c12 =3D &i2c12; + i2c15 =3D &i2c15; + i2c18 =3D &i2c18; serial0 =3D &uart17; }; =20 @@ -146,6 +151,41 @@ vreg_l8g: ldo8 { }; }; =20 +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_default>; + + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_default>; + + status =3D "okay"; +}; + +&i2c12 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c12_default>; + + status =3D "okay"; +}; + +&i2c15 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c15_default>; + + status =3D "okay"; +}; + +&i2c18 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c18_default>; + + status =3D "okay"; +}; + &pcie2a { ranges =3D <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, @@ -188,6 +228,14 @@ &pcie3a_phy { status =3D "okay"; }; =20 +&qup0 { + status =3D "okay"; +}; + +&qup1 { + status =3D "okay"; +}; + &qup2 { status =3D "okay"; }; @@ -268,6 +316,41 @@ &xo_board_clk { /* PINCTRL */ =20 &tlmm { + i2c0_default: i2c0-default-state { + pins =3D "gpio135", "gpio136"; + function =3D "qup15"; + drive-strength =3D <2>; + bias-pull-up; + }; + + i2c1_default: i2c1-default-state { + pins =3D "gpio158", "gpio159"; + function =3D "qup15"; + drive-strength =3D <2>; + bias-pull-up; + }; + + i2c12_default: i2c12-default-state { + pins =3D "gpio0", "gpio1"; + function =3D "qup15"; + drive-strength =3D <2>; + bias-pull-up; + }; + + i2c15_default: i2c15-default-state { + pins =3D "gpio36", "gpio37"; + function =3D "qup15"; + drive-strength =3D <2>; + bias-pull-up; + }; + + i2c18_default: i2c18-default-state { + pins =3D "gpio66", "gpio67"; + function =3D "qup18"; + drive-strength =3D <2>; + bias-pull-up; + }; + pcie2a_default: pcie2a-default-state { perst-pins { pins =3D "gpio143"; --=20 2.38.1 From nobody Wed Sep 17 22:18:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCF42C4167B for ; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id t30-20020a37ea1e000000b006eef13ef4c8sm10305477qkj.94.2022.12.14.09.12.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 09:12:06 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: quic_shazhuss@quicinc.com, konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com Subject: [PATCH v2 7/7] arm64: dts: qcom: sc8280xp: add rng device tree node Date: Wed, 14 Dec 2022 12:11:45 -0500 Message-Id: <20221214171145.2913557-8-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221214171145.2913557-1-bmasney@redhat.com> References: <20221214171145.2913557-1-bmasney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the necessary device tree node for qcom,prng-ee so we can use the hardware random number generator. This functionality was tested on a SA8540p automotive development board using kcapi-rng from libkcapi. Signed-off-by: Brian Masney --- This is a new patch that's introduced in v2. arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 4591d411f5fb..67765975361b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2811,6 +2811,13 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 230>; }; =20 + rng: rng@10d3000 { + compatible =3D "qcom,prng-ee"; + reg =3D <0 0x010d3000 0 0x1000>; + clocks =3D <&rpmhcc RPMH_HWKM_CLK>; + clock-names =3D "core"; + }; + apps_smmu: iommu@15000000 { compatible =3D "qcom,sc8280xp-smmu-500", "arm,mmu-500"; reg =3D <0 0x15000000 0 0x100000>; --=20 2.38.1