From nobody Wed Sep 17 22:20:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12908C4332F for ; Wed, 14 Dec 2022 14:27:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238709AbiLNO1b (ORCPT ); Wed, 14 Dec 2022 09:27:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238651AbiLNO1L (ORCPT ); Wed, 14 Dec 2022 09:27:11 -0500 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB54A20362; Wed, 14 Dec 2022 06:27:09 -0800 (PST) Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BEBT0Yp014299; Wed, 14 Dec 2022 09:26:51 -0500 Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 3mf6rntscd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Dec 2022 09:26:51 -0500 Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 2BEEQoUw004498 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 14 Dec 2022 09:26:50 -0500 Received: from ASHBCASHYB4.ad.analog.com (10.64.17.132) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Wed, 14 Dec 2022 09:26:48 -0500 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Wed, 14 Dec 2022 09:26:48 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Wed, 14 Dec 2022 09:26:48 -0500 Received: from IST-LT-40003.ad.analog.com (IST-LT-40003.ad.analog.com [10.25.36.26]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 2BEEQLNC022112; Wed, 14 Dec 2022 09:26:39 -0500 From: Sinan Divarci To: , , , CC: , , , Sinan Divarci Subject: [PATCH v2 1/3] drivers: hwmon: Add max31732 quad remote temperature sensor driver Date: Wed, 14 Dec 2022 17:22:04 +0300 Message-ID: <20221214142206.13288-2-Sinan.Divarci@analog.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221214142206.13288-1-Sinan.Divarci@analog.com> References: <20221214142206.13288-1-Sinan.Divarci@analog.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-ORIG-GUID: fCWgx-8A3bOPM3D5mA9O1_jw2YDhQWWI X-Proofpoint-GUID: fCWgx-8A3bOPM3D5mA9O1_jw2YDhQWWI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-14_06,2022-12-14_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 suspectscore=0 adultscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 phishscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212140114 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The MAX31732 is a multi-channel temperature sensor that monitors its own temperature and the temperatures of up to four external diodeconnected transistors. The MAX31732 offers two open-drain, active-low alarm outputs, ALARM1 and ALARM2. When the measured temperature of a channel crosses the respective primary over/under temperature threshold levels ALARM1 asserts low and a status bit is set in the corresponding thermal status registers. When the measured temperature of a channel crosses the secondary over/under temperature threshold levels, ALARM2 asserts low and a status bit is set in the corresponding thermal status registers. Signed-off-by: Sinan Divarci --- drivers/hwmon/Kconfig | 11 + drivers/hwmon/Makefile | 1 + drivers/hwmon/max31732.c | 620 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 632 insertions(+) create mode 100644 drivers/hwmon/max31732.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 3176c33af..f498f3867 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1076,6 +1076,17 @@ config SENSORS_MAX31730 This driver can also be built as a module. If so, the module will be called max31730. =20 +config SENSORS_MAX31732 + tristate "MAX31732 temperature sensor" + depends on I2C + select REGMAP_I2C + help + Support for the Analog Devices MAX31732 4-Channel Remote + Temperature Sensor. + + This driver can also be built as a module. If so, the module + will be called max31732. + config SENSORS_MAX31760 tristate "MAX31760 fan speed controller" depends on I2C diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index e2e4e87b2..6b2871cc5 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -140,6 +140,7 @@ obj-$(CONFIG_SENSORS_MAX1668) +=3D max1668.o obj-$(CONFIG_SENSORS_MAX197) +=3D max197.o obj-$(CONFIG_SENSORS_MAX31722) +=3D max31722.o obj-$(CONFIG_SENSORS_MAX31730) +=3D max31730.o +obj-$(CONFIG_SENSORS_MAX31732) +=3D max31732.o obj-$(CONFIG_SENSORS_MAX31760) +=3D max31760.o obj-$(CONFIG_SENSORS_MAX6620) +=3D max6620.o obj-$(CONFIG_SENSORS_MAX6621) +=3D max6621.o diff --git a/drivers/hwmon/max31732.c b/drivers/hwmon/max31732.c new file mode 100644 index 000000000..cf075c990 --- /dev/null +++ b/drivers/hwmon/max31732.c @@ -0,0 +1,620 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for MAX31732 4-Channel Remote Temperature Sensor + */ + +#include +#include +#include +#include + +/* common definitions*/ +#define MAX3173X_STOP BIT(7) +#define MAX3173X_ALARM_MODE BIT(4) +#define MAX3173X_ALARM_FAULT_QUEUE_MASK GENMASK(3, 2) +#define MAX3173X_EXTRANGE BIT(1) +#define MAX3173X_TEMP_OFFSET_BASELINE 0x77 +#define MAX3173X_TEMP_MIN (-128000) +#define MAX3173X_TEMP_MAX 127937 +#define MAX3173X_OFFSET_MIN (-14875) +#define MAX3173X_OFFSET_MAX 17000 +#define MAX3173X_OFFSET_ZERO 14875 +#define MAX31732_SECOND_TEMP_MIN (-128000) +#define MAX31732_SECOND_TEMP_MAX 127000 +#define MAX31732_CUSTOM_OFFSET_RES 125 +#define MAX31732_ALL_CHANNEL_MASK 0x1F +#define MAX31732_ALARM_INT_MODE 0 +#define MAX31732_ALARM_COMP_MODE 1 +#define MAX31732_ALARM_FAULT_QUE 1 +#define MAX31732_ALARM_FAULT_QUE_MAX 3 + +/* The MAX31732 registers */ +#define MAX31732_REG_TEMP_R 0x02 +#define MAX31732_REG_TEMP_L 0x0A +#define MAX31732_REG_PRIM_HIGH_STATUS 0x0C +#define MAX31732_REG_PRIM_LOW_STATUS 0x0D +#define MAX31732_REG_CHANNEL_ENABLE 0x0E +#define MAX31732_REG_CONF1 0x0F +#define MAX31732_REG_CONF2 0x10 +#define MAX31732_REG_TEMP_OFFSET 0x16 +#define MAX31732_REG_OFFSET_ENABLE 0x17 +#define MAX31732_REG_ALARM1_MASK 0x1B +#define MAX31732_REG_ALARM2_MASK 0x1C +#define MAX31732_REG_PRIM_HIGH_TEMP_R 0x1D +#define MAX31732_REG_PRIM_HIGH_TEMP_L 0x25 +#define MAX31732_REG_PRIM_LOW_TEMP 0x27 +#define MAX31732_REG_SECOND_HIGH_TEMP_R 0x29 +#define MAX31732_REG_SECOND_HIGH_TEMP_L 0x2D +#define MAX31732_REG_SECOND_LOW_TEMP 0x2E +#define MAX31732_REG_SECOND_HIGH_STATUS 0x42 +#define MAX31732_REG_SECOND_LOW_STATUS 0x43 +#define MAX31732_REG_TEMP_FAULT 0x44 + +enum max31732_temp_type { + MAX31732_TEMP, + MAX31732_PRIM_HIGH, + MAX31732_SECOND_HIGH +}; + +struct max31732_data { + struct i2c_client *client; + struct device *hwmon_dev; + struct regmap *regmap; + s32 irqs[2]; +}; + +static u32 max31732_get_temp_reg(enum max31732_temp_type temp_type, u32 ch= annel) +{ + switch (temp_type) { + case MAX31732_PRIM_HIGH: + if (channel =3D=3D 0) + return MAX31732_REG_PRIM_HIGH_TEMP_L; + else + return (MAX31732_REG_PRIM_HIGH_TEMP_R + (channel - 1) * 2); + break; + case MAX31732_SECOND_HIGH: + if (channel =3D=3D 0) + return MAX31732_REG_SECOND_HIGH_TEMP_L; + else + return (MAX31732_REG_SECOND_HIGH_TEMP_R + (channel - 1)); + break; + case MAX31732_TEMP: + default: + if (channel =3D=3D 0) + return MAX31732_REG_TEMP_L; + else + return (MAX31732_REG_TEMP_R + (channel - 1) * 2); + break; + } +} + +static bool max31732_volatile_reg(struct device *dev, u32 reg) +{ + if (reg >=3D MAX31732_REG_TEMP_R && reg <=3D MAX31732_REG_PRIM_LOW_STATUS) + return true; + + if (reg =3D=3D MAX31732_REG_SECOND_HIGH_STATUS || reg =3D=3D MAX31732_REG= _SECOND_LOW_STATUS) + return true; + + if (reg =3D=3D MAX31732_REG_TEMP_FAULT) + return true; + + return false; +} + +static const struct regmap_config regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .cache_type =3D REGCACHE_RBTREE, + .volatile_reg =3D max31732_volatile_reg, +}; + +static inline long max31732_reg_to_mc(s16 temp) +{ + return DIV_ROUND_CLOSEST((temp / 16) * 1000, 16); +} + +static int max31732_read(struct device *dev, enum hwmon_sensor_types type,= u32 attr, s32 channel, + long *val) +{ + struct max31732_data *data =3D dev_get_drvdata(dev); + s32 ret; + u32 reg_val, reg_addr; + s16 temp_reg_val; + u8 regs[2]; + + if (type !=3D hwmon_temp) + return -EINVAL; + + switch (attr) { + case hwmon_temp_input: + ret =3D regmap_test_bits(data->regmap, MAX31732_REG_CHANNEL_ENABLE, BIT(= channel)); + if (ret < 0) + return ret; + + if (!ret) + return -ENODATA; + + reg_addr =3D max31732_get_temp_reg(MAX31732_TEMP, channel); + break; + case hwmon_temp_max: + reg_addr =3D max31732_get_temp_reg(MAX31732_PRIM_HIGH, channel); + break; + case hwmon_temp_min: + reg_addr =3D MAX31732_REG_PRIM_LOW_TEMP; + break; + case hwmon_temp_lcrit: + ret =3D regmap_read(data->regmap, MAX31732_REG_SECOND_LOW_TEMP, ®_val= ); + if (ret) + return ret; + + *val =3D reg_val * 1000; + return 0; + case hwmon_temp_crit: + reg_addr =3D max31732_get_temp_reg(MAX31732_SECOND_HIGH, channel); + ret =3D regmap_read(data->regmap, reg_addr, ®_val); + if (ret) + return ret; + + *val =3D reg_val * 1000; + return 0; + case hwmon_temp_enable: + ret =3D regmap_test_bits(data->regmap, MAX31732_REG_CHANNEL_ENABLE, BIT(= channel)); + if (ret < 0) + return ret; + + *val =3D ret; + return 0; + case hwmon_temp_offset: + if (channel =3D=3D 0) + return -EINVAL; + + ret =3D regmap_test_bits(data->regmap, MAX31732_REG_OFFSET_ENABLE, BIT(c= hannel)); + if (ret < 0) + return ret; + + if (!ret) + return 0; + + ret =3D regmap_read(data->regmap, MAX31732_REG_TEMP_OFFSET, ®_val); + if (ret) + return ret; + + *val =3D (reg_val - MAX3173X_TEMP_OFFSET_BASELINE) * MAX31732_CUSTOM_OFF= SET_RES; + return 0; + case hwmon_temp_fault: + ret =3D regmap_test_bits(data->regmap, MAX31732_REG_TEMP_FAULT, BIT(chan= nel)); + if (ret < 0) + return ret; + + *val =3D ret; + return 0; + case hwmon_temp_lcrit_alarm: + ret =3D regmap_test_bits(data->regmap, MAX31732_REG_SECOND_LOW_STATUS, B= IT(channel)); + if (ret < 0) + return ret; + + *val =3D ret; + return 0; + case hwmon_temp_min_alarm: + ret =3D regmap_test_bits(data->regmap, MAX31732_REG_PRIM_LOW_STATUS, BIT= (channel)); + if (ret < 0) + return ret; + + *val =3D ret; + return 0; + case hwmon_temp_max_alarm: + ret =3D regmap_test_bits(data->regmap, MAX31732_REG_PRIM_HIGH_STATUS, BI= T(channel)); + if (ret < 0) + return ret; + + *val =3D ret; + return 0; + case hwmon_temp_crit_alarm: + ret =3D regmap_test_bits(data->regmap, MAX31732_REG_SECOND_HIGH_STATUS, = BIT(channel)); + if (ret < 0) + return ret; + + *val =3D ret; + return 0; + default: + return -EINVAL; + } + + ret =3D regmap_bulk_read(data->regmap, reg_addr, ®s, 2); + if (ret < 0) + return ret; + + temp_reg_val =3D regs[1] | regs[0] << 8; + *val =3D max31732_reg_to_mc(temp_reg_val); + return 0; +} + +static int max31732_write(struct device *dev, enum hwmon_sensor_types type= , u32 attr, s32 channel, + long val) +{ + struct max31732_data *data =3D dev_get_drvdata(dev); + s32 reg_addr, ret; + u16 temp_reg_val; + + if (type !=3D hwmon_temp) + return -EINVAL; + + switch (attr) { + case hwmon_temp_max: + reg_addr =3D max31732_get_temp_reg(MAX31732_PRIM_HIGH, channel); + break; + case hwmon_temp_min: + reg_addr =3D MAX31732_REG_PRIM_LOW_TEMP; + break; + case hwmon_temp_enable: + if (val =3D=3D 0) { + return regmap_clear_bits(data->regmap, MAX31732_REG_CHANNEL_ENABLE, + BIT(channel)); + } else if (val =3D=3D 1) { + return regmap_set_bits(data->regmap, MAX31732_REG_CHANNEL_ENABLE, + BIT(channel)); + } else { + return -EINVAL; + } + case hwmon_temp_offset: + val =3D clamp_val(val, MAX3173X_OFFSET_MIN, MAX3173X_OFFSET_MAX) + + MAX3173X_OFFSET_ZERO; + val =3D DIV_ROUND_CLOSEST(val, 125); + + if (val =3D=3D MAX3173X_TEMP_OFFSET_BASELINE) { + ret =3D regmap_clear_bits(data->regmap, MAX31732_REG_OFFSET_ENABLE, + BIT(channel)); + } else { + ret =3D regmap_set_bits(data->regmap, MAX31732_REG_OFFSET_ENABLE, + BIT(channel)); + } + if (ret) + return ret; + + return regmap_write(data->regmap, MAX31732_REG_TEMP_OFFSET, val); + case hwmon_temp_crit: + val =3D clamp_val(val, MAX31732_SECOND_TEMP_MIN, MAX31732_SECOND_TEMP_MA= X); + val =3D DIV_ROUND_CLOSEST(val, 1000); + reg_addr =3D max31732_get_temp_reg(MAX31732_SECOND_HIGH, channel); + return regmap_write(data->regmap, reg_addr, val); + case hwmon_temp_lcrit: + val =3D clamp_val(val, MAX31732_SECOND_TEMP_MIN, MAX31732_SECOND_TEMP_MA= X); + val =3D DIV_ROUND_CLOSEST(val, 1000); + return regmap_write(data->regmap, MAX31732_REG_SECOND_LOW_TEMP, val); + default: + return -EINVAL; + } + + val =3D clamp_val(val, MAX3173X_TEMP_MIN, MAX3173X_TEMP_MAX); + val =3D DIV_ROUND_CLOSEST(val << 4, 1000) << 4; + + temp_reg_val =3D (u16)val; + temp_reg_val =3D swab16(temp_reg_val); + + return regmap_bulk_write(data->regmap, reg_addr, &temp_reg_val, sizeof(te= mp_reg_val)); +} + +static umode_t max31732_is_visible(const void *data, enum hwmon_sensor_typ= es type, u32 attr, + s32 channel) +{ + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + case hwmon_temp_lcrit_alarm: + case hwmon_temp_min_alarm: + case hwmon_temp_max_alarm: + case hwmon_temp_crit_alarm: + case hwmon_temp_fault: + return 0444; + case hwmon_temp_min: + case hwmon_temp_lcrit: + return channel ? 0444 : 0644; + case hwmon_temp_offset: + case hwmon_temp_enable: + case hwmon_temp_max: + case hwmon_temp_crit: + return 0644; + } + break; + default: + break; + } + return 0; +} + +static irqreturn_t max31732_irq_handler(s32 irq, void *data) +{ + struct device *dev =3D data; + struct max31732_data *drvdata =3D dev_get_drvdata(dev); + s32 ret; + u32 reg_val; + bool reported =3D false; + + ret =3D regmap_read(drvdata->regmap, MAX31732_REG_PRIM_HIGH_STATUS, ®_= val); + if (ret) + return ret; + + if (reg_val !=3D 0) { + dev_crit(dev, "Primary Overtemperature Alarm, R4:%d R3:%d R2:%d R1:%d L:= %d.\n", + !!(reg_val & BIT(4)), !!(reg_val & BIT(3)), !!(reg_val & BIT(2)), + !!(reg_val & BIT(1)), !!(reg_val & BIT(0))); + hwmon_notify_event(drvdata->hwmon_dev, hwmon_temp, hwmon_temp_max_alarm,= 0); + reported =3D true; + } + + ret =3D regmap_read(drvdata->regmap, MAX31732_REG_PRIM_LOW_STATUS, ®_v= al); + if (ret) + return ret; + + if (reg_val !=3D 0) { + dev_crit(dev, "Primary Undertemperature Alarm, R4:%d R3:%d R2:%d R1:%d L= :%d.\n", + !!(reg_val & BIT(4)), !!(reg_val & BIT(3)), !!(reg_val & BIT(2)), + !!(reg_val & BIT(1)), !!(reg_val & BIT(0))); + hwmon_notify_event(drvdata->hwmon_dev, hwmon_temp, hwmon_temp_min_alarm,= 0); + reported =3D true; + } + + ret =3D regmap_read(drvdata->regmap, MAX31732_REG_SECOND_HIGH_STATUS, &re= g_val); + if (ret) + return ret; + + if (reg_val !=3D 0) { + dev_crit(dev, "Secondary Overtemperature Alarm, R4:%d R3:%d R2:%d R1:%d = L:%d.\n", + !!(reg_val & BIT(4)), !!(reg_val & BIT(3)), !!(reg_val & BIT(2)), + !!(reg_val & BIT(1)), !!(reg_val & BIT(0))); + hwmon_notify_event(drvdata->hwmon_dev, hwmon_temp, hwmon_temp_crit_alarm= , 0); + reported =3D true; + } + + ret =3D regmap_read(drvdata->regmap, MAX31732_REG_SECOND_LOW_STATUS, ®= _val); + if (ret) + return ret; + + if (reg_val !=3D 0) { + dev_crit(dev, "Secondary Undertemperature Alarm, R4:%d R3:%d R2:%d R1:%d= L:%d.\n", + !!(reg_val & BIT(4)), !!(reg_val & BIT(3)), !!(reg_val & BIT(2)), + !!(reg_val & BIT(1)), !!(reg_val & BIT(0))); + hwmon_notify_event(drvdata->hwmon_dev, hwmon_temp, hwmon_temp_lcrit_alar= m, 0); + reported =3D true; + } + + if (!reported) { + if (irq =3D=3D drvdata->irqs[0]) + dev_err(dev, "ALARM1 interrupt received but status registers not set.\n= "); + else if (irq =3D=3D drvdata->irqs[1]) + dev_err(dev, "ALARM2 interrupt received but status registers not set.\n= "); + else + dev_err(dev, "Undefined interrupt source.\n"); + } + + return IRQ_HANDLED; +} + +static const struct hwmon_channel_info *max31732_info[] =3D { + HWMON_CHANNEL_INFO(chip, + HWMON_C_REGISTER_TZ), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | HWMON_T_LCRIT | + HWMON_T_CRIT | + HWMON_T_ENABLE | + HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | + HWMON_T_LCRIT_ALARM, + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | HWMON_T_LCRIT | + HWMON_T_CRIT | + HWMON_T_OFFSET | HWMON_T_ENABLE | + HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | + HWMON_T_LCRIT_ALARM | + HWMON_T_FAULT, + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | HWMON_T_LCRIT | + HWMON_T_CRIT | + HWMON_T_OFFSET | HWMON_T_ENABLE | + HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | + HWMON_T_LCRIT_ALARM | + HWMON_T_FAULT, + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | HWMON_T_LCRIT | + HWMON_T_CRIT | + HWMON_T_OFFSET | HWMON_T_ENABLE | + HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | + HWMON_T_LCRIT_ALARM | + HWMON_T_FAULT, + HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX | HWMON_T_LCRIT | + HWMON_T_CRIT | + HWMON_T_OFFSET | HWMON_T_ENABLE | + HWMON_T_MIN_ALARM | HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | + HWMON_T_LCRIT_ALARM | + HWMON_T_FAULT + ), + NULL +}; + +static const struct hwmon_ops max31732_hwmon_ops =3D { + .is_visible =3D max31732_is_visible, + .read =3D max31732_read, + .write =3D max31732_write, +}; + +static const struct hwmon_chip_info max31732_chip_info =3D { + .ops =3D &max31732_hwmon_ops, + .info =3D max31732_info, +}; + +static int max31732_parse_alarms(struct device *dev, struct max31732_data = *data) +{ + s32 ret; + u32 alarm_que; + + if (fwnode_property_read_bool(dev_fwnode(dev), "adi,alarm1-interrupt-mode= ")) + ret =3D regmap_clear_bits(data->regmap, MAX31732_REG_CONF1, MAX3173X_ALA= RM_MODE); + else + ret =3D regmap_set_bits(data->regmap, MAX31732_REG_CONF1, MAX3173X_ALARM= _MODE); + + if (ret) + return ret; + + if (fwnode_property_read_bool(dev_fwnode(dev), "adi,alarm2-interrupt-mode= ")) + ret =3D regmap_clear_bits(data->regmap, MAX31732_REG_CONF2, MAX3173X_ALA= RM_MODE); + else + ret =3D regmap_set_bits(data->regmap, MAX31732_REG_CONF2, MAX3173X_ALARM= _MODE); + + if (ret) + return ret; + + alarm_que =3D MAX31732_ALARM_FAULT_QUE; + fwnode_property_read_u32(dev_fwnode(dev), "adi,alarm1-fault-queue", &alar= m_que); + + if ((alarm_que / 2) <=3D MAX31732_ALARM_FAULT_QUE_MAX) { + ret =3D regmap_write_bits(data->regmap, MAX31732_REG_CONF1, + MAX3173X_ALARM_FAULT_QUEUE_MASK, + FIELD_PREP(MAX3173X_ALARM_FAULT_QUEUE_MASK, + (alarm_que / 2))); + if (ret) + return ret; + } else { + return dev_err_probe(dev, -EINVAL, "Invalid adi,alarm1-fault-queue.\n"); + } + + alarm_que =3D MAX31732_ALARM_FAULT_QUE; + fwnode_property_read_u32(dev_fwnode(dev), "adi,alarm2-fault-queue", &alar= m_que); + + if ((alarm_que / 2) <=3D MAX31732_ALARM_FAULT_QUE_MAX) { + ret =3D regmap_write_bits(data->regmap, MAX31732_REG_CONF2, + MAX3173X_ALARM_FAULT_QUEUE_MASK, + FIELD_PREP(MAX3173X_ALARM_FAULT_QUEUE_MASK, + (alarm_que / 2))); + } else { + return dev_err_probe(dev, -EINVAL, "Invalid adi,alarm2-fault-queue.\n"); + } + + return ret; +} + +static int max31732_probe(struct i2c_client *client) +{ + struct device *dev =3D &client->dev; + struct max31732_data *data; + s32 ret; + u32 reg_val; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->client =3D client; + + data->regmap =3D devm_regmap_init_i2c(client, ®map_config); + if (IS_ERR(data->regmap)) + return dev_err_probe(dev, PTR_ERR(data->regmap), "regmap init failed\n"); + + ret =3D regmap_read(data->regmap, MAX31732_REG_CHANNEL_ENABLE, ®_val); + if (ret) + return ret; + + if (reg_val =3D=3D 0) + ret =3D regmap_set_bits(data->regmap, MAX31732_REG_CONF1, MAX3173X_STOP); + else + ret =3D regmap_clear_bits(data->regmap, MAX31732_REG_CONF1, MAX3173X_STO= P); + + if (ret) + return ret; + + ret =3D regmap_clear_bits(data->regmap, MAX31732_REG_CONF1, MAX3173X_EXTR= ANGE); + if (ret) + return ret; + + ret =3D max31732_parse_alarms(dev, data); + if (ret) + return ret; + + dev_set_drvdata(dev, data); + + data->irqs[0] =3D fwnode_irq_get_byname(dev_fwnode(dev), "ALARM1"); + if (data->irqs[0] > 0) { + ret =3D devm_request_threaded_irq(dev, data->irqs[0], NULL, max31732_irq= _handler, + IRQF_ONESHOT, client->name, dev); + if (ret) + return dev_err_probe(dev, ret, "cannot request irq\n"); + + ret =3D regmap_set_bits(data->regmap, MAX31732_REG_ALARM1_MASK, + MAX31732_ALL_CHANNEL_MASK); + if (ret) + return ret; + } else { + ret =3D regmap_clear_bits(data->regmap, MAX31732_REG_ALARM1_MASK, + MAX31732_ALL_CHANNEL_MASK); + if (ret) + return ret; + } + + data->irqs[1] =3D fwnode_irq_get_byname(dev_fwnode(dev), "ALARM2"); + if (data->irqs[1] > 0) { + ret =3D devm_request_threaded_irq(dev, data->irqs[1], NULL, max31732_irq= _handler, + IRQF_ONESHOT, client->name, dev); + if (ret) + return dev_err_probe(dev, ret, "cannot request irq\n"); + + ret =3D regmap_set_bits(data->regmap, MAX31732_REG_ALARM2_MASK, + MAX31732_ALL_CHANNEL_MASK); + if (ret) + return ret; + } else { + ret =3D regmap_clear_bits(data->regmap, MAX31732_REG_ALARM2_MASK, + MAX31732_ALL_CHANNEL_MASK); + if (ret) + return ret; + } + + data->hwmon_dev =3D devm_hwmon_device_register_with_info(dev, client->nam= e, data, + &max31732_chip_info, NULL); + + return PTR_ERR_OR_ZERO(data->hwmon_dev); +} + +static const struct i2c_device_id max31732_ids[] =3D { + { "max31732" }, + { }, +}; + +MODULE_DEVICE_TABLE(i2c, max31732_ids); + +static const struct of_device_id __maybe_unused max31732_of_match[] =3D { + { .compatible =3D "adi,max31732", }, + { }, +}; + +MODULE_DEVICE_TABLE(of, max31732_of_match); + +static int __maybe_unused max31732_suspend(struct device *dev) +{ + struct max31732_data *data =3D dev_get_drvdata(dev); + + return regmap_set_bits(data->regmap, MAX31732_REG_CONF1, MAX3173X_STOP); +} + +static int __maybe_unused max31732_resume(struct device *dev) +{ + struct max31732_data *data =3D dev_get_drvdata(dev); + + return regmap_clear_bits(data->regmap, MAX31732_REG_CONF1, MAX3173X_STOP); +} + +static SIMPLE_DEV_PM_OPS(max31732_pm_ops, max31732_suspend, max31732_resum= e); + +static struct i2c_driver max31732_driver =3D { + .class =3D I2C_CLASS_HWMON, + .driver =3D { + .name =3D "max31732-driver", + .of_match_table =3D of_match_ptr(max31732_of_match), + .pm =3D &max31732_pm_ops, + }, + .probe_new =3D max31732_probe, + .id_table =3D max31732_ids, +}; + +module_i2c_driver(max31732_driver); + +MODULE_AUTHOR("Sinan Divarci "); +MODULE_DESCRIPTION("MAX31732 driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); --=20 2.25.1 From nobody Wed Sep 17 22:20:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31CE8C001B2 for ; Wed, 14 Dec 2022 14:27:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238714AbiLNO1e (ORCPT ); Wed, 14 Dec 2022 09:27:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238675AbiLNO1U (ORCPT ); Wed, 14 Dec 2022 09:27:20 -0500 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7103227B02; Wed, 14 Dec 2022 06:27:13 -0800 (PST) Received: from pps.filterd (m0167088.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2BEBCYgP006823; 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Wed, 14 Dec 2022 09:26:54 -0500 Received: from IST-LT-40003.ad.analog.com (IST-LT-40003.ad.analog.com [10.25.36.26]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 2BEEQLND022112; Wed, 14 Dec 2022 09:26:44 -0500 From: Sinan Divarci To: , , , CC: , , , Sinan Divarci Subject: [PATCH v2 2/3] docs: hwmon: add max31732 documentation Date: Wed, 14 Dec 2022 17:22:05 +0300 Message-ID: <20221214142206.13288-3-Sinan.Divarci@analog.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221214142206.13288-1-Sinan.Divarci@analog.com> References: <20221214142206.13288-1-Sinan.Divarci@analog.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: SuS4rJQ4cQAaAUE6GLHZtto4J7ph7VrE X-Proofpoint-ORIG-GUID: SuS4rJQ4cQAaAUE6GLHZtto4J7ph7VrE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-14_06,2022-12-14_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2212140114 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adding documentation for max31732 quad remote temperature sensor Signed-off-by: Sinan Divarci --- Documentation/hwmon/index.rst | 1 + Documentation/hwmon/max31732.rst | 62 ++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 Documentation/hwmon/max31732.rst diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst index fe2cc6b73..e521bf555 100644 --- a/Documentation/hwmon/index.rst +++ b/Documentation/hwmon/index.rst @@ -133,6 +133,7 @@ Hardware Monitoring Kernel Drivers max20751 max31722 max31730 + max31732 max31760 max31785 max31790 diff --git a/Documentation/hwmon/max31732.rst b/Documentation/hwmon/max3173= 2.rst new file mode 100644 index 000000000..67bfcf393 --- /dev/null +++ b/Documentation/hwmon/max31732.rst @@ -0,0 +1,62 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Kernel driver max31732 +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Supported chips: + + * Analog Devices MAX31732 + + Prefix: 'max31732' + + Addresses scanned: none + +Author: Sinan Divarci + + +Description +----------- + +This driver implements support for Maxim MAX31732. + +The MAX31732 is a multi-channel temperature sensor that monitors its +own temperature and the temperatures of up to four external diodeconnected +transistors. The device operates with 3.0V to 3.6V supply range +and consume TBD=CE=BCA of current in standby mode of operation. Resistance +cancellation feature compensates for high series resistance between +circuit-board traces and the external thermal diode, while beta +compensation corrects for temperature-measurement errors due to lowbeta +sensing transistors. + +The MAX31732 offers two open-drain, active-low alarm outputs, +ALARM1 and ALARM2. When the measured temperature of a channel +crosses the respective primary over/under temperature threshold levels +ALARM1 asserts low and a status bit is set in the corresponding thermal +status registers. When the measured temperature of a channel crosses the +secondary over/under temperature threshold levels, ALARM2 asserts low +and a status bit is set in the corresponding thermal status registers. + +Temperature measurement range: from -64=C2=B0C to 150=C2=B0C + +Temperature Resolution: 12 Bits, =C2=B10.0625=C2=B0C + +Sysfs entries +------------- + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +temp[1-5]_enable RW Temperature enable/disable + Set to 1 to enable channel, 0 to disable +temp[1-5]_input RO Temperature input +temp[2-5]_fault RO Fault indicator for remote channels +temp[1-5]_max RW Temperature max value. Asserts "ALARM1" pin when = exceeded +temp[1-5]_max_alarm RO Temperature max alarm status +temp[1-5]_crit RW Temperature critical value. Asserts "ALARM2" pin = when exceeded +temp[1-5]_crit_alarm RO Temperature critical alarm status +temp[1-5]_min RW Temperature min value. Common for all channels. + Only temp1_min is writeable. Asserts "ALARM1" pin= when exceeded +temp[1-5]_min_alarm RO Temperature min alarm status +temp[1-5]_lcrit RW Temperature critical low value. Common for all ch= annels. + Only temp1_min is writeable. Asserts "ALARM2" pin= when exceeded +temp[1-5]_lcrit_alarm RO Temperature critical low alarm status +temp[2-5]_offset RW Temperature offset for remote channels +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D --=20 2.25.1 From nobody Wed Sep 17 22:20:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDF97C4332F for ; Wed, 14 Dec 2022 14:27:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238740AbiLNO1v (ORCPT ); Wed, 14 Dec 2022 09:27:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238663AbiLNO1X (ORCPT ); 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charset="utf-8" Adding bindings for max31732 quad remote temperature sensor Signed-off-by: Sinan Divarci --- .../bindings/hwmon/adi,max31732.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/adi,max31732.ya= ml diff --git a/Documentation/devicetree/bindings/hwmon/adi,max31732.yaml b/Do= cumentation/devicetree/bindings/hwmon/adi,max31732.yaml new file mode 100644 index 000000000..c701cda95 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/adi,max31732.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2022 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/adi,max31732.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices MAX31732 Temperature Sensor Device Driver + +maintainers: + - Sinan Divarci + +description: Bindings for the Analog Devices MAX31732 Temperature Sensor D= evice. + +properties: + compatible: + enum: + - adi,max31732 + + reg: + description: I2C address of the Temperature Sensor Device. + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + description: Name of the interrupt pin of max31732 used for IRQ. + minItems: 1 + items: + - enum: [ALARM1, ALARM2] + - enum: [ALARM1, ALARM2] + + adi,alarm1-interrupt-mode: + description: | + Enables the ALARM1 output to function in interrupt mode. + Default ALARM1 output function is comparator mode. + type: boolean + + adi,alarm2-interrupt-mode: + description: | + Enables the ALARM2 output to function in interrupt mode. + Default ALARM2 output function is comparator mode. + type: boolean + + adi,alarm1-fault-queue: + description: The number of consecutive faults required to assert ALARM= 1. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 6] + default: 1 + + adi,alarm2-fault-queue: + description: The number of consecutive faults required to assert ALARM= 2. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 6] + default: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + sensor@1c { + compatible =3D "adi,max31732"; + reg =3D <0x1c>; + interrupt-parent =3D <&gpio>; + interrupts =3D <17 IRQ_TYPE_EDGE_BOTH>, <27 IRQ_TYPE_EDGE_BOTH= >; + interrupt-names =3D "ALARM1", "ALARM2"; + adi,alarm1-fault-queue =3D <4>; + adi,alarm2-fault-queue =3D <2>; + adi,alarm2-interrupt-mode; + }; + }; --=20 2.25.1