From nobody Wed Sep 17 22:19:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7452BC46467 for ; Wed, 14 Dec 2022 11:42:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238276AbiLNLl5 (ORCPT ); Wed, 14 Dec 2022 06:41:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229592AbiLNLlv (ORCPT ); Wed, 14 Dec 2022 06:41:51 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85D0B1007C; Wed, 14 Dec 2022 03:41:49 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id i7so4365182wrv.8; Wed, 14 Dec 2022 03:41:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ns4iM9T1bOBC02dlnDL65OgFGuOFjTz8LmgOUq5fuL0=; b=ahLslNDU38JJlBqUtnI3xSjk1kOFeS/pggtpOaTJc7WfzQ06i1KmUvnMBNvMr6hzID gMEVbVIdO3uVOnYWRu06TG4PxliNtL8ezZzMToMpsft8UZwGPTl1F7dKSVONuCUGy0Bj lPoicGj6kekx1vLHNa/nl/X0GFAZKOqI8yVnCe+ePL+MIWNpPvZ2UlsoIpN6BhoDvB2z SYMW9g15rzpNiiR2iZOh9fvKtz03MM0eO21pVNeQVscUcxF75Q/Qo0D8cR8LyxnmtHMb l/IH/ecQLrhtKlqW7pYb9OfecAoQwmpNCpmUTWPIAjw2bFNX4zyst7Z6zg2926SZuSVl k9vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ns4iM9T1bOBC02dlnDL65OgFGuOFjTz8LmgOUq5fuL0=; b=8NHPymZF51vqSWz7NQEl1WiP+10EZ3upyGM0UqPf31JX+mQC4lWZBN59tJRIonIKUU zYFRnqyUu5oSkhaVGbgxMknilrBXMDMg5vXwVq6gviXXsPMv6ImNdMf+zB2FmW9ySdqE k4FEFGfoIzGGv5+t0POe+Aku1M9rPDq9QPExEI82i6FxOIGqSSLs+CScDHV48Muy1MNP 0lamj+U/eFZK8NbL+VouApDVfYhES1asHetT+i1/8ssr5cE/g+om+zEeruI5CC0hxz9e OJ3nJQuCZbJkLJAWJKtYtlwvCTsRiyjpnSHEvp9XhEOtk69T+WCnda67h8mG3DoJ7fxR EgPA== X-Gm-Message-State: ANoB5pnLhghWv2+GksbpOEOnxV6HWaYHbaAoYLVPAOma/9zGYfeDnfdb 6YQYqtI4elFog7Rac3Dos2k= X-Google-Smtp-Source: AA0mqf7Oovmior+GGirB8xomPHjpfrPVCBGZMxESLXssoZ2XZgwpGK9RWH1QLboxtsYzcw8SSg6vCw== X-Received: by 2002:a05:6000:16c4:b0:250:b68f:8b8b with SMTP id h4-20020a05600016c400b00250b68f8b8bmr7935931wrf.25.1671018107977; Wed, 14 Dec 2022 03:41:47 -0800 (PST) Received: from localhost.localdomain (2a02-8428-46a0-7c01-bc7c-15f1-6c3b-ad74.rev.sfr.net. [2a02:8428:46a0:7c01:bc7c:15f1:6c3b:ad74]) by smtp.gmail.com with ESMTPSA id b8-20020a05600003c800b0024258722a7fsm2697405wrg.37.2022.12.14.03.41.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 03:41:47 -0800 (PST) From: Christophe Branchereau To: thierry.reding@gmail.com, sam@ravnborg.org, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, paul@crapouillou.net, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christophe Branchereau Subject: [PATCH v2 1/2] drm/panel: Add driver for the AUO A030JTN01 TFT LCD Date: Wed, 14 Dec 2022 12:41:41 +0100 Message-Id: <20221214114142.204041-2-cbranchereau@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221214114142.204041-1-cbranchereau@gmail.com> References: <20221214114142.204041-1-cbranchereau@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add driver for the AUO A030JTN01 panel, which is a 320x480 3.0" 4:3 24-bit TFT LCD panel with non-square pixels and a delta-RGB 8-bit interface. Signed-off-by: Christophe Branchereau Signed-off-by: Paul Cercueil --- drivers/gpu/drm/panel/Kconfig | 8 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-auo-a030jtn01.c | 295 ++++++++++++++++++++ 3 files changed, 304 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-auo-a030jtn01.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index a582ddd583c2..3db85c68d182 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -8,6 +8,14 @@ config DRM_PANEL menu "Display Panels" depends on DRM && DRM_PANEL =20 +config DRM_PANEL_AUO_A030JTN01 + tristate "AUO A030JTN01" + depends on OF && SPI + select REGMAP_SPI + help + Say Y here to enable support for the AUO A030JTN01 320x480 3.0" panel + as found in the YLM RS-97 handheld gaming console. + config DRM_PANEL_ABT_Y030XX067A tristate "ABT Y030XX067A 320x480 LCD panel" depends on OF && SPI diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 34e717382dbb..f425599c2717 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_DRM_PANEL_AUO_A030JTN01) +=3D panel-auo-a030jtn01.o obj-$(CONFIG_DRM_PANEL_ABT_Y030XX067A) +=3D panel-abt-y030xx067a.o obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) +=3D panel-arm-versatile.o obj-$(CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596) +=3D panel-asus-z00t-tm5p5= -n35596.o diff --git a/drivers/gpu/drm/panel/panel-auo-a030jtn01.c b/drivers/gpu/drm/= panel/panel-auo-a030jtn01.c new file mode 100644 index 000000000000..1c4f812e9483 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-auo-a030jtn01.c @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AU Optronics A030JTN01.0 TFT LCD panel driver + * + * Copyright (C) 2020, Paul Cercueil + * Copyright (C) 2020, Christophe Branchereau + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct a030jtn01_info { + const struct drm_display_mode *display_modes; + unsigned int num_modes; + u16 width_mm, height_mm; + u32 bus_format, bus_flags; +}; + +struct a030jtn01 { + struct drm_panel panel; + struct spi_device *spi; + struct regmap *map; + + const struct a030jtn01_info *panel_info; + + struct regulator *supply; + struct gpio_desc *reset_gpio; +}; + +static inline struct a030jtn01 *to_a030jtn01(struct drm_panel *panel) +{ + return container_of(panel, struct a030jtn01, panel); +} + +static int a030jtn01_prepare(struct drm_panel *panel) +{ + struct a030jtn01 *priv =3D to_a030jtn01(panel); + struct device *dev =3D &priv->spi->dev; + int err; + + err =3D regulator_enable(priv->supply); + if (err) { + dev_err(dev, "Failed to enable power supply: %d\n", err); + return err; + } + + usleep_range(1000, 8000); + + /* Reset the chip */ + gpiod_set_value_cansleep(priv->reset_gpio, 1); + usleep_range(100, 8000); + gpiod_set_value_cansleep(priv->reset_gpio, 0); + usleep_range(2000, 8000); + + /* + * No idea why two writes are needed. If this write is commented, + * the colors are wrong. Doesn't seem to be timing-related, since + * a msleep(200) doesn't fix it. + */ + regmap_write(priv->map, 0x06, 0x00); + + /* Use (24 + 6) =3D=3D 0x1e as the vertical back porch */ + err =3D regmap_write(priv->map, 0x06, 0x1e); + if (err) + goto err_disable_regulator; + + /* Use (42 + 30) * 3 =3D=3D 0xd8 as the horizontal back porch */ + err =3D regmap_write(priv->map, 0x07, 0xd8); + if (err) + goto err_disable_regulator; + + regmap_write(priv->map, 0x05, 0x74); + + return 0; + +err_disable_regulator: + gpiod_set_value_cansleep(priv->reset_gpio, 1); + regulator_disable(priv->supply); + return err; +} + +static int a030jtn01_unprepare(struct drm_panel *panel) +{ + struct a030jtn01 *priv =3D to_a030jtn01(panel); + + gpiod_set_value_cansleep(priv->reset_gpio, 1); + regulator_disable(priv->supply); + + return 0; +} + +static int a030jtn01_enable(struct drm_panel *panel) +{ + struct a030jtn01 *priv =3D to_a030jtn01(panel); + int ret; + + ret =3D regmap_write(priv->map, 0x05, 0x75); + if (ret) + return ret; + + /* Wait for the picture to be stable */ + if (panel->backlight) + msleep(100); + + return 0; +} + +static int a030jtn01_disable(struct drm_panel *panel) +{ + struct a030jtn01 *priv =3D to_a030jtn01(panel); + + return regmap_write(priv->map, 0x05, 0x74); +} + +static int a030jtn01_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct a030jtn01 *priv =3D to_a030jtn01(panel); + const struct a030jtn01_info *panel_info =3D priv->panel_info; + struct drm_display_mode *mode; + unsigned int i; + + for (i =3D 0; i < panel_info->num_modes; i++) { + mode =3D drm_mode_duplicate(connector->dev, + &panel_info->display_modes[i]); + if (!mode) + return -ENOMEM; + + drm_mode_set_name(mode); + + mode->type =3D DRM_MODE_TYPE_DRIVER; + if (panel_info->num_modes =3D=3D 1) + mode->type |=3D DRM_MODE_TYPE_PREFERRED; + + drm_mode_probed_add(connector, mode); + } + + connector->display_info.bpc =3D 8; + connector->display_info.width_mm =3D panel_info->width_mm; + connector->display_info.height_mm =3D panel_info->height_mm; + + drm_display_info_set_bus_formats(&connector->display_info, + &panel_info->bus_format, 1); + connector->display_info.bus_flags =3D panel_info->bus_flags; + + return panel_info->num_modes; +} + +static const struct drm_panel_funcs a030jtn01_funcs =3D { + .prepare =3D a030jtn01_prepare, + .unprepare =3D a030jtn01_unprepare, + .enable =3D a030jtn01_enable, + .disable =3D a030jtn01_disable, + .get_modes =3D a030jtn01_get_modes, +}; + +static bool a030jtn01_has_reg(struct device *dev, unsigned int reg) +{ + static const u32 a030jtn01_regs_mask =3D 0x001823f1fb; + + return a030jtn01_regs_mask & BIT(reg); +}; + +static const struct regmap_config a030jtn01_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .read_flag_mask =3D 0x40, + .max_register =3D 0x1c, + .readable_reg =3D a030jtn01_has_reg, + .writeable_reg =3D a030jtn01_has_reg, +}; + +static int a030jtn01_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + struct a030jtn01 *priv; + int err; + + spi->mode |=3D SPI_MODE_3 | SPI_3WIRE; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->spi =3D spi; + spi_set_drvdata(spi, priv); + + priv->map =3D devm_regmap_init_spi(spi, &a030jtn01_regmap_config); + if (IS_ERR(priv->map)) { + dev_err(dev, "Unable to init regmap\n"); + return PTR_ERR(priv->map); + } + + priv->panel_info =3D of_device_get_match_data(dev); + if (!priv->panel_info) + return -EINVAL; + + priv->supply =3D devm_regulator_get(dev, "power"); + if (IS_ERR(priv->supply)) { + dev_err(dev, "Failed to get power supply\n"); + return PTR_ERR(priv->supply); + } + + priv->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(priv->reset_gpio)) { + dev_err(dev, "Failed to get reset GPIO\n"); + return PTR_ERR(priv->reset_gpio); + } + + drm_panel_init(&priv->panel, dev, &a030jtn01_funcs, + DRM_MODE_CONNECTOR_DPI); + + err =3D drm_panel_of_backlight(&priv->panel); + if (err) + return err; + + drm_panel_add(&priv->panel); + + return 0; +} + +static void a030jtn01_remove(struct spi_device *spi) +{ + struct a030jtn01 *priv =3D spi_get_drvdata(spi); + + drm_panel_remove(&priv->panel); + drm_panel_disable(&priv->panel); + drm_panel_unprepare(&priv->panel); +} + +static const struct drm_display_mode a030jtn01_modes[] =3D { + { /* 60 Hz */ + .clock =3D 14400, + .hdisplay =3D 320, + .hsync_start =3D 320 + 8, + .hsync_end =3D 320 + 8 + 42, + .htotal =3D 320 + 8 + 42 + 30, + .vdisplay =3D 480, + .vsync_start =3D 480 + 90, + .vsync_end =3D 480 + 90 + 24, + .vtotal =3D 480 + 90 + 24 + 6, + .flags =3D DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + }, + { /* 50 Hz */ + .clock =3D 12000, + .hdisplay =3D 320, + .hsync_start =3D 320 + 8, + .hsync_end =3D 320 + 8 + 42, + .htotal =3D 320 + 8 + 42 + 30, + .vdisplay =3D 480, + .vsync_start =3D 480 + 90, + .vsync_end =3D 480 + 90 + 24, + .vtotal =3D 480 + 90 + 24 + 6, + .flags =3D DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + }, +}; + +static const struct a030jtn01_info a030jtn01_info =3D { + .display_modes =3D a030jtn01_modes, + .num_modes =3D ARRAY_SIZE(a030jtn01_modes), + .width_mm =3D 70, + .height_mm =3D 51, + .bus_format =3D MEDIA_BUS_FMT_RGB888_3X8_DELTA, + .bus_flags =3D DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, +}; + +static const struct of_device_id a030jtn01_of_match[] =3D { + { .compatible =3D "auo,a030jtn01", .data =3D &a030jtn01_info }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, a030jtn01_of_match); + +static struct spi_driver a030jtn01_driver =3D { + .driver =3D { + .name =3D "auo-a030jtn01", + .of_match_table =3D a030jtn01_of_match, + }, + .probe =3D a030jtn01_probe, + .remove =3D a030jtn01_remove, +}; +module_spi_driver(a030jtn01_driver); + +MODULE_AUTHOR("Paul Cercueil "); +MODULE_AUTHOR("Christophe Branchereau "); +MODULE_LICENSE("GPL v2"); --=20 2.35.1 From nobody Wed Sep 17 22:19:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B4C0C4332F for ; Wed, 14 Dec 2022 11:42:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238286AbiLNLmI (ORCPT ); Wed, 14 Dec 2022 06:42:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238119AbiLNLlw (ORCPT ); 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[2a02:8428:46a0:7c01:bc7c:15f1:6c3b:ad74]) by smtp.gmail.com with ESMTPSA id b8-20020a05600003c800b0024258722a7fsm2697405wrg.37.2022.12.14.03.41.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 03:41:49 -0800 (PST) From: Christophe Branchereau To: thierry.reding@gmail.com, sam@ravnborg.org, airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, paul@crapouillou.net, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christophe Branchereau Subject: [PATCH v2 2/2] dt-bindings: display/panel: Add AUO A030JTN01 Date: Wed, 14 Dec 2022 12:41:42 +0100 Message-Id: <20221214114142.204041-3-cbranchereau@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221214114142.204041-1-cbranchereau@gmail.com> References: <20221214114142.204041-1-cbranchereau@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Paul Cercueil Add binding for the AUO A030JTN01 panel, which is a 320x480 3.0" 4:3 24-bit TFT LCD panel with non-square pixels and a delta-RGB 8-bit interface. Signed-off-by: Paul Cercueil Signed-off-by: Christophe Branchereau Reviewed-by: Krzysztof Kozlowski --- .../bindings/display/panel/auo,a030jtn01.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/auo,a03= 0jtn01.yaml diff --git a/Documentation/devicetree/bindings/display/panel/auo,a030jtn01.= yaml b/Documentation/devicetree/bindings/display/panel/auo,a030jtn01.yaml new file mode 100644 index 000000000000..6c099eb63434 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/auo,a030jtn01.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/auo,a030jtn01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AUO A030JTN01 3.0" (320x480 pixels) 24-bit TFT LCD panel + +description: | + The panel must obey the rules for a SPI slave device as specified in + spi/spi-controller.yaml + +maintainers: + - Paul Cercueil + - Christophe Branchereau + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: auo,a030jtn01 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + panel@0 { + compatible =3D "auo,a030jtn01"; + reg =3D <0>; + + spi-max-frequency =3D <10000000>; + + reset-gpios =3D <&gpe 4 GPIO_ACTIVE_LOW>; + power-supply =3D <&lcd_power>; + + backlight =3D <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint =3D <&panel_output>; + }; + }; + }; + }; --=20 2.35.1