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[93.129.109.38]) by smtp.gmail.com with ESMTPSA id f5-20020a05640214c500b00458b41d9460sm5407498edx.92.2022.12.13.15.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 15:43:49 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v5 1/7] dt-bindings: arm64: dts: mediatek: Add mt8365-evk board Date: Wed, 14 Dec 2022 00:43:40 +0100 Message-Id: <20221213234346.2868828-2-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221213234346.2868828-1-bero@baylibre.com> References: <20221213234346.2868828-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings for the Mediatek mt8365-evk board. Signed-off-by: Bernhard Rosenkr=C3=A4nzer Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Document= ation/devicetree/bindings/arm/mediatek.yaml index 2275e5d93721b..ae12b1cab9fbd 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -244,6 +244,10 @@ properties: - enum: - mediatek,mt8183-pumpkin - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8365-evk + - const: mediatek,mt8365 - items: - enum: - mediatek,mt8516-pumpkin --=20 2.39.0 From nobody Sat Sep 21 07:34:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39CF2C4332F for ; Tue, 13 Dec 2022 23:44:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237094AbiLMXoD (ORCPT ); Tue, 13 Dec 2022 18:44:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236833AbiLMXnx (ORCPT ); Tue, 13 Dec 2022 18:43:53 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 338A7FF for ; Tue, 13 Dec 2022 15:43:52 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id s5so20171240edc.12 for ; Tue, 13 Dec 2022 15:43:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=O64VFuluv/+RAMm/QFXRr7gO6/gguZoVuAfGvEuXsBQ=; b=F9RT9ErcDtYTRk4QvJML9Q2BwydzJrsY0EeEGEb3lyQZkpJPZ1825l40mqF59gmBf6 IEP8/v5jMBBYbDVWMW35gsJbsDp6lrE983cm5GCT4nE4ccUju771j2+52gLQlO8oilL8 wnWt/26odfyzZNddt7U43WNY+7mNwD2VuKihmUMbVw7x3poO0Tyk2AVzjzS+U8ahunkJ ZKsvl4t4z4deKT11qyMyAXvqQdylk1DXpf5MLAHcWsr7LWp3E/wQOdr9J03F0KskP+1x riOq9XMk9doRBgxrxIBs3e83RozJhm+4mnJHoQL2RzxKMt0Jbbca/oB0f5BNbaw+Wed2 CUtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O64VFuluv/+RAMm/QFXRr7gO6/gguZoVuAfGvEuXsBQ=; b=vdR0QPUpyHHWCfBGcICepR3plBRxD17C0Urdl4k6GQ2dICgZ3LG7jiumCqvIVhuf8k LEVbwqxTAASneONhw/jdWY8dbHAQEFu9pY0jbgbt7FozF/znPv90p05P+TzTxLsYnk/S 02zGnRv/3WJFsm+CR0mFddcLmsUOjxu2MaGEmrJuf3Nmsnaob73wzjtI4fYuvE6WuoHn eE4m3q++oLTzPbxaKdTZ1p6IXRG+SjHj9UTYhPLWnWKBJvGvUq6s8t3FmBNxDuuQKadx Gv6iGMwDA4kbnlxWn0pA5N2h+ZFiyUWFZA6n5zp9M7aU/hG7KVowym4igaURBx+iftbs sK1g== X-Gm-Message-State: ANoB5pmmQKixNa5xd6moDxEe0SzYP/Dv6jl9wEydM9SE/SjLQeH+1f2q g+IVXhFy48i0GWDh5NEcx02eWg== X-Google-Smtp-Source: AA0mqf44+TtTHjB2d/Gl2sH9AH4zHu5kBAdtGeps2WGjNdvMA739ICQX1O2kyUGBcd+nn1H6QRtCRQ== X-Received: by 2002:a50:ee1a:0:b0:46b:6214:44c8 with SMTP id g26-20020a50ee1a000000b0046b621444c8mr18101392eds.39.1670975030826; Tue, 13 Dec 2022 15:43:50 -0800 (PST) Received: from predatorhelios.fritz.box (dynamic-093-129-109-038.93.129.pool.telefonica.de. [93.129.109.38]) by smtp.gmail.com with ESMTPSA id f5-20020a05640214c500b00458b41d9460sm5407498edx.92.2022.12.13.15.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 15:43:50 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v5 2/7] dt-bindings: irq: mtk, sysirq: add support for mt8365 Date: Wed, 14 Dec 2022 00:43:41 +0100 Message-Id: <20221213234346.2868828-3-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221213234346.2868828-1-bero@baylibre.com> References: <20221213234346.2868828-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding documentation of mediatek,sysirq for mt8365 SoC. Signed-off-by: Bernhard Rosenkr=C3=A4nzer Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediate= k,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/media= tek,sysirq.txt index 84ced3f4179b9..3ffc60184e445 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysir= q.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysir= q.txt @@ -25,6 +25,7 @@ Required properties: "mediatek,mt6577-sysirq": for MT6577 "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 + "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365 - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Use the same format as specified by GIC in arm,gic.tx= t. - reg: Physical base address of the intpol registers and length of memory --=20 2.39.0 From nobody Sat Sep 21 07:34:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B448C4332F for ; Tue, 13 Dec 2022 23:44:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237111AbiLMXoG (ORCPT ); Tue, 13 Dec 2022 18:44:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236903AbiLMXny (ORCPT ); Tue, 13 Dec 2022 18:43:54 -0500 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22A971573C for ; Tue, 13 Dec 2022 15:43:53 -0800 (PST) Received: by mail-ed1-x52a.google.com with SMTP id v8so20211676edi.3 for ; Tue, 13 Dec 2022 15:43:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1o+J70yLyVR2sOUu4UxPxrOg5DN55K4T4PHkpCAWjn4=; b=wORGT+IErpNloxOBrcuEF3V0K95c28pxI6CUW43ehtacgN64O4wuoQMWVMYwflNV18 LtfER7cU6y//IYxXH6rHv/nUkSrwpjabljAsTXMEQQVsQOIuxusklexXtRS2HhW2E+M9 RHL1KamjZitB/2rbpYL9YoyJruQAz8cO17AnxMw5CDCxhqm54IgCKZwwiEdKUAsZMv8Q B5dwE1h81HAntKODSwCexeyPsZz/6LMVYPtueVRljyNMgUjPxba8eX+i3tjKYwzTMZXf ewC9DISbTQyOl76QBgttZpU1yky1a41JPHqcZ2xCq9pVAysDEqINJvpaN4ft0KDm0gsG +aWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1o+J70yLyVR2sOUu4UxPxrOg5DN55K4T4PHkpCAWjn4=; b=12dCswqMv+BdnB1BP8qHFe+A1e1bydJwpodsYn0LDT63rtGZJvrJxwWfm+OCxZ/Jre Ln847/cNiRHUxjne7ppAYPET11oz4wVN3MZrAQttfTFlfPB7TPwRzGdGT4+Sk8oDRM20 073INWywKUe1uO2pyYXL7icbmJXfORJsXwOhEueGHsoHLRn0si0P8RFcEHs+04Ys3ZFN Z2So9lFsPX56jCkZSI1pacL5C8YPt6QtcZ0gYwLKRpz03zFNVo9moqVxd9RlM/LOkzev 191PUtCB+F6t14oOvXxmyG6BLGSJGTJ6Vwotqp0vt14/t+AhhwNU3sqaeoVBWhdpheBH VguQ== X-Gm-Message-State: ANoB5pncXMn5LTsPQpk17JuDkykVmywS+75sh9cQUnBVvFsoybwqYG15 f7kwCWoLLvfqmklZS++QkB3foQ== X-Google-Smtp-Source: AA0mqf6bcglIg2qJY5ALdaxVVJdoWYM0lGfOFG1QMFMMUhShdk4Z6n00yKzWtIpU77TFfb/M19JI7A== X-Received: by 2002:a05:6402:3445:b0:46b:14d8:af9b with SMTP id l5-20020a056402344500b0046b14d8af9bmr18887312edc.38.1670975031767; Tue, 13 Dec 2022 15:43:51 -0800 (PST) Received: from predatorhelios.fritz.box (dynamic-093-129-109-038.93.129.pool.telefonica.de. [93.129.109.38]) by smtp.gmail.com with ESMTPSA id f5-20020a05640214c500b00458b41d9460sm5407498edx.92.2022.12.13.15.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 15:43:51 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v5 3/7] dt-bindings: mfd: syscon: Add mt8365-syscfg Date: Wed, 14 Dec 2022 00:43:42 +0100 Message-Id: <20221213234346.2868828-4-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221213234346.2868828-1-bero@baylibre.com> References: <20221213234346.2868828-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document Mediatek mt8365-syscfg Signed-off-by: Bernhard Rosenkr=C3=A4nzer Acked-by: Krzysztof Kozlowski Reviewed-by: Matthias Brugger --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 1b01bd0104316..7beeb0abc4db0 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -50,6 +50,7 @@ properties: - marvell,armada-3700-usb2-host-misc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg + - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep --=20 2.39.0 From nobody Sat Sep 21 07:34:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44B29C4332F for ; Tue, 13 Dec 2022 23:44:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229514AbiLMXoJ (ORCPT ); Tue, 13 Dec 2022 18:44:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236969AbiLMXnz (ORCPT ); Tue, 13 Dec 2022 18:43:55 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EA3555B8 for ; Tue, 13 Dec 2022 15:43:54 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id i9so7330447edj.4 for ; Tue, 13 Dec 2022 15:43:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DION+KR3do3yHDMcyu0wTA4CxKiIa292v6vXsZ0tISk=; b=RzlMn2Rb6Hu5fJppNkeTi/jNvVUpEVCqOq5XselGGk4SLVyt2HtnLWSZzm7PwHVMY9 juTx62OBQs9JLWXhttD7BtaXBABVhK2UKO3/WwCdBxo6xFnc3IRIESfxmOeKYjWpESBs 9JHAULBErSjViowsRVy0snP/GyD2QYgVsVY5R1E8iJqRAKHTsssbO0dvTR4MdZ73FreL Qn9PNr7JCVaO2C9knNvwenj+xDeXH+KN+PqYeUmdIBdKDZjp3ZQysJgrS9VMsJCj/AmN XFmrvnSbWi561J0AsX8tZbOy06tqM/ptPz6w50I7Tqx7wAysbI8KEmXAjLliX+ANnWDL c6Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DION+KR3do3yHDMcyu0wTA4CxKiIa292v6vXsZ0tISk=; b=LYGFKrR1acMcK8OE37pWmuQuRJXI57XyYA63Gz/fBbKK/KvqZ9FpAh+BwoYDLAUEqY osjKErOwGHKsFx+Q74FpTWHQ9NuORh952NrSEy3ZEotB+3vYzjo1B4iB2vcU0qeUYLtE wylmNdViw3disREaXMpR/0/jXSU/CscllVBhHKbST4JGWWh+USItiWRX7zjjyp+H0fe1 hma0FvAv3AveE7JhgMxYjYFntbmOSHabtaQ3MWVlt+6/WFHHyKtWZ+ZZ9+EgTD4dGQiF AOwt2SMxMJX/o7Vp9ll6K9sTeAivNLWw1WIkBCHlvRXxpBow4bGoxqDaoXy7cpfnDeKU VGJg== X-Gm-Message-State: ANoB5pmZhXWptkWBh3LmXdurnLOFayFisAFPJqSw6i5p9TofwlQmghSd gUy672flK6q+6s5FgM8Y9QFH9A== X-Google-Smtp-Source: AA0mqf477wk9D39J7zfehzIDtqjioOCBEJ0lKYT/SNJSeRi9jeeATBNuYLO9diGAC6VO8ICaSjrtJw== X-Received: by 2002:a05:6402:12c9:b0:46c:55ef:8d50 with SMTP id k9-20020a05640212c900b0046c55ef8d50mr19150747edx.24.1670975032801; Tue, 13 Dec 2022 15:43:52 -0800 (PST) Received: from predatorhelios.fritz.box (dynamic-093-129-109-038.93.129.pool.telefonica.de. [93.129.109.38]) by smtp.gmail.com with ESMTPSA id f5-20020a05640214c500b00458b41d9460sm5407498edx.92.2022.12.13.15.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 15:43:52 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v5 4/7] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC Date: Wed, 14 Dec 2022 00:43:43 +0100 Message-Id: <20221213234346.2868828-5-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221213234346.2868828-1-bero@baylibre.com> References: <20221213234346.2868828-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree bindings for Mediatek MT8365 pinctrl driver. Signed-off-by: Bernhard Rosenkr=C3=A4nzer --- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 197 ++++++++++++++++++ 1 file changed, 197 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt83= 65-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctr= l.yaml new file mode 100644 index 0000000000000..3c0248b48caff --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,197 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao + - Bernhard Rosenkr=C3=A4nzer + +description: | + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: | + Should be phandles of the syscfg node. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the= below + mentioned gpio binding representation for description of particular = cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +patternProperties: + "-pins$": + type: object + additionalProperties: false + patternProperties: + "pins$": + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing = the + pinctrl groups available on the machine. Each subnode will list = the + pins it needs, and how they should be configured, with regard to= muxer + configuration, pullups, drive strength, input enable/disable and= input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and = are + defined as macros in -pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: | + Besides generic pinconfig options, it can be used as the pul= l up + settings for 2 pull resistors, R0 and R1. User can configure= those + special pins. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only su= pport + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup= , they + can support 0.125/0.25/0.5/1mA adjustment. If we enable spec= ific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=3D0/E0=3D0, the strength is 0.125mA. + When E1=3D0/E0=3D1, the strength is 0.25mA. + When E1=3D1/E0=3D0, the strength is 0.5mA. + When E1=3D1/E0=3D1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) =3D (0, 0, 0) + 1: (E1, E0, EN) =3D (0, 0, 1) + 2: (E1, E0, EN) =3D (0, 1, 0) + 3: (E1, E0, EN) =3D (0, 1, 1) + 4: (E1, E0, EN) =3D (1, 0, 0) + 5: (E1, E0, EN) =3D (1, 0, 1) + 6: (E1, E0, EN) =3D (1, 1, 0) + 7: (E1, E0, EN) =3D (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described = as below: + 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. + 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. + 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. + 3: (R1, R0) =3D (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described = as below: + 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. + 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. + 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. + 3: (R1, R0) =3D (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: | + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arg= uments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: | + An integer describing the steps for input level shifter duty= cycle + when asserted (high pulse width adjustment). Valid arguments= are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pio: pinctrl@1000b000 { + compatible =3D "mediatek,mt8365-pinctrl"; + reg =3D <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap =3D <&syscfg_pctl>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + + pio-pins { + pins { + pinmux =3D , ; + mediatek,pull-up-adv =3D <3>; + mediatek,drive-strength-adv =3D <00>; + bias-pull-up; + }; + }; + }; + }; --=20 2.39.0 From nobody Sat Sep 21 07:34:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39AA2C4332F for ; Tue, 13 Dec 2022 23:44:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237154AbiLMXoM (ORCPT ); Tue, 13 Dec 2022 18:44:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237066AbiLMXn4 (ORCPT ); Tue, 13 Dec 2022 18:43:56 -0500 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 353FB63AF for ; Tue, 13 Dec 2022 15:43:55 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id f7so20205747edc.6 for ; Tue, 13 Dec 2022 15:43:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TyLi6iA5QFbrZuLEeQFr7qfmVlBeS8MD2efPde1AiOw=; b=xCguJJPaZEjMzGujNfSpsGHOF24EbRn3Blw4RFAU6A1N96sJQxF9GOtFOS7pLu97Pt yaVSQlU3rrKnjqEN3y/OlqKWGPUFlkrNmQnJCbtUdZ2WmMDeP8Oqv/Ej6Zin5oz5CdTh 0cj3DsTDBuj3TcfBJfwFTKnq32HFP25sPusoxE9S4hjEpHRTeEHNhzr6hAp4j8tWhuI/ h7HrJClZcRnR5gK36OCk6rSkzuOYSlRodgxXepUHNgam72gDdO/UQvEk8glHhIXBYRgd W++69kt6vnhtQ2EHDA9OSHbfSsuzmxjqtRFAYShCnhFiZd5nbRwJY8A3f+4Y3hCknzSv 76FQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TyLi6iA5QFbrZuLEeQFr7qfmVlBeS8MD2efPde1AiOw=; b=3eBlGrK+BBviqZhCe/33Odj22PvnqSsRQCyzk88mkLe8rgIp2ZfZEzRJEasHR2XN1z GrsOpaJtEJ010ICChq1bqDxT8pX85aMNJWSq9r6N6kthiCq5zkQXFzYE7nIXIX2Cml4/ p7H8dcU5Snu1tdb6fi+MEuZ0x0NLN8D0EdzhTOOIekmlGRWlWz3W2FnFPjls8UgB40Bf Banc/PrmD78ehoGMmvtOvbecBXJyhrrtZjw7jDc7A1brmAHYraIOlF6NRBnCGcD+Uf0A UulzebirUz47SAMm0mawzLzIVUHuGa5Qryj9uC3coFPprWIU58QCT2+hPezH/5VVLoMG DZHg== X-Gm-Message-State: ANoB5plb1hzQrvr2cbfYk+HbNGbTVbjIRPSigVb++uAcqJVeobraMM1r u7qrbQTdgFChwuaRiVMBdF5UDA== X-Google-Smtp-Source: AA0mqf6Z1k1vCSwJWdeOCOWRZIb7unYzNGZhFgwCvPgtqpxtk3N+bmmDBUibzZdHGGxxWSSHS1dSrg== X-Received: by 2002:a05:6402:12c9:b0:46c:55ef:8d50 with SMTP id k9-20020a05640212c900b0046c55ef8d50mr19150778edx.24.1670975033781; Tue, 13 Dec 2022 15:43:53 -0800 (PST) Received: from predatorhelios.fritz.box (dynamic-093-129-109-038.93.129.pool.telefonica.de. [93.129.109.38]) by smtp.gmail.com with ESMTPSA id f5-20020a05640214c500b00458b41d9460sm5407498edx.92.2022.12.13.15.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 15:43:53 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v5 5/7] dt-bindings: usb: mediatek,mtu3: add MT8365 SoC bindings Date: Wed, 14 Dec 2022 00:43:44 +0100 Message-Id: <20221213234346.2868828-6-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221213234346.2868828-1-bero@baylibre.com> References: <20221213234346.2868828-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: Matthias Brugger --- Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Doc= umentation/devicetree/bindings/usb/mediatek,mtu3.yaml index 7168110e2f9de..d2655173e108c 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt8188-mtu3 - mediatek,mt8192-mtu3 - mediatek,mt8195-mtu3 + - mediatek,mt8365-mtu3 - const: mediatek,mtu3 =20 reg: --=20 2.39.0 From nobody Sat Sep 21 07:34:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0762DC4332F for ; Tue, 13 Dec 2022 23:44:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236963AbiLMXoP (ORCPT ); Tue, 13 Dec 2022 18:44:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237067AbiLMXn4 (ORCPT ); Tue, 13 Dec 2022 18:43:56 -0500 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E89F6454 for ; Tue, 13 Dec 2022 15:43:55 -0800 (PST) Received: by mail-ed1-x52a.google.com with SMTP id v8so20211900edi.3 for ; Tue, 13 Dec 2022 15:43:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CMWE91a+pM6oT2mNZ7gfHqIhmh1zpfFSCXxbfA75K/I=; b=KjTg7+fHnrZSJ9TzbIsuime+L1iUIUwcVnapNP7Kz2D3un0pTvjzZ2erx7j4s4gVEU q2O+Vn65Z3QsWnPwgojrcUuASdZU9O7eDJQMkV6U1OxmSnuYP5GNYwZrPChVe8WFciB2 OiPvOOHpgKhu/WeZsxcNCVhLDYqw81qj4+mqLePCEsClvo2uz5DZ+UF9meaL6L+aGPpP otkWO9YYIY9wAzU4O+wq71Ly0Sh4qD1zTPYUhH+bPgPaJE+KDqUgsnIMAenQaWv1mbIZ vvN1y0vi2rSHWWPw00xS2aB/KQb00bBRXp9lm4MoZjLEx+w7ivYWFXiITBSHqTzALnmc NFvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CMWE91a+pM6oT2mNZ7gfHqIhmh1zpfFSCXxbfA75K/I=; b=Z7BpXVivz9K0uat9IOpQ6qiiWbfYJAwf+BUl2SCcc3JGW7eYS26CUqvk4JntdeDXal +zYzDj+GO4201xW5wu4xvoc7FFpcjC9hmQTDFXgy2py+rJKsU85woly4X2XZDhlciANU YzfoRWWFdaY8Anwwc554i3dOL+h8eqfmt1dMnlHrCorCGznsYEdUtWNqgiXsA3RCYF0U nd+hFc5zFBE7o8dyhxh6618zCuTm1Ni5wWuvccsJyV+SygRKrtthclvu2qgO8DOe9TSC BMQ2pUvPWjpyjTA5l0XYCMAJfHm2P1N8t2VvIyibCeUwWbva9srx0Q+0Xkaif4bygNyn G43g== X-Gm-Message-State: ANoB5pmW3s5uiv6S55VItBOFt4jane6FZg0MBB9GSE4AyeEIc3vUYGLN so9KRYLO7YsE4BjnVm6LdrNIeQ== X-Google-Smtp-Source: AA0mqf7VY+UGWGAMmObwTeYssJFUqQjOW3MtCDrFoe81hJCUG38R80/7WKyZmkUHMO+BOY6yug4ZPA== X-Received: by 2002:a05:6402:913:b0:46c:fe2d:a588 with SMTP id g19-20020a056402091300b0046cfe2da588mr17564775edz.18.1670975035226; Tue, 13 Dec 2022 15:43:55 -0800 (PST) Received: from predatorhelios.fritz.box (dynamic-093-129-109-038.93.129.pool.telefonica.de. [93.129.109.38]) by smtp.gmail.com with ESMTPSA id f5-20020a05640214c500b00458b41d9460sm5407498edx.92.2022.12.13.15.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 15:43:54 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v5 6/7] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings Date: Wed, 14 Dec 2022 00:43:45 +0100 Message-Id: <20221213234346.2868828-7-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221213234346.2868828-1-bero@baylibre.com> References: <20221213234346.2868828-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add binding documentation for the MT8365 SoC. Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b= /Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index a3c37944c6305..c119caa9ad168 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -35,6 +35,7 @@ properties: - mediatek,mt8188-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci + - mediatek,mt8365-xhci - const: mediatek,mtk-xhci =20 reg: --=20 2.39.0 From nobody Sat Sep 21 07:34:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23F73C4332F for ; Tue, 13 Dec 2022 23:44:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237013AbiLMXoT (ORCPT ); Tue, 13 Dec 2022 18:44:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237089AbiLMXn6 (ORCPT ); Tue, 13 Dec 2022 18:43:58 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B13A026CC for ; Tue, 13 Dec 2022 15:43:56 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id a16so20183404edb.9 for ; Tue, 13 Dec 2022 15:43:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wElmBlp8lUK13LpJTSFSUhrGzeF0MlEpla7yl2XGcO4=; b=sQ70ALCRsY/r6d6tHGxxQUM+xO3ur6675gBHnIVWWb/VtnuzC6gM9hI8jCbgry6+JX dUDYuOesVVo8sTbwO4icoUhBqbmp7uo/MRgcouZFs3nI6C9Sz3pu6YD5RTyYJL2bcBc9 8zuagp87Kmey+rgpyo4jv3FtwUaXk5UW6wcdTUuL2QnIPO0dt7zP7aVFb/YQHaD1H0cz 1mk/R02ab91SzTCbKkDk2BSHbc8eO3Ig/0Xg6DEDQAhT7Ri7HEyw9liNBsHIBdAW6ehh sDpSGA//+Guq9LuLOWG7naqOJCnNJMiI2/75QhUUjjmwluPW306FJNRdYiYryKh4bCe4 iMiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wElmBlp8lUK13LpJTSFSUhrGzeF0MlEpla7yl2XGcO4=; b=xv+BCTfIuAXAxB7z5zp2094j6h/A4wZMhhmxGVis9kBSZfBFdiOOjpV8H+SenCPPcV EVweEkQ91/gsyLSF0eMD0IHkgSSBXrIf0Vx8Sg89j/fMjvG0YQPhUK4fKQiWy0uztkbb ymI2IVH0M3XCcovAlDs2SV5ophMxZDpelUazCoTrLKMykWWFtDF2uQoTPsExdVc+OyQP AVO2sZ8f3mdpPzr8TWDLFAXaEGNJB/0XqjYrd2yKzUvbA6UmQV1auz1guYBgu8ByPIye kTu4dDsZvE9IBnZvoNp0Jv+MCfATQwoXO1DvAF1LntFbc1mMItjmG00ARODrgLGOCP13 4Dzg== X-Gm-Message-State: ANoB5pm4J11NgO+qGycK2vW7pevzm3g9NBhWEjtr5zTtzodSnKNowXMc TOmSDMrfjyh4J1g+fJ13jLctzg== X-Google-Smtp-Source: AA0mqf5ksi0oTpp4Tw2+DYBZK4aJECPzh2L0O4O8xS1tkvj+wYg5m4llIj8aFwMkiK6ahYtVSidqHg== X-Received: by 2002:a05:6402:c2:b0:461:568b:fb22 with SMTP id i2-20020a05640200c200b00461568bfb22mr18080941edu.8.1670975036217; Tue, 13 Dec 2022 15:43:56 -0800 (PST) Received: from predatorhelios.fritz.box (dynamic-093-129-109-038.93.129.pool.telefonica.de. [93.129.109.38]) by smtp.gmail.com with ESMTPSA id f5-20020a05640214c500b00458b41d9460sm5407498edx.92.2022.12.13.15.43.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 15:43:55 -0800 (PST) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, khilman@baylibre.com Subject: [PATCH v5 7/7] arm64: dts: mediatek: Initial mt8365-evk support Date: Wed, 14 Dec 2022 00:43:46 +0100 Message-Id: <20221213234346.2868828-8-bero@baylibre.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221213234346.2868828-1-bero@baylibre.com> References: <20221213234346.2868828-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent This adds minimal support for the Mediatek 8365 SOC and the EVK reference board, allowing the board to boot to initramfs with serial port I/O. Signed-off-by: Fabien Parent [bero@baylibre.com: Removed parts depending on drivers that aren't upstream= yet, cleanups, add L2 cache] Signed-off-by: Bernhard Rosenkr=C3=A4nzer Tested-by: Kevin Hilman --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 163 ++++++++++ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 343 ++++++++++++++++++++ 3 files changed, 507 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 813e735c5b96d..d78523c5a7dd6 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -47,4 +47,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r2.= dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/= dts/mediatek/mt8365-evk.dts new file mode 100644 index 0000000000000..972843f9e4e9d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021-2022 BayLibre, SAS. + * Authors: + * Fabien Parent + * Bernhard Rosenkr=C3=A4nzer + */ + +/dts-v1/; + +#include +#include +#include +#include "mt8365.dtsi" + +/ { + model =3D "MediaTek MT8365 Open Platform EVK"; + compatible =3D "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + input-name =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio_keys>; + + key-volume-up { + gpios =3D <&pio 24 GPIO_ACTIVE_LOW>; + label =3D "volume_up"; + linux,code =3D ; + wakeup-source; + debounce-interval =3D <15>; + }; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 0 0xc0000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "otg_vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg =3D <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&pio { + gpio_keys: gpio-keys-pins { + pins { + pinmux =3D ; + bias-pull-up; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux =3D , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux =3D , + ; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux =3D , + ; + }; + }; + + usb_pins: usb-pins { + pins-id { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pins-usb0-vbus { + pinmux =3D ; + output-high; + }; + + pin-usb1-vbus { + pinmux =3D ; + output-high; + }; + }; + + pwm_pins: pwm-pins { + pins { + pinmux =3D , + ; + }; + }; +}; + +&pwm { + pinctrl-0 =3D <&pwm_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts= /mediatek/mt8365.dtsi new file mode 100644 index 0000000000000..2c4ef9b92b68b --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) 2018 MediaTek Inc. + * Copyright (C) 2022 BayLibre SAS + * Fabien Parent + * Bernhard Rosenkr=C3=A4nzer + */ +#include +#include +#include +#include +#include + +/ { + compatible =3D "mediatek,mt8365"; + interrupt-parent =3D <&sysirq>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + #cooling-cells =3D <2>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache { + compatible =3D "cache"; + }; + }; + + clk26m: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + clock-output-names =3D "clk26m"; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg =3D <0 0x43000000 0 0x20000>; + }; + }; + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <4>; + interrupt-parent =3D <&gic>; + interrupt-controller; + reg =3D <0 0x0c000000 0 0x80000>, <0 0x0c080000 0 0x80000>; + + interrupts =3D ; + }; + + topckgen: syscon@10000000 { + compatible =3D "mediatek,mt8365-topckgen", "syscon"; + reg =3D <0 0x10000000 0 0x1000>; + #clock-cells =3D <1>; + }; + + infracfg: syscon@10001000 { + compatible =3D "mediatek,mt8365-infracfg", "syscon"; + reg =3D <0 0x10001000 0 0x1000>; + #clock-cells =3D <1>; + }; + + pericfg: syscon@10003000 { + compatible =3D "mediatek,mt8365-pericfg", "syscon"; + reg =3D <0 0x10003000 0 0x1000>; + #clock-cells =3D <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible =3D "mediatek,mt8365-syscfg", "syscon"; + reg =3D <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@1000b000 { + compatible =3D "mediatek,mt8365-pinctrl"; + reg =3D <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap =3D <&syscfg_pctl>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + }; + + apmixedsys: syscon@1000c000 { + compatible =3D "mediatek,mt8365-apmixedsys", "syscon"; + reg =3D <0 0x1000c000 0 0x1000>; + #clock-cells =3D <1>; + }; + + keypad: keypad@10010000 { + compatible =3D "mediatek,mt6779-keypad"; + reg =3D <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts =3D ; + clocks =3D <&clk26m>; + clock-names =3D "kpd"; + status =3D "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible =3D "mediatek,mt8365-mcucfg", "syscon"; + reg =3D <0 0x10200000 0 0x2000>; + #clock-cells =3D <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible =3D "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells =3D <3>; + interrupt-parent =3D <&gic>; + reg =3D <0 0x10200a80 0 0x20>; + }; + + infracfg_nao: infracfg@1020e000 { + compatible =3D "mediatek,mt8365-infracfg", "syscon"; + reg =3D <0 0x1020e000 0 0x1000>; + }; + + rng: rng@1020f000 { + compatible =3D "mediatek,mt8365-rng", "mediatek,mt7623-rng"; + reg =3D <0 0x1020f000 0 0x100>; + clocks =3D <&infracfg CLK_IFR_TRNG>; + clock-names =3D "rng"; + }; + + apdma: dma-controller@11000280 { + compatible =3D "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; + reg =3D <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts =3D , + , + , + , + , + ; + dma-requests =3D <6>; + clocks =3D <&infracfg CLK_IFR_AP_DMA>; + clock-names =3D "apdma"; + #dma-cells =3D <1>; + }; + + uart0: serial@11002000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11002000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 0>, <&apdma 1>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart1: serial@11003000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11003000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 2>, <&apdma 3>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + uart2: serial@11004000 { + compatible =3D "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg =3D <0 0x11004000 0 0x1000>; + interrupts =3D ; + clocks =3D <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names =3D "baud", "bus"; + dmas =3D <&apdma 4>, <&apdma 5>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + pwm: pwm@11006000 { + compatible =3D "mediatek,mt8365-pwm"; + reg =3D <0 0x11006000 0 0x1000>; + #pwm-cells =3D <2>; + interrupts =3D ; + clocks =3D <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names =3D "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + spi: spi@1100a000 { + compatible =3D "mediatek,mt8365-spi", "mediatek,mt7622-spi"; + reg =3D <0 0x1100a000 0 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk"; + status =3D "disabled"; + }; + + ssusb: usb@11201000 { + compatible =3D "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg =3D <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks =3D <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb_host: usb@11200000 { + compatible =3D "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>; + reg-names =3D "mac"; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status =3D "disabled"; + }; + }; + + u3phy: phy@11cc0000 { + compatible =3D "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; + #address-cells =3D <2>; + #size-cells =3D <2>; + #phy-cells =3D <1>; + ranges; + + u2port0: usb-phy@11cc0000 { + reg =3D <0 0x11cc0000 0 0x400>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + + u2port1: usb-phy@11cc1000 { + reg =3D <0 0x11cc1000 0 0x400>; + clocks =3D <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names =3D "ref", "da_ref"; + #phy-cells =3D <1>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + }; +}; --=20 2.39.0