From nobody Thu Sep 18 00:01:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E23DC4332F for ; Tue, 13 Dec 2022 22:43:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235536AbiLMWnf (ORCPT ); Tue, 13 Dec 2022 17:43:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236039AbiLMWn0 (ORCPT ); Tue, 13 Dec 2022 17:43:26 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 29FF42127F; Tue, 13 Dec 2022 14:43:25 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,242,1665414000"; d="scan'208";a="146060114" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Dec 2022 07:43:24 +0900 Received: from mulinux.home (unknown [10.226.93.1]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2D13540F4527; Wed, 14 Dec 2022 07:43:18 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH 1/5] dt-bindings: gpio: Add RZ/V2M PWC GPIO driver bindings Date: Tue, 13 Dec 2022 22:43:06 +0000 Message-Id: <20221213224310.543243-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> References: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dt-bindings document for the RZ/V2M PWC GPIO driver. Signed-off-by: Fabrizio Castro --- .../bindings/gpio/renesas,rzv2m-pwc-gpio.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/renesas,rzv2m-pw= c-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.= yaml b/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml new file mode 100644 index 000000000000..ecc034d53259 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/renesas,rzv2m-pwc-gpio.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/renesas,rzv2m-pwc-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) GPIO + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with General-Purpose + Output pins, alongside the below functions + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + This node uses syscon to map the register used to control the GPIOs + (the register map is retrieved from the parent dt-node), and the node sh= ould + be represented as a sub node of a "syscon", "simple-mfd" node. + +maintainers: + - Fabrizio Castro + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc-gpio # RZ/V2M + - renesas,r9a09g055-pwc-gpio # RZ/V2MA + - const: renesas,rzv2m-pwc-gpio + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Offset in the register map for controlling the GPIOs (in bytes). + + regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the register map node. + + gpio-controller: true + + '#gpio-cells': + const: 2 + +required: + - compatible + - regmap + - offset + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + gpio { + compatible =3D "renesas,r9a09g011-pwc-gpio", + "renesas,rzv2m-pwc-gpio"; + regmap =3D <®mapnode>; + offset =3D <0x80>; + gpio-controller; + #gpio-cells =3D <2>; + }; --=20 2.34.1 From nobody Thu Sep 18 00:01:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 374A2C10F1B for ; Tue, 13 Dec 2022 22:43:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236292AbiLMWni (ORCPT ); Tue, 13 Dec 2022 17:43:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236710AbiLMWnc (ORCPT ); Tue, 13 Dec 2022 17:43:32 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9A5D022291; Tue, 13 Dec 2022 14:43:30 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,242,1665414000"; d="scan'208";a="146060125" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Dec 2022 07:43:29 +0900 Received: from mulinux.home (unknown [10.226.93.1]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id D32DC40F4527; Wed, 14 Dec 2022 07:43:24 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH 2/5] dt-bindings: power: reset: Add RZ/V2M PWC Power OFF bindings Date: Tue, 13 Dec 2022 22:43:07 +0000 Message-Id: <20221213224310.543243-3-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> References: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dt-bindings document for the RZ/V2M PWC Power OFF driver. Signed-off-by: Fabrizio Castro --- .../reset/renesas,rzv2m-pwc-poweroff.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/reset/renesas,r= zv2m-pwc-poweroff.yaml diff --git a/Documentation/devicetree/bindings/power/reset/renesas,rzv2m-pw= c-poweroff.yaml b/Documentation/devicetree/bindings/power/reset/renesas,rzv= 2m-pwc-poweroff.yaml new file mode 100644 index 000000000000..12456e3e93e6 --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/renesas,rzv2m-pwc-power= off.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/renesas,rzv2m-pwc-poweroff.= yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) Power OFF + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with the below + capabilities + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + - general-purpose output pins + This node uses syscon to map the registers relevant to Power OFF (the + register map is retrieved from the parent dt-node), and the node should = be + represented as a sub node of a "syscon", "simple-mfd" node. + +maintainers: + - Fabrizio Castro + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc-poweroff # RZ/V2M + - renesas,r9a09g055-pwc-poweroff # RZ/V2MA + - const: renesas,rzv2m-pwc-poweroff + + regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the register map node. + +required: + - compatible + - regmap + +additionalProperties: false + +examples: + - | + poweroff { + compatible =3D "renesas,r9a09g011-pwc-poweroff", + "renesas,rzv2m-pwc-poweroff"; + regmap =3D <®mapnode>; + }; --=20 2.34.1 From nobody Thu Sep 18 00:01:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A99AC4332F for ; Tue, 13 Dec 2022 22:43:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236791AbiLMWnr (ORCPT ); Tue, 13 Dec 2022 17:43:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236733AbiLMWnh (ORCPT ); Tue, 13 Dec 2022 17:43:37 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id DA98722292; Tue, 13 Dec 2022 14:43:35 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,242,1665414000"; d="scan'208";a="143229837" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 14 Dec 2022 07:43:35 +0900 Received: from mulinux.home (unknown [10.226.93.1]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 819BB40F4527; Wed, 14 Dec 2022 07:43:30 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH 3/5] dt-bindings: mfd: Add RZ/V2M PWC global registers bindings Date: Tue, 13 Dec 2022 22:43:08 +0000 Message-Id: <20221213224310.543243-4-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> References: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RZ/V2M PWC is a multi-function device, and its software support relies on "syscon" and "simple-mfd". Add the dt-bindings for the top level device tree node. Signed-off-by: Fabrizio Castro --- .../bindings/mfd/renesas,rzv2m-pwc.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc= .yaml diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml b= /Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml new file mode 100644 index 000000000000..a7e180bfbd83 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/renesas,rzv2m-pwc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with the below + capabilities + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + - general-purpose output pins + +maintainers: + - Fabrizio Castro + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc # RZ/V2M + - renesas,r9a09g055-pwc # RZ/V2MA + - const: renesas,rzv2m-pwc + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + gpio: + type: object + $ref: /schemas/gpio/renesas,rzv2m-pwc-gpio.yaml# + description: General-Purpose Output pins controller. + + poweroff: + type: object + $ref: /schemas/power/reset/renesas,rzv2m-pwc-poweroff.yaml# + description: Power OFF controller. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pwc: pwc@a3700000 { + compatible =3D "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc", "= syscon", + "simple-mfd"; + reg =3D <0xa3700000 0x800>; + + gpio { + compatible =3D "renesas,r9a09g011-pwc-gpio", + "renesas,rzv2m-pwc-gpio"; + regmap =3D <&pwc>; + offset =3D <0x80>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + poweroff { + compatible =3D "renesas,r9a09g011-pwc-poweroff", + "renesas,rzv2m-pwc-poweroff"; + regmap =3D <&pwc>; + }; + }; --=20 2.34.1 From nobody Thu Sep 18 00:01:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3EC0DC25B04 for ; Tue, 13 Dec 2022 22:44:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236737AbiLMWoO (ORCPT ); Tue, 13 Dec 2022 17:44:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236540AbiLMWnr (ORCPT ); Tue, 13 Dec 2022 17:43:47 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 25C9B2252A; Tue, 13 Dec 2022 14:43:42 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,242,1665414000"; d="scan'208";a="146060139" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 14 Dec 2022 07:43:41 +0900 Received: from mulinux.home (unknown [10.226.93.1]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 326C440F4527; Wed, 14 Dec 2022 07:43:35 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi , Phil Edworthy Subject: [PATCH 4/5] gpio: Add support for Renesas RZ/V2M PWC Date: Tue, 13 Dec 2022 22:43:09 +0000 Message-Id: <20221213224310.543243-5-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> References: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RZ/V2M SoC contains an External Power Sequence Controller (PWC) module. This module provides an external power supply on/off sequence, on/off signal for the LPDDR4 core power supply, control signals for external I/O power supplies of the SD host interfaces, and key input signals. PWC is essentially a Multi-Function Device (MFD). The driver just implements the control signals for external I/O power supplies of the SD host interfaces as gpios, and it relies on syscon and simple-mfd. Signed-off-by: Phil Edworthy Signed-off-by: Fabrizio Castro --- drivers/gpio/Kconfig | 8 +++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rzv2m-pwc.c | 123 ++++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+) create mode 100644 drivers/gpio/gpio-rzv2m-pwc.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e6ebc4c90a5d..e016919b9643 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -553,6 +553,14 @@ config GPIO_ROCKCHIP help Say yes here to support GPIO on Rockchip SoCs. =20 +config GPIO_RZV2M_PWC + tristate "Renesas RZ/V2M PWC GPIO support" + depends on MFD_SYSCON + depends on ARCH_R9A09G011 || COMPILE_TEST + help + Say yes here to support the External Power Sequence Controller (PWC) + GPIO controller driver for RZ/V2M devices. + config GPIO_SAMA5D2_PIOBU tristate "SAMA5D2 PIOBU GPIO support" depends on MFD_SYSCON diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 3462a138764a..5f655684603f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -132,6 +132,7 @@ obj-$(CONFIG_GPIO_RDC321X) +=3D gpio-rdc321x.o obj-$(CONFIG_GPIO_REALTEK_OTTO) +=3D gpio-realtek-otto.o obj-$(CONFIG_GPIO_REG) +=3D gpio-reg.o obj-$(CONFIG_GPIO_ROCKCHIP) +=3D gpio-rockchip.o +obj-$(CONFIG_GPIO_RZV2M_PWC) +=3D gpio-rzv2m-pwc.o obj-$(CONFIG_ARCH_SA1100) +=3D gpio-sa1100.o obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) +=3D gpio-sama5d2-piobu.o obj-$(CONFIG_GPIO_SCH311X) +=3D gpio-sch311x.o diff --git a/drivers/gpio/gpio-rzv2m-pwc.c b/drivers/gpio/gpio-rzv2m-pwc.c new file mode 100644 index 000000000000..672d868cb8c9 --- /dev/null +++ b/drivers/gpio/gpio-rzv2m-pwc.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Renesas Electronics Corporation + * + * GPIO driver for Renesas RZ/V2M External Power Sequence Controller (PWC) + */ + +#include +#include +#include +#include +#include + +struct rzv2m_pwc_gpio_priv { + struct gpio_chip gp; + int offset; + struct regmap *regmap; + DECLARE_BITMAP(ch_en_bits, 2); +}; + +static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct rzv2m_pwc_gpio_priv *priv =3D gpiochip_get_data(chip); + u32 reg; + + /* BIT 16 enables write to BIT 0, and BIT 17 enables write to BIT 1 */ + reg =3D BIT(offset + 16); + if (value) + reg |=3D BIT(offset); + + regmap_write(priv->regmap, priv->offset, reg); + + if (value) + set_bit(offset, priv->ch_en_bits); + else + clear_bit(offset, priv->ch_en_bits); +} + +static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rzv2m_pwc_gpio_priv *priv =3D gpiochip_get_data(chip); + + return test_bit(offset, priv->ch_en_bits); +} + +static int rzv2m_pwc_gpio_direction_output(struct gpio_chip *gc, + unsigned int nr, int value) +{ + if (nr > 1) + return -EINVAL; + + rzv2m_pwc_gpio_set(gc, nr, value); + + return 0; +} + +static const struct gpio_chip rzv2m_pwc_gc =3D { + .label =3D "rzv2m_pwc_gpio", + .owner =3D THIS_MODULE, + .get =3D rzv2m_pwc_gpio_get, + .set =3D rzv2m_pwc_gpio_set, + .direction_output =3D rzv2m_pwc_gpio_direction_output, + .can_sleep =3D false, + .ngpio =3D 2, + .base =3D -1, +}; + +static int rzv2m_pwc_gpio_probe(struct platform_device *pdev) +{ + struct rzv2m_pwc_gpio_priv *priv; + int err; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "regmap"); + + if (IS_ERR(priv->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->regmap), + "Can't find regmap property"); + + err =3D of_property_read_u32(pdev->dev.of_node, "offset", &priv->offset); + if (err) + return dev_err_probe(&pdev->dev, -EINVAL, + "Can't find offset property"); + + /* + * The register used by this driver cannot be read, therefore set the + * outputs to their default values and initialize priv->ch_en_bits accord= ingly. + * BIT 16 enables write to BIT 0, BIT 17 enables write to BIT 1, and the + * default value of both BIT 0 and BIT 1 is 0. + */ + regmap_write(priv->regmap, priv->offset, BIT(17) | BIT(16)); + bitmap_zero(priv->ch_en_bits, 2); + + priv->gp =3D rzv2m_pwc_gc; + priv->gp.parent =3D pdev->dev.parent; + priv->gp.fwnode =3D dev_fwnode(&pdev->dev); + + return devm_gpiochip_add_data(&pdev->dev, &priv->gp, priv); +} + +static const struct of_device_id rzv2m_pwc_gpio_of_match[] =3D { + { .compatible =3D "renesas,rzv2m-pwc-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzv2m_pwc_gpio_of_match); + +static struct platform_driver rzv2m_pwc_gpio_driver =3D { + .probe =3D rzv2m_pwc_gpio_probe, + .driver =3D { + .name =3D "rzv2m_pwc_gpio", + .of_match_table =3D of_match_ptr(rzv2m_pwc_gpio_of_match), + }, +}; +module_platform_driver(rzv2m_pwc_gpio_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Fabrizio Castro "); +MODULE_DESCRIPTION("Renesas RZ/V2M PWC GPIO"); --=20 2.34.1 From nobody Thu Sep 18 00:01:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED906C4332F for ; Tue, 13 Dec 2022 22:44:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236812AbiLMWoT (ORCPT ); Tue, 13 Dec 2022 17:44:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236798AbiLMWoE (ORCPT ); Tue, 13 Dec 2022 17:44:04 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D1FFF2314D; Tue, 13 Dec 2022 14:43:47 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,242,1665414000"; d="scan'208";a="143229849" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 14 Dec 2022 07:43:47 +0900 Received: from mulinux.home (unknown [10.226.93.1]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2149140F4527; Wed, 14 Dec 2022 07:43:41 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH 5/5] power: reset: Add new driver for RZ/V2M PWC poweroff Date: Tue, 13 Dec 2022 22:43:10 +0000 Message-Id: <20221213224310.543243-6-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> References: <20221213224310.543243-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RZ/V2M PWC IP controls external power supplies and therefore can turn the power supplies off when powering down the system. PWC is essentially a Multi-Function Device (MFD), and this driver relies on syscon and simple-mfd to integrate within the larger scheme of things. Signed-off-by: Fabrizio Castro --- drivers/power/reset/Kconfig | 10 +++ drivers/power/reset/Makefile | 1 + drivers/power/reset/rzv2m-pwc-poweroff.c | 81 ++++++++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 drivers/power/reset/rzv2m-pwc-poweroff.c diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index a8c46ba5878f..9f7c9ed1a36e 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -303,4 +303,14 @@ config POWER_MLXBF help This driver supports reset or low power mode handling for Mellanox Blue= Field. =20 +config POWER_RESET_RZV2M_PWC + tristate "Renesas RZ/V2M PWC Power OFF" + depends on MFD_SYSCON + depends on ARCH_R9A09G011 || COMPILE_TEST + help + The RZ/V2M PWC IP controls external power supplies and therefore can + turn the power supplies off when powering down the system. + Enable this driver when PWC is in control of the system power supplies + and it's the preferred way to shutdown the system. + endif diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index 0a39424fc558..f05a8abff2eb 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -36,3 +36,4 @@ obj-$(CONFIG_SYSCON_REBOOT_MODE) +=3D syscon-reboot-mode.o obj-$(CONFIG_POWER_RESET_SC27XX) +=3D sc27xx-poweroff.o obj-$(CONFIG_NVMEM_REBOOT_MODE) +=3D nvmem-reboot-mode.o obj-$(CONFIG_POWER_MLXBF) +=3D pwr-mlxbf.o +obj-$(CONFIG_POWER_RESET_RZV2M_PWC) +=3D rzv2m-pwc-poweroff.o diff --git a/drivers/power/reset/rzv2m-pwc-poweroff.c b/drivers/power/reset= /rzv2m-pwc-poweroff.c new file mode 100644 index 000000000000..e9bd16e65b6a --- /dev/null +++ b/drivers/power/reset/rzv2m-pwc-poweroff.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Renesas Electronics Corporation + * + * Reset driver for Renesas RZ/V2M External Power Sequence Controller (PWC) + */ + +#include +#include +#include +#include +#include + +#define PWC_PWCRST 0x00 +#define PWC_PWCCKEN 0x04 +#define PWC_PWCCTL 0x50 + +#define PWC_PWCRST_RSTSOFTAX 0x1 +#define PWC_PWCCKEN_ENGCKMAIN 0x1 +#define PWC_PWCCTL_PWOFF 0x1 + +struct rzv2m_pwc_poweroff_priv { + struct regmap *regmap; + struct device *dev; +}; + +static int rzv2m_pwc_poweroff(struct sys_off_data *data) +{ + struct rzv2m_pwc_poweroff_priv *priv =3D + (struct rzv2m_pwc_poweroff_priv *)data->cb_data; + + regmap_write(priv->regmap, PWC_PWCRST, PWC_PWCRST_RSTSOFTAX); + regmap_write(priv->regmap, PWC_PWCCKEN, PWC_PWCCKEN_ENGCKMAIN); + regmap_write(priv->regmap, PWC_PWCCTL, PWC_PWCCTL_PWOFF); + + mdelay(150); + + dev_err(priv->dev, "Failed to power off the system"); + + return NOTIFY_DONE; +} + +static int rzv2m_pwc_poweroff_probe(struct platform_device *pdev) +{ + struct rzv2m_pwc_poweroff_priv *priv; + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "regmap"); + + if (IS_ERR(priv->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->regmap), + "Can't find regmap property"); + + priv->dev =3D &pdev->dev; + + return devm_register_power_off_handler(&pdev->dev, rzv2m_pwc_poweroff, + priv); +} + +static const struct of_device_id rzv2m_pwc_poweroff_of_match[] =3D { + { .compatible =3D "renesas,rzv2m-pwc-poweroff" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzv2m_pwc_poweroff_of_match); + +static struct platform_driver rzv2m_pwc_poweroff_driver =3D { + .probe =3D rzv2m_pwc_poweroff_probe, + .driver =3D { + .name =3D "rzv2m_pwc_poweroff", + .of_match_table =3D of_match_ptr(rzv2m_pwc_poweroff_of_match), + }, +}; +module_platform_driver(rzv2m_pwc_poweroff_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Fabrizio Castro "); +MODULE_DESCRIPTION("Renesas RZ/V2M PWC power OFF driver"); --=20 2.34.1