From nobody Wed Sep 17 23:53:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1C3AC4332F for ; Tue, 13 Dec 2022 16:43:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236264AbiLMQnt (ORCPT ); Tue, 13 Dec 2022 11:43:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236199AbiLMQnc (ORCPT ); Tue, 13 Dec 2022 11:43:32 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F5615FFC; Tue, 13 Dec 2022 08:43:27 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BDGhCAL042949; Tue, 13 Dec 2022 10:43:12 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1670949792; bh=1sdVIeBxoZTAw0wZ5K5+Bhj/ogaEqZRyuZbryv9UwlI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hEW/fUPwFxgKXn7fr86wLCXDNZ70m/iqH5o4ynC2TPpH/lq/7oF6gY5/BZIr8Z5Xd LmwV5M4c/EMrIEeguZVb+MOXvKgQ8JGkFZEFe1dPcYkFsVEqfDe3qt0ySzrnQb/Lv9 BzN72XT5J4uN6OgJzDSmco12s8r0gvj7CedKJQAw= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BDGhCoP112121 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Dec 2022 10:43:12 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 13 Dec 2022 10:43:12 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 13 Dec 2022 10:43:12 -0600 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BDGh6gJ034997; Tue, 13 Dec 2022 10:43:09 -0600 From: Vignesh Raghavendra To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski CC: , , , Vignesh Raghavendra , Subject: [PATCH v3 1/5] dt-bindings: dma: ti: k3-bcdma: Add bindings for BCDMA CSI RX Date: Tue, 13 Dec 2022 22:13:00 +0530 Message-ID: <20221213164304.1126945-2-vigneshr@ti.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221213164304.1126945-1-vigneshr@ti.com> References: <20221213164304.1126945-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" AM62A SoC has a dedicated BCDMA that serves Camera Serial Interface (CSI) IP. Add new compatible for the same. Unlike system BCDMA, this instance only has RX DMA channels and lack TX or block copy channel. Thus make those properties optional. Additionally CSI RX has independent power domain, add the binding for the same. Signed-off-by: Vignesh Raghavendra Acked-by: Peter Ujfalusi Reviewed-by: Krzysztof Kozlowski --- v3: Add min/max constraints for reg-names and reg on per compatible basis v2: reorder compatibles alphabetically Fix reg defintion to min 3 and max 5 Keep top level constraints as is and further restrict variants within "if-else" blocks .../devicetree/bindings/dma/ti/k3-bcdma.yaml | 77 ++++++++++++++----- 1 file changed, 59 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml b/Docum= entation/devicetree/bindings/dma/ti/k3-bcdma.yaml index 08627d91e607..2bc48dfd3396 100644 --- a/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml +++ b/Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml @@ -28,13 +28,19 @@ description: | PDMAs can be configured via BCDMA split channel's peer registers to matc= h with the configuration of the legacy peripheral. =20 -allOf: - - $ref: /schemas/dma/dma-controller.yaml# - - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# - properties: compatible: - const: ti,am64-dmss-bcdma + enum: + - ti,am62a-dmss-bcdma-csirx + - ti,am64-dmss-bcdma + + reg: + minItems: 3 + maxItems: 5 + + reg-names: + minItems: 3 + maxItems: 5 =20 "#dma-cells": const: 3 @@ -65,19 +71,13 @@ properties: =20 cell 3: ASEL value for the channel =20 - reg: - maxItems: 5 - - reg-names: - items: - - const: gcfg - - const: bchanrt - - const: rchanrt - - const: tchanrt - - const: ringrt - msi-parent: true =20 + power-domains: + description: + Power domain if available + maxItems: 1 + ti,asel: $ref: /schemas/types.yaml#/definitions/uint32 description: ASEL value for non slave channels @@ -123,10 +123,51 @@ required: - msi-parent - ti,sci - ti,sci-dev-id - - ti,sci-rm-range-bchan - - ti,sci-rm-range-tchan - ti,sci-rm-range-rchan =20 +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# + + - if: + properties: + compatible: + contains: + const: ti,am62a-dmss-bcdma-csirx + then: + properties: + ti,sci-rm-range-bchan: false + ti,sci-rm-range-tchan: false + + reg: + maxItems: 3 + + reg-names: + items: + - const: gcfg + - const: rchanrt + - const: ringrt + + required: + - power-domains + + else: + properties: + reg: + minItems: 5 + + reg-names: + items: + - const: gcfg + - const: bchanrt + - const: rchanrt + - const: tchanrt + - const: ringrt + + required: + - ti,sci-rm-range-bchan + - ti,sci-rm-range-tchan + unevaluatedProperties: false =20 examples: --=20 2.38.1 From nobody Wed Sep 17 23:53:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FE1DC4708D for ; Tue, 13 Dec 2022 16:43:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236225AbiLMQng (ORCPT ); Tue, 13 Dec 2022 11:43:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236147AbiLMQn1 (ORCPT ); Tue, 13 Dec 2022 11:43:27 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDF432BC4; Tue, 13 Dec 2022 08:43:25 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BDGhF4V042968; Tue, 13 Dec 2022 10:43:15 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1670949795; bh=5eBEqont1Hh66nEc8s7Ovin4BNz2G7HwxSF5/nTvwu8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LxfwkajrXiy7c2mhpHKiG7RS36PCiVkGpANNK9D52aAVhT7dGMy+Enjbhb+EhT+qB xgtm6b9S3PW4F7OhxURZDrm35KCm0fBuRSQ9lBQ99GRgkpvCtk7pX2CDjLf+WOW/E7 wkKOZJVG6DOmaO/O1Y9ptUbfeJPlZeD+KC45m3uQ= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BDGhF0t112141 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Dec 2022 10:43:15 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 13 Dec 2022 10:43:15 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 13 Dec 2022 10:43:15 -0600 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BDGh6gK034997; Tue, 13 Dec 2022 10:43:12 -0600 From: Vignesh Raghavendra To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski CC: , , , Vignesh Raghavendra , Subject: [PATCH v3 2/5] dmaengine: ti: k3-udma: Fix BCDMA for case w/o BCHAN Date: Tue, 13 Dec 2022 22:13:01 +0530 Message-ID: <20221213164304.1126945-3-vigneshr@ti.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221213164304.1126945-1-vigneshr@ti.com> References: <20221213164304.1126945-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Reusing loop iterator fails if BCHAN is not present as iterator is uninitialized Signed-off-by: Vignesh Raghavendra Acked-by: Peter Ujfalusi --- drivers/dma/ti/k3-udma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index ce8b80bb34d7..aa50d46fa856 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -4774,7 +4774,10 @@ static int bcdma_setup_resources(struct udma_dev *ud) irq_res.desc[i].num =3D rm_res->desc[i].num; } } + } else { + i =3D 0; } + if (ud->tchan_cnt) { rm_res =3D tisci_rm->rm_ranges[RM_RANGE_TCHAN]; if (IS_ERR(rm_res)) { --=20 2.38.1 From nobody Wed Sep 17 23:53:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFC5AC10F1B for ; Tue, 13 Dec 2022 16:44:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236258AbiLMQoE (ORCPT ); Tue, 13 Dec 2022 11:44:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236221AbiLMQnf (ORCPT ); Tue, 13 Dec 2022 11:43:35 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA804EB3; Tue, 13 Dec 2022 08:43:33 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BDGhIx8043204; Tue, 13 Dec 2022 10:43:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1670949798; bh=MNTh7fcR4cK+3mQwKYc6KkmSaImly7w3U82jURq1P8U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uBHBRyZsI5R01WbZfWJvPPCqCtNqhrdVc6MlJ1MA1TpnIRGo2YuVJ+OeCHqquCyeb P4X4IE5qCWdXr2v6Bxy52gg4ma5eeXuKC6jEXiQKyJpyjPD9DOWHYL8ryOPPG8Yjt5 xMWtn/i3HYrXActWzz2g/J9QpgveVmUblfdZD75Y= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BDGhI4O112161 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Dec 2022 10:43:18 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 13 Dec 2022 10:43:18 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 13 Dec 2022 10:43:17 -0600 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BDGh6gL034997; Tue, 13 Dec 2022 10:43:15 -0600 From: Vignesh Raghavendra To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski CC: , , , Vignesh Raghavendra , Subject: [PATCH v3 3/5] dmaengine: ti: k3-psil-am62a: Add AM62Ax PSIL and PDMA data Date: Tue, 13 Dec 2022 22:13:02 +0530 Message-ID: <20221213164304.1126945-4-vigneshr@ti.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221213164304.1126945-1-vigneshr@ti.com> References: <20221213164304.1126945-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jai Luthra Add PSIL and PDMA data for AM62Ax SoC. Signed-off-by: Jai Luthra Signed-off-by: Vignesh Raghavendra Acked-by: Peter Ujfalusi --- drivers/dma/ti/Makefile | 3 +- drivers/dma/ti/k3-psil-am62a.c | 196 +++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-psil-priv.h | 1 + drivers/dma/ti/k3-psil.c | 1 + 4 files changed, 200 insertions(+), 1 deletion(-) create mode 100644 drivers/dma/ti/k3-psil-am62a.c diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile index b53d05b11ca5..bd1e07fda559 100644 --- a/drivers/dma/ti/Makefile +++ b/drivers/dma/ti/Makefile @@ -10,6 +10,7 @@ k3-psil-lib-objs :=3D k3-psil.o \ k3-psil-j7200.o \ k3-psil-am64.o \ k3-psil-j721s2.o \ - k3-psil-am62.o + k3-psil-am62.o \ + k3-psil-am62a.o obj-$(CONFIG_TI_K3_PSIL) +=3D k3-psil-lib.o obj-$(CONFIG_TI_DMA_CROSSBAR) +=3D dma-crossbar.o diff --git a/drivers/dma/ti/k3-psil-am62a.c b/drivers/dma/ti/k3-psil-am62a.c new file mode 100644 index 000000000000..ca9d71f91422 --- /dev/null +++ b/drivers/dma/ti/k3-psil-am62a.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com + */ + +#include + +#include "k3-psil-priv.h" + +#define PSIL_PDMA_XY_TR(x) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_PDMA_XY, \ + .mapped_channel_id =3D -1, \ + .default_flow_id =3D -1, \ + }, \ + } + +#define PSIL_PDMA_XY_PKT(x) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_PDMA_XY, \ + .mapped_channel_id =3D -1, \ + .default_flow_id =3D -1, \ + .pkt_mode =3D 1, \ + }, \ + } + +#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_NATIVE, \ + .pkt_mode =3D 1, \ + .needs_epib =3D 1, \ + .psd_size =3D 16, \ + .mapped_channel_id =3D ch, \ + .flow_start =3D flow_base, \ + .flow_num =3D flow_cnt, \ + .default_flow_id =3D flow_base, \ + }, \ + } + +#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_NATIVE, \ + .pkt_mode =3D 1, \ + .needs_epib =3D 1, \ + .psd_size =3D 64, \ + .mapped_channel_id =3D ch, \ + .flow_start =3D flow_base, \ + .flow_num =3D flow_cnt, \ + .default_flow_id =3D default_flow, \ + .notdpkt =3D tx, \ + }, \ + } + +#define PSIL_PDMA_MCASP(x) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_PDMA_XY, \ + .pdma_acc32 =3D 1, \ + .pdma_burst =3D 1, \ + }, \ + } + +#define PSIL_CSI2RX(x) \ + { \ + .thread_id =3D x, \ + .ep_config =3D { \ + .ep_type =3D PSIL_EP_NATIVE, \ + }, \ + } + +/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ +static struct psil_ep am62a_src_ep_map[] =3D { + /* SAUL */ + PSIL_SAUL(0x7504, 20, 35, 8, 35, 0), + PSIL_SAUL(0x7505, 21, 35, 8, 36, 0), + PSIL_SAUL(0x7506, 22, 43, 8, 43, 0), + PSIL_SAUL(0x7507, 23, 43, 8, 44, 0), + /* PDMA_MAIN0 - SPI0-3 */ + PSIL_PDMA_XY_PKT(0x4302), + PSIL_PDMA_XY_PKT(0x4303), + PSIL_PDMA_XY_PKT(0x4304), + PSIL_PDMA_XY_PKT(0x4305), + PSIL_PDMA_XY_PKT(0x4306), + PSIL_PDMA_XY_PKT(0x4307), + PSIL_PDMA_XY_PKT(0x4308), + PSIL_PDMA_XY_PKT(0x4309), + PSIL_PDMA_XY_PKT(0x430a), + PSIL_PDMA_XY_PKT(0x430b), + PSIL_PDMA_XY_PKT(0x430c), + PSIL_PDMA_XY_PKT(0x430d), + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0x4400), + PSIL_PDMA_XY_PKT(0x4401), + PSIL_PDMA_XY_PKT(0x4402), + PSIL_PDMA_XY_PKT(0x4403), + PSIL_PDMA_XY_PKT(0x4404), + PSIL_PDMA_XY_PKT(0x4405), + PSIL_PDMA_XY_PKT(0x4406), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0x4500), + PSIL_PDMA_MCASP(0x4501), + PSIL_PDMA_MCASP(0x4502), + /* CPSW3G */ + PSIL_ETHERNET(0x4600, 19, 19, 16), + /* CSI2RX */ + PSIL_CSI2RX(0x5000), + PSIL_CSI2RX(0x5001), + PSIL_CSI2RX(0x5002), + PSIL_CSI2RX(0x5003), + PSIL_CSI2RX(0x5004), + PSIL_CSI2RX(0x5005), + PSIL_CSI2RX(0x5006), + PSIL_CSI2RX(0x5007), + PSIL_CSI2RX(0x5008), + PSIL_CSI2RX(0x5009), + PSIL_CSI2RX(0x500a), + PSIL_CSI2RX(0x500b), + PSIL_CSI2RX(0x500c), + PSIL_CSI2RX(0x500d), + PSIL_CSI2RX(0x500e), + PSIL_CSI2RX(0x500f), + PSIL_CSI2RX(0x5010), + PSIL_CSI2RX(0x5011), + PSIL_CSI2RX(0x5012), + PSIL_CSI2RX(0x5013), + PSIL_CSI2RX(0x5014), + PSIL_CSI2RX(0x5015), + PSIL_CSI2RX(0x5016), + PSIL_CSI2RX(0x5017), + PSIL_CSI2RX(0x5018), + PSIL_CSI2RX(0x5019), + PSIL_CSI2RX(0x501a), + PSIL_CSI2RX(0x501b), + PSIL_CSI2RX(0x501c), + PSIL_CSI2RX(0x501d), + PSIL_CSI2RX(0x501e), + PSIL_CSI2RX(0x501f), +}; + +/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ +static struct psil_ep am62a_dst_ep_map[] =3D { + /* SAUL */ + PSIL_SAUL(0xf500, 27, 83, 8, 83, 1), + PSIL_SAUL(0xf501, 28, 91, 8, 91, 1), + /* PDMA_MAIN0 - SPI0-3 */ + PSIL_PDMA_XY_PKT(0xc302), + PSIL_PDMA_XY_PKT(0xc303), + PSIL_PDMA_XY_PKT(0xc304), + PSIL_PDMA_XY_PKT(0xc305), + PSIL_PDMA_XY_PKT(0xc306), + PSIL_PDMA_XY_PKT(0xc307), + PSIL_PDMA_XY_PKT(0xc308), + PSIL_PDMA_XY_PKT(0xc309), + PSIL_PDMA_XY_PKT(0xc30a), + PSIL_PDMA_XY_PKT(0xc30b), + PSIL_PDMA_XY_PKT(0xc30c), + PSIL_PDMA_XY_PKT(0xc30d), + /* PDMA_MAIN1 - UART0-6 */ + PSIL_PDMA_XY_PKT(0xc400), + PSIL_PDMA_XY_PKT(0xc401), + PSIL_PDMA_XY_PKT(0xc402), + PSIL_PDMA_XY_PKT(0xc403), + PSIL_PDMA_XY_PKT(0xc404), + PSIL_PDMA_XY_PKT(0xc405), + PSIL_PDMA_XY_PKT(0xc406), + /* PDMA_MAIN2 - MCASP0-2 */ + PSIL_PDMA_MCASP(0xc500), + PSIL_PDMA_MCASP(0xc501), + PSIL_PDMA_MCASP(0xc502), + /* CPSW3G */ + PSIL_ETHERNET(0xc600, 19, 19, 8), + PSIL_ETHERNET(0xc601, 20, 27, 8), + PSIL_ETHERNET(0xc602, 21, 35, 8), + PSIL_ETHERNET(0xc603, 22, 43, 8), + PSIL_ETHERNET(0xc604, 23, 51, 8), + PSIL_ETHERNET(0xc605, 24, 59, 8), + PSIL_ETHERNET(0xc606, 25, 67, 8), + PSIL_ETHERNET(0xc607, 26, 75, 8), +}; + +struct psil_ep_map am62a_ep_map =3D { + .name =3D "am62a", + .src =3D am62a_src_ep_map, + .src_count =3D ARRAY_SIZE(am62a_src_ep_map), + .dst =3D am62a_dst_ep_map, + .dst_count =3D ARRAY_SIZE(am62a_dst_ep_map), +}; diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h index 74fa9ec02968..abd650bb7600 100644 --- a/drivers/dma/ti/k3-psil-priv.h +++ b/drivers/dma/ti/k3-psil-priv.h @@ -43,5 +43,6 @@ extern struct psil_ep_map j7200_ep_map; extern struct psil_ep_map am64_ep_map; extern struct psil_ep_map j721s2_ep_map; extern struct psil_ep_map am62_ep_map; +extern struct psil_ep_map am62a_ep_map; =20 #endif /* K3_PSIL_PRIV_H_ */ diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c index 8b6533a1eeeb..2da6988a0e7b 100644 --- a/drivers/dma/ti/k3-psil.c +++ b/drivers/dma/ti/k3-psil.c @@ -24,6 +24,7 @@ static const struct soc_device_attribute k3_soc_devices[]= =3D { { .family =3D "AM64X", .data =3D &am64_ep_map }, { .family =3D "J721S2", .data =3D &j721s2_ep_map }, { .family =3D "AM62X", .data =3D &am62_ep_map }, + { .family =3D "AM62AX", .data =3D &am62a_ep_map }, { /* sentinel */ } }; =20 --=20 2.38.1 From nobody Wed Sep 17 23:53:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A64A7C4332F for ; Tue, 13 Dec 2022 16:43:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236242AbiLMQnl (ORCPT ); Tue, 13 Dec 2022 11:43:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236190AbiLMQn1 (ORCPT ); Tue, 13 Dec 2022 11:43:27 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25EAA268; Tue, 13 Dec 2022 08:43:27 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BDGhLEU114201; Tue, 13 Dec 2022 10:43:21 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1670949801; bh=w2Ue5WDDYL9x4Hgu6bdWROqq/0qU9t4BO6DzYi2Kw+M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HnE55/SMN2jaQMP5FeYwi/jv9sKnhDra2+OCh0XCMI4KooatbjreAHoOGD0Xh2pVf 9n3IIjFLpwIcoRksBrWk6PMyCuCBIk0Q97A5EVrVPpWtgVe5+5uL1cOZBVJECba/ia koX6fBOeWj8FPj0xsIEuqcYtc/GPLEYwHRztdX/c= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BDGhL47073245 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Dec 2022 10:43:21 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 13 Dec 2022 10:43:20 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 13 Dec 2022 10:43:20 -0600 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BDGh6gM034997; Tue, 13 Dec 2022 10:43:18 -0600 From: Vignesh Raghavendra To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski CC: , , , Vignesh Raghavendra , Subject: [PATCH v3 4/5] dmaengine: ti: k3-udma: Add support for DMAs on AM62A SoC Date: Tue, 13 Dec 2022 22:13:03 +0530 Message-ID: <20221213164304.1126945-5-vigneshr@ti.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221213164304.1126945-1-vigneshr@ti.com> References: <20221213164304.1126945-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" AM62A SoC has a BCDMA and PKTDMA as systems DMAs for service various peripherals similar to AM64 SoC. Add support for the same. Signed-off-by: Vignesh Raghavendra Acked-by: Peter Ujfalusi --- drivers/dma/ti/k3-udma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index aa50d46fa856..c1005d17b42e 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -4386,6 +4386,7 @@ static const struct soc_device_attribute k3_soc_devic= es[] =3D { { .family =3D "AM64X", .data =3D &am64_soc_data }, { .family =3D "J721S2", .data =3D &j721e_soc_data}, { .family =3D "AM62X", .data =3D &am64_soc_data }, + { .family =3D "AM62AX", .data =3D &am64_soc_data }, { /* sentinel */ } }; =20 --=20 2.38.1 From nobody Wed Sep 17 23:53:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5205CC4332F for ; Tue, 13 Dec 2022 16:43:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235911AbiLMQny (ORCPT ); Tue, 13 Dec 2022 11:43:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236204AbiLMQnd (ORCPT ); Tue, 13 Dec 2022 11:43:33 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC23D2AC1; Tue, 13 Dec 2022 08:43:31 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BDGhOrT043041; Tue, 13 Dec 2022 10:43:24 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1670949804; bh=lSeG+4HQ3gyOii17ukc7PlcSnkdUoIsNZqiqck3q650=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=O/goOkBVWekE6VNa2kdMtSSwaEGAq7DG+i/uLi+0ubskeE27wMbAJNtCF0+tr4YY7 T0l5cWiURgzytV6Jq0JOXhlQpggdJCzqZv0rrlFPLOELuWaGVUKJU+auvQyV9VwrVl D0Da9MSKanKnD1DXXvbfe462H9ECjZacKKfwHed8= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BDGhOWq073274 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Dec 2022 10:43:24 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 13 Dec 2022 10:43:23 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 13 Dec 2022 10:43:23 -0600 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BDGh6gN034997; Tue, 13 Dec 2022 10:43:21 -0600 From: Vignesh Raghavendra To: Peter Ujfalusi , Vinod Koul , Rob Herring , Krzysztof Kozlowski CC: , , , Vignesh Raghavendra , Subject: [PATCH v3 5/5] dmaengine: ti: k3-udma: Add support for BCDMA CSI RX Date: Tue, 13 Dec 2022 22:13:04 +0530 Message-ID: <20221213164304.1126945-6-vigneshr@ti.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221213164304.1126945-1-vigneshr@ti.com> References: <20221213164304.1126945-1-vigneshr@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" BCDMA CSI RX present on AM62Ax SoC is a dedicated DMA for servicing Camera Serial Interface (CSI) IP. Add support for the same. Signed-off-by: Vignesh Raghavendra Acked-by: Peter Ujfalusi --- drivers/dma/ti/k3-udma.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index c1005d17b42e..1d3d1b387b96 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -135,6 +135,7 @@ struct udma_match_data { u32 flags; u32 statictr_z_mask; u8 burst_size[3]; + struct udma_soc_data *soc_data; }; =20 struct udma_soc_data { @@ -4295,6 +4296,25 @@ static struct udma_match_data j721e_mcu_data =3D { }, }; =20 +static struct udma_soc_data am62a_dmss_csi_soc_data =3D { + .oes =3D { + .bcdma_rchan_data =3D 0xe00, + .bcdma_rchan_ring =3D 0x1000, + }, +}; + +static struct udma_match_data am62a_bcdma_csirx_data =3D { + .type =3D DMA_TYPE_BCDMA, + .psil_base =3D 0x3100, + .enable_memcpy_support =3D false, + .burst_size =3D { + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ + 0, /* No H Channels */ + 0, /* No UH Channels */ + }, + .soc_data =3D &am62a_dmss_csi_soc_data, +}; + static struct udma_match_data am64_bcdma_data =3D { .type =3D DMA_TYPE_BCDMA, .psil_base =3D 0x2000, /* for tchan and rchan, not applicable to bchan */ @@ -4344,6 +4364,10 @@ static const struct of_device_id udma_of_match[] =3D= { .compatible =3D "ti,am64-dmss-pktdma", .data =3D &am64_pktdma_data, }, + { + .compatible =3D "ti,am62a-dmss-bcdma-csirx", + .data =3D &am62a_bcdma_csirx_data, + }, { /* Sentinel */ }, }; =20 @@ -5274,12 +5298,15 @@ static int udma_probe(struct platform_device *pdev) } ud->match_data =3D match->data; =20 - soc =3D soc_device_match(k3_soc_devices); - if (!soc) { - dev_err(dev, "No compatible SoC found\n"); - return -ENODEV; + ud->soc_data =3D ud->match_data->soc_data; + if (!ud->soc_data) { + soc =3D soc_device_match(k3_soc_devices); + if (!soc) { + dev_err(dev, "No compatible SoC found\n"); + return -ENODEV; + } + ud->soc_data =3D soc->data; } - ud->soc_data =3D soc->data; =20 ret =3D udma_get_mmrs(pdev, ud); if (ret) --=20 2.38.1