From nobody Thu Sep 18 01:20:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69B65C4167B for ; Tue, 13 Dec 2022 11:24:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235330AbiLMLXu (ORCPT ); Tue, 13 Dec 2022 06:23:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230061AbiLMLXi (ORCPT ); Tue, 13 Dec 2022 06:23:38 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D37401183B; Tue, 13 Dec 2022 03:23:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670930616; x=1702466616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O6Yhf97L/pahv9g9FCa7RxbB9udp6xC8MQ4GIoD13oM=; b=dXhJkT6MAKRBo1qXGxX6QU+QcVe2H9rAdR6GBSWpw3WXbK3VaC4CHqxN 4qszrpVazdNrZb1BOTPYV9Ks/bMlvGhcemacaNtu2JNQuDBo6b2Qdqrvl 4YThPAP3H2HT3jCG6HD6/Z+hHg5I9ob85xixUb9Hly6qRDPiQ9dwOOlBR RTZKQ045oc3nzh20+CztJgVZsMim4T11UWAhmcUWhbej2lvrbOMHzm9po wRC4YRtu0EAmycbBKpOftVTdx0Aleaua9Ac9wPfhJu4klaPUM3IxNqwWd IuYRfN+YnCtVBc98tdgCyOosZ7FLTw2c7rRenBZ238DrQtXicEOvlxpbO A==; X-IronPort-AV: E=Sophos;i="5.96,241,1665471600"; d="scan'208";a="192862226" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Dec 2022 04:23:36 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 13 Dec 2022 04:23:35 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 13 Dec 2022 04:23:32 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 1/4] ASoC: dt-bindings: microchip: use proper naming syntax Date: Tue, 13 Dec 2022 13:28:48 +0200 Message-ID: <20221213112851.89212-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221213112851.89212-1-claudiu.beznea@microchip.com> References: <20221213112851.89212-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use the following syntax for Microchip ASoC YAML files: vendor,device.yaml Signed-off-by: Claudiu Beznea Acked-by: Krzysztof Kozlowski --- .../sound/{mchp,i2s-mcc.yaml =3D> microchip,sama7g5-i2smcc.yaml} | 2 +- .../sound/{microchip,pdmc.yaml =3D> microchip,sama7g5-pdmc.yaml} | 2 +- .../sound/{mchp,spdifrx.yaml =3D> microchip,sama7g5-spdifrx.yaml} | 2 +- .../sound/{mchp,spdiftx.yaml =3D> microchip,sama7g5-spdiftx.yaml} | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) rename Documentation/devicetree/bindings/sound/{mchp,i2s-mcc.yaml =3D> mic= rochip,sama7g5-i2smcc.yaml} (97%) rename Documentation/devicetree/bindings/sound/{microchip,pdmc.yaml =3D> m= icrochip,sama7g5-pdmc.yaml} (97%) rename Documentation/devicetree/bindings/sound/{mchp,spdifrx.yaml =3D> mic= rochip,sama7g5-spdifrx.yaml} (95%) rename Documentation/devicetree/bindings/sound/{mchp,spdiftx.yaml =3D> mic= rochip,sama7g5-spdiftx.yaml} (95%) diff --git a/Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml b/Do= cumentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.yaml similarity index 97% rename from Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml rename to Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.= yaml index 0481315cb5f2..68423f43ac3a 100644 --- a/Documentation/devicetree/bindings/sound/mchp,i2s-mcc.yaml +++ b/Documentation/devicetree/bindings/sound/microchip,sama7g5-i2smcc.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/sound/mchp,i2s-mcc.yaml# +$id: http://devicetree.org/schemas/sound/microchip,sama7g5-i2smcc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Microchip I2S Multi-Channel Controller diff --git a/Documentation/devicetree/bindings/sound/microchip,pdmc.yaml b/= Documentation/devicetree/bindings/sound/microchip,sama7g5-pdmc.yaml similarity index 97% rename from Documentation/devicetree/bindings/sound/microchip,pdmc.yaml rename to Documentation/devicetree/bindings/sound/microchip,sama7g5-pdmc.ya= ml index 04414eb4ada9..7cc80dac980c 100644 --- a/Documentation/devicetree/bindings/sound/microchip,pdmc.yaml +++ b/Documentation/devicetree/bindings/sound/microchip,sama7g5-pdmc.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/sound/microchip,pdmc.yaml# +$id: http://devicetree.org/schemas/sound/microchip,sama7g5-pdmc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Microchip Pulse Density Microphone Controller diff --git a/Documentation/devicetree/bindings/sound/mchp,spdifrx.yaml b/Do= cumentation/devicetree/bindings/sound/microchip,sama7g5-spdifrx.yaml similarity index 95% rename from Documentation/devicetree/bindings/sound/mchp,spdifrx.yaml rename to Documentation/devicetree/bindings/sound/microchip,sama7g5-spdifrx= .yaml index 970311143253..5121ea1600ae 100644 --- a/Documentation/devicetree/bindings/sound/mchp,spdifrx.yaml +++ b/Documentation/devicetree/bindings/sound/microchip,sama7g5-spdifrx.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/sound/mchp,spdifrx.yaml# +$id: http://devicetree.org/schemas/sound/microchip,sama7g5-spdifrx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Microchip S/PDIF Rx Controller Device Tree Bindings diff --git a/Documentation/devicetree/bindings/sound/mchp,spdiftx.yaml b/Do= cumentation/devicetree/bindings/sound/microchip,sama7g5-spdiftx.yaml similarity index 95% rename from Documentation/devicetree/bindings/sound/mchp,spdiftx.yaml rename to Documentation/devicetree/bindings/sound/microchip,sama7g5-spdiftx= .yaml index d5c022e49526..d13e76269250 100644 --- a/Documentation/devicetree/bindings/sound/mchp,spdiftx.yaml +++ b/Documentation/devicetree/bindings/sound/microchip,sama7g5-spdiftx.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/sound/mchp,spdiftx.yaml# +$id: http://devicetree.org/schemas/sound/microchip,sama7g5-spdiftx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Microchip S/PDIF Tx Controller Device Tree Bindings --=20 2.34.1 From nobody Thu Sep 18 01:20:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED83CC4332F for ; Tue, 13 Dec 2022 11:24:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235305AbiLMLYV (ORCPT ); Tue, 13 Dec 2022 06:24:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235228AbiLMLXl (ORCPT ); Tue, 13 Dec 2022 06:23:41 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C28FB31C; Tue, 13 Dec 2022 03:23:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670930619; x=1702466619; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mr8bvoDR3kP1Rf0wpZPD+P1CiMLnicoQSVkgRqx6GS4=; b=Jvf0gRpYMZ291v8vTjNdYvh4fOGByIbHa5heNq5G7KQY12itF7hmImgH cZZN8y0M0waa+4/veW+x0IFQrEsl6A8RFBMAClysAI33nhLIlTK6pkDK6 srcpgPMs15qwlgwWC0xfm9nC4Lq9bVLxkruKRNDB4CXJLnDWzWyyshvNm xSOndCDJHgIzF7438aUWnvlUa2asZMK0/6YgX+raBTWRnVppz9oRGBmQQ 3kELcQi4iodSUc0FnWLBK0Mo60tnAXKGXQ7uwhbwcc9B8IJUaC9afFu4l tfP+DuXjF80dgdRBP4fw2FRbPlzD0UtascO67EzZ3O8UiuIxoPfKqnHWW w==; X-IronPort-AV: E=Sophos;i="5.96,241,1665471600"; d="scan'208";a="192862229" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Dec 2022 04:23:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 13 Dec 2022 04:23:38 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 13 Dec 2022 04:23:35 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 2/4] ASoC: mchp-pdmc: use runtime pm for clock power saving Date: Tue, 13 Dec 2022 13:28:49 +0200 Message-ID: <20221213112851.89212-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221213112851.89212-1-claudiu.beznea@microchip.com> References: <20221213112851.89212-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement clock power saving taking advantage of runtime PM infrastructure. This simplifies the code and allow using the same infrastructure for suspend to RAM functionalities. Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-pdmc.c | 126 ++++++++++++++++++++++++------------ 1 file changed, 84 insertions(+), 42 deletions(-) diff --git a/sound/soc/atmel/mchp-pdmc.c b/sound/soc/atmel/mchp-pdmc.c index 44aefbd5b62c..f184404e74e5 100644 --- a/sound/soc/atmel/mchp-pdmc.c +++ b/sound/soc/atmel/mchp-pdmc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 #include @@ -115,7 +116,6 @@ struct mchp_pdmc { int mic_no; int sinc_order; bool audio_filter_en; - u8 gclk_enabled:1; }; =20 static const char *const mchp_pdmc_sinc_filter_order_text[] =3D { @@ -454,13 +454,6 @@ static int mchp_pdmc_startup(struct snd_pcm_substream = *substream, struct snd_soc_dai *dai) { struct mchp_pdmc *dd =3D snd_soc_dai_get_drvdata(dai); - int ret; - - ret =3D clk_prepare_enable(dd->pclk); - if (ret) { - dev_err(dd->dev, "failed to enable the peripheral clock: %d\n", ret); - return ret; - } =20 regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST); =20 @@ -470,14 +463,6 @@ static int mchp_pdmc_startup(struct snd_pcm_substream = *substream, return 0; } =20 -static void mchp_pdmc_shutdown(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) -{ - struct mchp_pdmc *dd =3D snd_soc_dai_get_drvdata(dai); - - clk_disable_unprepare(dd->pclk); -} - static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai) { struct mchp_pdmc *dd =3D snd_soc_dai_get_drvdata(dai); @@ -594,11 +579,6 @@ static int mchp_pdmc_hw_params(struct snd_pcm_substrea= m *substream, cfgr_val |=3D MCHP_PDMC_CFGR_BSSEL(i); } =20 - if (dd->gclk_enabled) { - clk_disable_unprepare(dd->gclk); - dd->gclk_enabled =3D 0; - } - for (osr_start =3D dd->audio_filter_en ? 64 : 8; osr_start <=3D 256 && best_diff_rate; osr_start *=3D 2) { long round_rate; @@ -620,8 +600,12 @@ static int mchp_pdmc_hw_params(struct snd_pcm_substrea= m *substream, return -EINVAL; } =20 + /* CLK is enabled by runtime PM. */ + clk_disable_unprepare(dd->gclk); + /* set the rate */ ret =3D clk_set_rate(dd->gclk, gclk_rate); + clk_prepare_enable(dd->gclk); if (ret) { dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n", gclk_rate, ret); @@ -636,9 +620,6 @@ static int mchp_pdmc_hw_params(struct snd_pcm_substream= *substream, mr_val |=3D MCHP_PDMC_MR_CHUNK(dd->addr.maxburst); dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst); =20 - clk_prepare_enable(dd->gclk); - dd->gclk_enabled =3D 1; - snd_soc_component_update_bits(comp, MCHP_PDMC_MR, MCHP_PDMC_MR_OSR_MASK | MCHP_PDMC_MR_SINCORDER_MASK | @@ -650,19 +631,6 @@ static int mchp_pdmc_hw_params(struct snd_pcm_substrea= m *substream, return 0; } =20 -static int mchp_pdmc_hw_free(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) -{ - struct mchp_pdmc *dd =3D snd_soc_dai_get_drvdata(dai); - - if (dd->gclk_enabled) { - clk_disable_unprepare(dd->gclk); - dd->gclk_enabled =3D 0; - } - - return 0; -} - static int mchp_pdmc_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { @@ -711,9 +679,7 @@ static int mchp_pdmc_trigger(struct snd_pcm_substream *= substream, static const struct snd_soc_dai_ops mchp_pdmc_dai_ops =3D { .set_fmt =3D mchp_pdmc_set_fmt, .startup =3D mchp_pdmc_startup, - .shutdown =3D mchp_pdmc_shutdown, .hw_params =3D mchp_pdmc_hw_params, - .hw_free =3D mchp_pdmc_hw_free, .trigger =3D mchp_pdmc_trigger, }; =20 @@ -864,6 +830,7 @@ static const struct regmap_config mchp_pdmc_regmap_conf= ig =3D { .readable_reg =3D mchp_pdmc_readable_reg, .writeable_reg =3D mchp_pdmc_writeable_reg, .precious_reg =3D mchp_pdmc_precious_reg, + .cache_type =3D REGCACHE_FLAT, }; =20 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd) @@ -970,6 +937,49 @@ static struct snd_dmaengine_pcm_config mchp_pdmc_confi= g =3D { .prepare_slave_config =3D snd_dmaengine_pcm_prepare_slave_config, }; =20 +static int mchp_pdmc_runtime_suspend(struct device *dev) +{ + struct mchp_pdmc *dd =3D dev_get_drvdata(dev); + + regcache_cache_only(dd->regmap, true); + + clk_disable_unprepare(dd->gclk); + clk_disable_unprepare(dd->pclk); + + return 0; +} + +static int mchp_pdmc_runtime_resume(struct device *dev) +{ + struct mchp_pdmc *dd =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_prepare_enable(dd->pclk); + if (ret) { + dev_err(dd->dev, + "failed to enable the peripheral clock: %d\n", ret); + return ret; + } + ret =3D clk_prepare_enable(dd->gclk); + if (ret) { + dev_err(dd->dev, + "failed to enable generic clock: %d\n", ret); + goto disable_pclk; + } + + regcache_cache_only(dd->regmap, false); + regcache_mark_dirty(dd->regmap); + ret =3D regcache_sync(dd->regmap); + if (ret) { + regcache_cache_only(dd->regmap, true); + clk_disable_unprepare(dd->gclk); +disable_pclk: + clk_disable_unprepare(dd->pclk); + } + + return ret; +} + static int mchp_pdmc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -1039,18 +1049,25 @@ static int mchp_pdmc_probe(struct platform_device *= pdev) dd->addr.addr =3D (dma_addr_t)res->start + MCHP_PDMC_RHR; platform_set_drvdata(pdev, dd); =20 + pm_runtime_enable(dd->dev); + if (!pm_runtime_enabled(dd->dev)) { + ret =3D mchp_pdmc_runtime_resume(dd->dev); + if (ret) + return ret; + } + /* register platform */ ret =3D devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0); if (ret) { dev_err(dev, "could not register platform: %d\n", ret); - return ret; + goto pm_runtime_suspend; } =20 ret =3D devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component, &mchp_pdmc_dai, 1); if (ret) { dev_err(dev, "could not register CPU DAI: %d\n", ret); - return ret; + goto pm_runtime_suspend; } =20 /* print IP version */ @@ -1059,6 +1076,25 @@ static int mchp_pdmc_probe(struct platform_device *p= dev) version & MCHP_PDMC_VER_VERSION); =20 return 0; + +pm_runtime_suspend: + if (!pm_runtime_status_suspended(dd->dev)) + mchp_pdmc_runtime_suspend(dd->dev); + pm_runtime_disable(dd->dev); + + return ret; +} + +static int mchp_pdmc_remove(struct platform_device *pdev) +{ + struct mchp_pdmc *dd =3D platform_get_drvdata(pdev); + + if (!pm_runtime_status_suspended(dd->dev)) + mchp_pdmc_runtime_suspend(dd->dev); + + pm_runtime_disable(dd->dev); + + return 0; } =20 static const struct of_device_id mchp_pdmc_of_match[] =3D { @@ -1070,13 +1106,19 @@ static const struct of_device_id mchp_pdmc_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match); =20 +static const struct dev_pm_ops mchp_pdmc_pm_ops =3D { + RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume, + NULL) +}; + static struct platform_driver mchp_pdmc_driver =3D { .driver =3D { .name =3D "mchp-pdmc", .of_match_table =3D of_match_ptr(mchp_pdmc_of_match), - .pm =3D &snd_soc_pm_ops, + .pm =3D pm_ptr(&mchp_pdmc_pm_ops), }, .probe =3D mchp_pdmc_probe, + .remove =3D mchp_pdmc_remove, }; module_platform_driver(mchp_pdmc_driver); =20 --=20 2.34.1 From nobody Thu Sep 18 01:20:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48DF9C4332F for ; Tue, 13 Dec 2022 11:24:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235208AbiLMLYX (ORCPT ); Tue, 13 Dec 2022 06:24:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235309AbiLMLXp (ORCPT ); Tue, 13 Dec 2022 06:23:45 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67BFE13F45; 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Tue, 13 Dec 2022 04:23:42 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 13 Dec 2022 04:23:39 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 3/4] ASoC: mchp-pdmc: add support for suspend to RAM Date: Tue, 13 Dec 2022 13:28:50 +0200 Message-ID: <20221213112851.89212-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221213112851.89212-1-claudiu.beznea@microchip.com> References: <20221213112851.89212-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for suspend to RAM by re-aranging the lines in switch..case from mchp_pdmc_trigger() and saving/restoring the enabled interrupts. These are necessary as AT91 devices has a special power saving mode (called backup and self-refresh) where most of the SoC parts are powered off and thus we need to reconfigure the PDMC on resume. Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-pdmc.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/sound/soc/atmel/mchp-pdmc.c b/sound/soc/atmel/mchp-pdmc.c index f184404e74e5..cf4084dcbd5e 100644 --- a/sound/soc/atmel/mchp-pdmc.c +++ b/sound/soc/atmel/mchp-pdmc.c @@ -113,6 +113,7 @@ struct mchp_pdmc { struct clk *pclk; struct clk *gclk; u32 pdmcen; + u32 suspend_irq; int mic_no; int sinc_order; bool audio_filter_en; @@ -641,22 +642,27 @@ static int mchp_pdmc_trigger(struct snd_pcm_substream= *substream, #endif =20 switch (cmd) { - case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: - case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + case SNDRV_PCM_TRIGGER_START: /* Enable overrun and underrun error interrupts */ - regmap_write(dd->regmap, MCHP_PDMC_IER, + regmap_write(dd->regmap, MCHP_PDMC_IER, dd->suspend_irq | MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); + dd->suspend_irq =3D 0; + fallthrough; + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, MCHP_PDMC_MR_PDMCEN_MASK, dd->pdmcen); break; - case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: - case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + regmap_read(dd->regmap, MCHP_PDMC_IMR, &dd->suspend_irq); + fallthrough; + case SNDRV_PCM_TRIGGER_STOP: /* Disable overrun and underrun error interrupts */ - regmap_write(dd->regmap, MCHP_PDMC_IDR, + regmap_write(dd->regmap, MCHP_PDMC_IDR, dd->suspend_irq | MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR); + fallthrough; + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: snd_soc_component_update_bits(cpu, MCHP_PDMC_MR, MCHP_PDMC_MR_PDMCEN_MASK, 0); break; @@ -1107,6 +1113,7 @@ static const struct of_device_id mchp_pdmc_of_match[]= =3D { MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match); =20 static const struct dev_pm_ops mchp_pdmc_pm_ops =3D { + SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume, NULL) }; --=20 2.34.1 From nobody Thu Sep 18 01:20:24 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E041C4708E for ; Tue, 13 Dec 2022 11:24:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235317AbiLMLYe (ORCPT ); Tue, 13 Dec 2022 06:24:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235343AbiLMLXw (ORCPT ); Tue, 13 Dec 2022 06:23:52 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B7CC13F38; Tue, 13 Dec 2022 03:23:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1670930628; x=1702466628; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5xjzRZVtRE1cVlsbZZS0eIcjhBI2JgzIzQmwqEVYM3I=; b=f6RJhkpyAF08NSBjqTdnuVp0NA+nyExxAyi3XrBbq7SwJqqyEkhUtWVe 0X8sMtG3p6JGNy+7iMETbHJ/ySk8XMyDM+jGUMFLysK3igkHb39g/LPnf L1yvSoG+8aIvKyeENOhyugUxIn4x/lyYKblyIdHiN4idroRzMvmmSKp/N 3vtY9rr8Dq8oSduNU6Sf9pch0rTwOIjbt3k7Huup/wzNITQQYHlHaPGlN pcT/4z2DdPNYTwL7nvgGwqAIOuw70gQf0/TAlcYm7vd6q9Q1AKD2bJo5G Kn+ZGN2MBVv3t3DqVFL1ppFUG9/uLn4aYT0pQy9UnOcCutTa8y5TMUCkK w==; X-IronPort-AV: E=Sophos;i="5.96,241,1665471600"; d="scan'208";a="191416487" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Dec 2022 04:23:47 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 13 Dec 2022 04:23:45 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Tue, 13 Dec 2022 04:23:42 -0700 From: Claudiu Beznea To: , , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v3 4/4] ASoC: mchp-spdiftx: use FIELD_PREP() where possible Date: Tue, 13 Dec 2022 13:28:51 +0200 Message-ID: <20221213112851.89212-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20221213112851.89212-1-claudiu.beznea@microchip.com> References: <20221213112851.89212-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use FIELD_PREP() in macro definitions. Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-spdiftx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/atmel/mchp-spdiftx.c b/sound/soc/atmel/mchp-spdiftx.c index dc96a6fbf514..20d135c718b0 100644 --- a/sound/soc/atmel/mchp-spdiftx.c +++ b/sound/soc/atmel/mchp-spdiftx.c @@ -6,6 +6,7 @@ // // Author: Codrin Ciubotariu =20 +#include #include #include #include @@ -71,11 +72,11 @@ =20 /* Valid Bits per Sample */ #define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8) -#define SPDIFTX_MR_VBPS(bps) (((bps) << 8) & SPDIFTX_MR_VBPS_MASK) +#define SPDIFTX_MR_VBPS(bps) FIELD_PREP(SPDIFTX_MR_VBPS_MASK, bps) =20 /* Chunk Size */ #define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16) -#define SPDIFTX_MR_CHUNK(size) (((size) << 16) & SPDIFTX_MR_CHUNK_MASK) +#define SPDIFTX_MR_CHUNK(size) FIELD_PREP(SPDIFTX_MR_CHUNK_MASK, size) =20 /* Validity Bits for Channels 1 and 2 */ #define SPDIFTX_MR_VALID1 BIT(24) @@ -88,8 +89,7 @@ =20 /* Bytes per Sample */ #define SPDIFTX_MR_BPS_MASK GENMASK(29, 28) -#define SPDIFTX_MR_BPS(bytes) \ - ((((bytes) - 1) << 28) & SPDIFTX_MR_BPS_MASK) +#define SPDIFTX_MR_BPS(bytes) FIELD_PREP(SPDIFTX_MR_BPS_MASK, (bytes - 1)) =20 /* * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) --= -- --=20 2.34.1