From nobody Sun Sep 14 16:30:01 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D48D0C25B4E for ; Fri, 20 Jan 2023 13:19:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230446AbjATNTG (ORCPT ); Fri, 20 Jan 2023 08:19:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231144AbjATNSg (ORCPT ); Fri, 20 Jan 2023 08:18:36 -0500 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5291C383D for ; Fri, 20 Jan 2023 05:15:03 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id tz11so13975033ejc.0 for ; Fri, 20 Jan 2023 05:15:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=BwOqzf9R7uT7rGnQwy0vwJjfAeAuPeUDIWBIETds350=; b=OjovKzTl0s7/JFX7HiitnHEZbspdX38IUG1ceXIElPZKDkRS+eA34Vabe3tRlINfKY K5sxHSkmWsIVY5e0OUjACmtZi1xLfUrc+4mE4D4XNc+PEkhb3m8FoX4F1djXtXSp7xz7 NIBu2PLX7zirMHAbm180RpXt+N/zM1CzQ+bj1tBMOaYJsCVYNJCmujv1D8wTpkK1+LyK fIKLvF3sBdwuSzikosEuHDtmnIcAFvmH1jaXKggHzmpjDORUf3DQ/XgXUYn4ljO/Rvfz FBaHmsxeET5pNU4/NI7ECdceoeeh1muHBhbc+5tUz1mSaHBbp28ZtBjV+MA3kr7oFtS0 WjQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BwOqzf9R7uT7rGnQwy0vwJjfAeAuPeUDIWBIETds350=; b=LVD7/z7qcsA4BhNhh5/j2R4P8tKgrMilXGTm8xlfGDzKCxXB0wACgxccJQaFLGrHKK thp82kicYMSE3FSw1GYwuPUMpMjPgzTWOpn1+euwiZ9xmHl9aPeqZ78hmPSIHKyqqWGx IdBbb+sz0HChiSCXKv5WoyklrUj3fYsTyg2xSXHOro97+rioiNjB19VuT2dXmswTTUdP 2c+DNO0xcpx3SI8dpEJnP1GKAbQsUMnrRX3qIcbNT+sQxL4dkbAS/j/+FoO0l+C7QaGI xTOyN56mxlD3uIQB9OiIPY2ophyinyJkYZRa4JmKnF8kibafS0ClyHMbWmtkkFVEusGd ewKw== X-Gm-Message-State: AFqh2krOVtlNcz6DAiOwzqI5hPB+KO6tnUHXTT2tU9nPQWQAPHVIggp/ e6hu4z2U5gso3cQtfdaM2Kl4dU0dLY7mQhGjPLgugQ== X-Google-Smtp-Source: AMrXdXvL7IOr4H2KuxOoBPBNi6gt8ip/qp3X831ZZU8m1YHLRc4xw18f1Jf0RLbF06drPMGSU3EO0A== X-Received: by 2002:a17:906:60d0:b0:877:612e:516e with SMTP id f16-20020a17090660d000b00877612e516emr29754553ejk.61.1674220493307; Fri, 20 Jan 2023 05:14:53 -0800 (PST) Received: from [172.16.220.87] (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id t1-20020a1709061be100b0086f40238403sm8063276ejg.223.2023.01.20.05.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 05:14:53 -0800 (PST) From: Luca Weiss Date: Fri, 20 Jan 2023 14:13:46 +0100 Subject: [PATCH v2 3/4] arm64: dts: qcom: sm6350: Add CCI nodes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221213-sm6350-cci-v2-3-15c2c14c34bb@fairphone.com> References: <20221213-sm6350-cci-v2-0-15c2c14c34bb@fairphone.com> In-Reply-To: <20221213-sm6350-cci-v2-0-15c2c14c34bb@fairphone.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Loic Poulain , Robert Foss , Rob Herring , Krzysztof Kozlowski Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12-dev-78462 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add nodes for the two CCI blocks found on SM6350. The first contains two i2c busses and while the second one might also contains two busses, the downstream kernel only has one configured, and some boards use the GPIOs for the potential cci1_i2c1 one other purposes, so leave that one unconfigured. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 132 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 132 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 300ced5cda57..802d7f494162 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -1435,6 +1436,95 @@ usb_1_dwc3: usb@a600000 { }; }; =20 + cci0: cci@ac4a000 { + compatible =3D "qcom,sm6350-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac4a000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>, + <&camcc CAMCC_CCI_0_CLK_SRC>; + clock-names =3D "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CCI_0_CLK>; + assigned-clock-rates =3D <80000000>, <37500000>; + + pinctrl-0 =3D <&cci0_default &cci1_default>; + pinctrl-1 =3D <&cci0_sleep &cci1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible =3D "qcom,sm6350-cci", "qcom,msm8996-cci"; + reg =3D <0 0x0ac4b000 0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>, + <&camcc CAMCC_CCI_1_CLK_SRC>; + clock-names =3D "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks =3D <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CCI_1_CLK>; + assigned-clock-rates =3D <80000000>, <37500000>; + + pinctrl-0 =3D <&cci2_default>; + pinctrl-1 =3D <&cci2_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstrea= m */ + }; + camcc: clock-controller@ad00000 { compatible =3D "qcom,sm6350-camcc"; reg =3D <0 0x0ad00000 0 0x16000>; @@ -1522,6 +1612,48 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; gpio-ranges =3D <&tlmm 0 0 157>; =20 + cci0_default: cci0-default-state { + pins =3D "gpio39", "gpio40"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins =3D "gpio39", "gpio40"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins =3D "gpio41", "gpio42"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins =3D "gpio41", "gpio42"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci2_default: cci2-default-state { + pins =3D "gpio43", "gpio44"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up; + }; + + cci2_sleep: cci2-sleep-state { + pins =3D "gpio43", "gpio44"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + sdc2_off_state: sdc2-off-state { clk-pins { pins =3D "sdc2_clk"; --=20 2.39.1